include/asm-blackfin/mach-bf533/irq.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf533/defBF532.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *
  13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; see the file COPYING.
  27  * If not, write to the Free Software Foundation,
  28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 #ifndef _BF533_IRQ_H_
  32 #define _BF533_IRQ_H_
  33
  34 /*
  35  * Interrupt source definitions
  36              Event Source    Core Event Name
  37 Core        Emulation               **
  38  Events         (highest priority)  EMU         0
  39             Reset                   RST         1
  40             NMI                     NMI         2
  41             Exception               EVX         3
  42             Reserved                --          4
  43             Hardware Error          IVHW        5
  44             Core Timer              IVTMR       6 *
  45             PLL Wakeup Interrupt    IVG7        7
  46             DMA Error (generic)     IVG7        8
  47             PPI Error Interrupt     IVG7        9
  48             SPORT0 Error Interrupt  IVG7        10
  49             SPORT1 Error Interrupt  IVG7        11
  50             SPI Error Interrupt     IVG7        12
  51             UART Error Interrupt    IVG7        13
  52             RTC Interrupt           IVG8        14
  53             DMA0 Interrupt (PPI)    IVG8        15
  54             DMA1 (SPORT0 RX)        IVG9        16
  55             DMA2 (SPORT0 TX)        IVG9        17
  56             DMA3 (SPORT1 RX)        IVG9        18
  57             DMA4 (SPORT1 TX)        IVG9        19
  58             DMA5 (PPI)              IVG10       20
  59             DMA6 (UART RX)          IVG10       21
  60             DMA7 (UART TX)          IVG10       22
  61             Timer0                  IVG11       23
  62             Timer1                  IVG11       24
  63             Timer2                  IVG11       25
  64             PF Interrupt A          IVG12       26
  65             PF Interrupt B          IVG12       27
  66             DMA8/9 Interrupt        IVG13       28
  67             DMA10/11 Interrupt      IVG13       29
  68             Watchdog Timer          IVG13       30
  69             Software Interrupt 1    IVG14       31
  70             Software Interrupt 2    --
  71                  (lowest priority)  IVG15       32 *
  72  */
  73 #define SYS_IRQS                32
  74 #define NR_PERI_INTS    24
  75
  76 /* The ABSTRACT IRQ definitions */
  77 /** the first seven of the following are fixed, the rest you change if you need to **/
  78 #define IRQ_EMU                 0       /*Emulation */
  79 #define IRQ_RST                 1       /*reset */
  80 #define IRQ_NMI                 2       /*Non Maskable */
  81 #define IRQ_EVX                 3       /*Exception */
  82 #define IRQ_UNUSED              4       /*- unused interrupt*/
  83 #define IRQ_HWERR               5       /*Hardware Error */
  84 #define IRQ_CORETMR             6       /*Core timer */
  85
  86 #define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
  87 #define IRQ_DMA_ERROR           8       /*DMA Error (general) */
  88 #define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
  89 #define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
  90 #define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
  91 #define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
  92 #define IRQ_UART_ERROR          13      /*UART Error Interrupt */
  93 #define IRQ_RTC                 14      /*RTC Interrupt */
  94 #define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
  95 #define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
  96 #define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
  97 #define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
  98 #define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
  99 #define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
 100 #define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
 101 #define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
 102 #define IRQ_TMR0                23      /*Timer 0 */
 103 #define IRQ_TMR1                24      /*Timer 1 */
 104 #define IRQ_TMR2                25      /*Timer 2 */
 105 #define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
 106 #define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
 107 #define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
 108 #define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
 109 #define IRQ_WATCH               30      /*Watch Dog Timer */
 110
 111 #define IRQ_SW_INT1             31      /*Software Int 1 */
 112 #define IRQ_SW_INT2             32      /*Software Int 2 (reserved for SYSCALL) */
 113
 114 #define IRQ_PF0                 33
 115 #define IRQ_PF1                 34
 116 #define IRQ_PF2                 35
 117 #define IRQ_PF3                 36
 118 #define IRQ_PF4                 37
 119 #define IRQ_PF5                 38
 120 #define IRQ_PF6                 39
 121 #define IRQ_PF7                 40
 122 #define IRQ_PF8                 41
 123 #define IRQ_PF9                 42
 124 #define IRQ_PF10                43
 125 #define IRQ_PF11                44
 126 #define IRQ_PF12                45
 127 #define IRQ_PF13                46
 128 #define IRQ_PF14                47
 129 #define IRQ_PF15                48
 130
 131 #define GPIO_IRQ_BASE           IRQ_PF0
 132
 133 #define NR_IRQS         (IRQ_PF15+1)
 134
 135 #define IVG7                    7
 136 #define IVG8                    8
 137 #define IVG9                    9
 138 #define IVG10                   10
 139 #define IVG11                   11
 140 #define IVG12                   12
 141 #define IVG13                   13
 142 #define IVG14                   14
 143 #define IVG15                   15
 144
 145 /* IAR0 BIT FIELDS*/
 146 #define RTC_ERROR_POS                   28
 147 #define UART_ERROR_POS                  24
 148 #define SPORT1_ERROR_POS                20
 149 #define SPI_ERROR_POS                   16
 150 #define SPORT0_ERROR_POS                12
 151 #define PPI_ERROR_POS                   8
 152 #define DMA_ERROR_POS                   4
 153 #define PLLWAKE_ERROR_POS               0
 154
 155 /* IAR1 BIT FIELDS*/
 156 #define DMA7_UARTTX_POS                 28
 157 #define DMA6_UARTRX_POS                 24
 158 #define DMA5_SPI_POS                    20
 159 #define DMA4_SPORT1TX_POS               16
 160 #define DMA3_SPORT1RX_POS               12
 161 #define DMA2_SPORT0TX_POS               8
 162 #define DMA1_SPORT0RX_POS               4
 163 #define DMA0_PPI_POS                    0
 164
 165 /* IAR2 BIT FIELDS*/
 166 #define WDTIMER_POS                     28
 167 #define MEMDMA1_POS                     24
 168 #define MEMDMA0_POS                     20
 169 #define PFB_POS                         16
 170 #define PFA_POS                         12
 171 #define TIMER2_POS                      8
 172 #define TIMER1_POS                      4
 173 #define TIMER0_POS                      0
 174
 175 #endif                          /* _BF533_IRQ_H_ */