include/asm-blackfin/mach-bf548/bfin_serial_5xx.h

   1 #include <linux/serial.h>
   2 #include <asm/dma.h>
   3 #include <asm/portmux.h>
   4
   5 #define NR_PORTS                4
   6
   7 #define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
   8 #define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
   9 #define OFFSET_GCTL             0x08    /* Global Control Register              */
  10 #define OFFSET_LCR              0x0C    /* Line Control Register                */
  11 #define OFFSET_MCR              0x10    /* Modem Control Register               */
  12 #define OFFSET_LSR              0x14    /* Line Status Register                 */
  13 #define OFFSET_MSR              0x18    /* Modem Status Register                */
  14 #define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
  15 #define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
  16 #define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
  17 #define OFFSET_THR              0x28    /* Transmit Holding register            */
  18 #define OFFSET_RBR              0x2C    /* Receive Buffer register              */
  19
  20 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  21 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  22 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  23 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
  24 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  25 #define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
  26 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  27 <<<<<<< HEAD:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  28 =======
  29 #define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
  30 #define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
  31 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  32
  33 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  34 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  35 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
  36 #define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
  37 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  38 #define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
  39 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  40 <<<<<<< HEAD:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  41 =======
  42 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
  43 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  44 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  45 <<<<<<< HEAD:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  46 =======
  47 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
  48 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  49
  50 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
  51 # define CONFIG_SERIAL_BFIN_CTSRTS
  52
  53 # ifndef CONFIG_UART0_CTS_PIN
  54 #  define CONFIG_UART0_CTS_PIN -1
  55 # endif
  56
  57 # ifndef CONFIG_UART0_RTS_PIN
  58 #  define CONFIG_UART0_RTS_PIN -1
  59 # endif
  60
  61 # ifndef CONFIG_UART1_CTS_PIN
  62 #  define CONFIG_UART1_CTS_PIN -1
  63 # endif
  64
  65 # ifndef CONFIG_UART1_RTS_PIN
  66 #  define CONFIG_UART1_RTS_PIN -1
  67 # endif
  68 #endif
  69 /*
  70  * The pin configuration is different from schematic
  71  */
  72 struct bfin_serial_port {
  73         struct uart_port        port;
  74         unsigned int            old_status;
  75 #ifdef CONFIG_SERIAL_BFIN_DMA
  76         int                     tx_done;
  77         int                     tx_count;
  78         struct circ_buf         rx_dma_buf;
  79         struct timer_list       rx_dma_timer;
  80         int                     rx_dma_nrows;
  81         unsigned int            tx_dma_channel;
  82         unsigned int            rx_dma_channel;
  83         struct work_struct      tx_dma_workqueue;
  84 <<<<<<< HEAD:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  85 #else
  86         struct work_struct      cts_workqueue;
  87 =======
  88 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  89 #endif
  90 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  91 <<<<<<< HEAD:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  92 =======
  93         struct work_struct      cts_workqueue;
  94 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
  95         int             cts_pin;
  96         int             rts_pin;
  97 #endif
  98 };
  99
 100 struct bfin_serial_port bfin_serial_ports[NR_PORTS];
 101 struct bfin_serial_res {
 102         unsigned long   uart_base_addr;
 103         int             uart_irq;
 104 #ifdef CONFIG_SERIAL_BFIN_DMA
 105         unsigned int    uart_tx_dma_channel;
 106         unsigned int    uart_rx_dma_channel;
 107 #endif
 108 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 109         int     uart_cts_pin;
 110         int     uart_rts_pin;
 111 #endif
 112 };
 113
 114 struct bfin_serial_res bfin_serial_resource[] = {
 115 #ifdef CONFIG_SERIAL_BFIN_UART0
 116         {
 117         0xFFC00400,
 118         IRQ_UART0_RX,
 119 #ifdef CONFIG_SERIAL_BFIN_DMA
 120         CH_UART0_TX,
 121         CH_UART0_RX,
 122 #endif
 123 #ifdef CONFIG_BFIN_UART0_CTSRTS
 124         CONFIG_UART0_CTS_PIN,
 125         CONFIG_UART0_RTS_PIN,
 126 #endif
 127         },
 128 #endif
 129 #ifdef CONFIG_SERIAL_BFIN_UART1
 130         {
 131         0xFFC02000,
 132         IRQ_UART1_RX,
 133 #ifdef CONFIG_SERIAL_BFIN_DMA
 134         CH_UART1_TX,
 135         CH_UART1_RX,
 136 #endif
 137         },
 138 #endif
 139 #ifdef CONFIG_SERIAL_BFIN_UART2
 140         {
 141         0xFFC02100,
 142         IRQ_UART2_RX,
 143 #ifdef CONFIG_SERIAL_BFIN_DMA
 144         CH_UART2_TX,
 145         CH_UART2_RX,
 146 #endif
 147 #ifdef CONFIG_BFIN_UART2_CTSRTS
 148         CONFIG_UART2_CTS_PIN,
 149         CONFIG_UART2_RTS_PIN,
 150 #endif
 151         },
 152 #endif
 153 #ifdef CONFIG_SERIAL_BFIN_UART3
 154         {
 155         0xFFC03100,
 156         IRQ_UART3_RX,
 157 #ifdef CONFIG_SERIAL_BFIN_DMA
 158         CH_UART3_TX,
 159         CH_UART3_RX,
 160 #endif
 161         },
 162 #endif
 163 };
 164
 165 int nr_ports = ARRAY_SIZE(bfin_serial_resource);
 166
 167 #define DRIVER_NAME "bfin-uart"
 168
 169 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 170 {
 171 #ifdef CONFIG_SERIAL_BFIN_UART0
 172         peripheral_request(P_UART0_TX, DRIVER_NAME);
 173         peripheral_request(P_UART0_RX, DRIVER_NAME);
 174 #endif
 175
 176 #ifdef CONFIG_SERIAL_BFIN_UART1
 177         peripheral_request(P_UART1_TX, DRIVER_NAME);
 178         peripheral_request(P_UART1_RX, DRIVER_NAME);
 179
 180 #ifdef CONFIG_BFIN_UART1_CTSRTS
 181         peripheral_request(P_UART1_RTS, DRIVER_NAME);
 182         peripheral_request(P_UART1_CTS DRIVER_NAME);
 183 #endif
 184 #endif
 185
 186 #ifdef CONFIG_SERIAL_BFIN_UART2
 187         peripheral_request(P_UART2_TX, DRIVER_NAME);
 188         peripheral_request(P_UART2_RX, DRIVER_NAME);
 189 #endif
 190
 191 #ifdef CONFIG_SERIAL_BFIN_UART3
 192         peripheral_request(P_UART3_TX, DRIVER_NAME);
 193         peripheral_request(P_UART3_RX, DRIVER_NAME);
 194
 195 #ifdef CONFIG_BFIN_UART3_CTSRTS
 196         peripheral_request(P_UART3_RTS, DRIVER_NAME);
 197         peripheral_request(P_UART3_CTS DRIVER_NAME);
 198 #endif
 199 #endif
 200         SSYNC();
 201 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 202         if (uart->cts_pin >= 0) {
 203                 gpio_request(uart->cts_pin, DRIVER_NAME);
 204                 gpio_direction_input(uart->cts_pin);
 205         }
 206
 207         if (uart->rts_pin >= 0) {
 208                 gpio_request(uart->rts_pin, DRIVER_NAME);
 209                 gpio_direction_output(uart->rts_pin, 0);
 210         }
 211 #endif
 212 }