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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / include / asm-blackfin / mach-common / def_LPBlackfin.h
blobe8967f6124f7ea2eb0a3878ec9fbc70c142e9c9d
1 /*
2 * File: include/asm-blackfin/mach-common/def_LPBlackfin.h
3 * Based on:
4 * Author: unknown
5 * COPYRIGHT 2005 Analog Devices
6 * Created: ?
7 * Description:
8 *
9 * Modified:
10 *
11 * Bugs: Enter bugs at http://blackfin.uclinux.org/
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING.
25 * If not, write to the Free Software Foundation,
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29 /* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
30
31 #ifndef _DEF_LPBLACKFIN_H
32 #define _DEF_LPBLACKFIN_H
33
34 #include <asm/mach/anomaly.h>
35
36 #define MK_BMSK_(x) (1<<x)
37
38 #ifndef __ASSEMBLY__
39
40 #include <linux/types.h>
41
42 #if ANOMALY_05000198
43 # define NOP_PAD_ANOMALY_05000198 "nop;"
44 #else
45 # define NOP_PAD_ANOMALY_05000198
46 #endif
47
48 #define bfin_read8(addr) ({ \
49 uint32_t __v; \
50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \
53 : "=d" (__v) \
54 : "a" (addr) \
55 ); \
56 __v; })
57
58 #define bfin_read16(addr) ({ \
59 uint32_t __v; \
60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \
63 : "=d" (__v) \
64 : "a" (addr) \
65 ); \
66 __v; })
67
68 #define bfin_read32(addr) ({ \
69 uint32_t __v; \
70 __asm__ __volatile__( \
71 NOP_PAD_ANOMALY_05000198 \
72 "%0 = [%1];" \
73 : "=d" (__v) \
74 : "a" (addr) \
75 ); \
76 __v; })
77
78 #define bfin_write8(addr, val) \
79 __asm__ __volatile__( \
80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \
82 : \
83 : "a" (addr), "d" ((uint8_t)(val)) \
84 : "memory" \
85 )
86
87 #define bfin_write16(addr, val) \
88 __asm__ __volatile__( \
89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \
91 : \
92 : "a" (addr), "d" ((uint16_t)(val)) \
93 : "memory" \
94 )
95
96 #define bfin_write32(addr, val) \
97 __asm__ __volatile__( \
98 NOP_PAD_ANOMALY_05000198 \
99 "[%0] = %1;" \
100 : \
101 : "a" (addr), "d" (val) \
102 : "memory" \
103 )
104
105 #endif /* __ASSEMBLY__ */
106
107 /**************************************************
108 * System Register Bits
109 **************************************************/
110
111 /**************************************************
112 * ASTAT register
113 **************************************************/
114
115 /* definitions of ASTAT bit positions*/
116
117 /*Result of last ALU0 or shifter operation is zero*/
118 #define ASTAT_AZ_P 0x00000000
119 /*Result of last ALU0 or shifter operation is negative*/
120 #define ASTAT_AN_P 0x00000001
121 /*Condition Code, used for holding comparison results*/
122 #define ASTAT_CC_P 0x00000005
123 /*Quotient Bit*/
124 #define ASTAT_AQ_P 0x00000006
125 /*Rounding mode, set for biased, clear for unbiased*/
126 #define ASTAT_RND_MOD_P 0x00000008
127 /*Result of last ALU0 operation generated a carry*/
128 #define ASTAT_AC0_P 0x0000000C
129 /*Result of last ALU0 operation generated a carry*/
130 #define ASTAT_AC0_COPY_P 0x00000002
131 /*Result of last ALU1 operation generated a carry*/
132 #define ASTAT_AC1_P 0x0000000D
133 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
134 #define ASTAT_AV0_P 0x00000010
135 /*Sticky version of ASTAT_AV0 */
136 #define ASTAT_AV0S_P 0x00000011
137 /*Result of last MAC1 operation overflowed, sticky for MAC*/
138 #define ASTAT_AV1_P 0x00000012
139 /*Sticky version of ASTAT_AV1 */
140 #define ASTAT_AV1S_P 0x00000013
141 /*Result of last ALU0 or MAC0 operation overflowed*/
142 #define ASTAT_V_P 0x00000018
143 /*Result of last ALU0 or MAC0 operation overflowed*/
144 #define ASTAT_V_COPY_P 0x00000003
145 /*Sticky version of ASTAT_V*/
146 #define ASTAT_VS_P 0x00000019
147
148 /* Masks */
149
150 /*Result of last ALU0 or shifter operation is zero*/
151 #define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P)
152 /*Result of last ALU0 or shifter operation is negative*/
153 #define ASTAT_AN MK_BMSK_(ASTAT_AN_P)
154 /*Result of last ALU0 operation generated a carry*/
155 #define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P)
156 /*Result of last ALU0 operation generated a carry*/
157 #define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P)
158 /*Result of last ALU0 operation generated a carry*/
159 #define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P)
160 /*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
161 #define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P)
162 /*Result of last MAC1 operation overflowed, sticky for MAC*/
163 #define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P)
164 /*Condition Code, used for holding comparison results*/
165 #define ASTAT_CC MK_BMSK_(ASTAT_CC_P)
166 /*Quotient Bit*/
167 #define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P)
168 /*Rounding mode, set for biased, clear for unbiased*/
169 #define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P)
170 /*Overflow Bit*/
171 #define ASTAT_V MK_BMSK_(ASTAT_V_P)
172 /*Overflow Bit*/
173 #define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P)
174
175 /**************************************************
176 * SEQSTAT register
177 **************************************************/
178
179 /* Bit Positions */
180 #define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
181 #define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
182 #define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
183 #define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
184 #define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
185 #define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
186 #define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request,
187 * set by IDLE instruction.
188 */
189 #define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last
190 * reset was a software reset
191 * (=1)
192 */
193 #define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
194 #define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
195 #define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
196 #define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
197 #define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
198 /* Masks */
199 /* Exception cause */
200 #define SEQSTAT_EXCAUSE (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
201 MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
202 MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
203 MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
204 MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
205 MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
206 0)
207
208 /* Indicates whether the last reset was a software reset (=1) */
209 #define SEQSTAT_SFTRESET (MK_BMSK_(SEQSTAT_SFTRESET_P))
210
211 /* Last hw error cause */
212 #define SEQSTAT_HWERRCAUSE (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
213 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
214 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
215 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
216 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
217 0)
218
219 /* Translate bits to something useful */
220
221 /* Last hw error cause */
222 #define SEQSTAT_HWERRCAUSE_SHIFT (14)
223 #define SEQSTAT_HWERRCAUSE_SYSTEM_MMR (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
224 #define SEQSTAT_HWERRCAUSE_EXTERN_ADDR (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
225 #define SEQSTAT_HWERRCAUSE_PERF_FLOW (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
226 #define SEQSTAT_HWERRCAUSE_RAISE_5 (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
227
228 /**************************************************
229 * SYSCFG register
230 **************************************************/
231
232 /* Bit Positions */
233 #define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when
234 * set it forces an exception
235 * for each instruction executed
236 */
237 #define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
238 #define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
239
240 /* Masks */
241
242 /* Supervisor single step, when set it forces an exception for each
243 *instruction executed
244 */
245 #define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P )
246 /* Enable cycle counter (=1) */
247 #define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P )
248 /* Self Nesting Interrupt Enable */
249 #define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P)
250 /* Backward-compatibility for typos in prior releases */
251 #define SYSCFG_SSSSTEP SYSCFG_SSSTEP
252 #define SYSCFG_CCCEN SYSCFG_CCEN
253
254 /****************************************************
255 * Core MMR Register Map
256 ****************************************************/
257
258 /* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
259
260 #define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
261 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */
262 #define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside
263 * Buffer Status
264 */
265 #define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
266 #define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside
267 * Buffer Fault Address
268 */
269 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside
270 * Buffer 0
271 */
272 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside
273 * Buffer 1
274 */
275 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside
276 * Buffer 2
277 */
278 #define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection
279 * Lookaside Buffer 3
280 */
281 #define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection
282 * Lookaside Buffer 4
283 */
284 #define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection
285 * Lookaside Buffer 5
286 */
287 #define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection
288 * Lookaside Buffer 6
289 */
290 #define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection
291 * Lookaside Buffer 7
292 */
293 #define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection
294 * Lookaside Buffer 8
295 */
296 #define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection
297 * Lookaside Buffer 9
298 */
299 #define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection
300 * Lookaside Buffer 10
301 */
302 #define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection
303 * Lookaside Buffer 11
304 */
305 #define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection
306 * Lookaside Buffer 12
307 */
308 #define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection
309 * Lookaside Buffer 13
310 */
311 #define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection
312 * Lookaside Buffer 14
313 */
314 #define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection
315 * Lookaside Buffer 15
316 */
317 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
318 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
319 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
320 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
321 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
322 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
323 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
324 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
325 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
326 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
327 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
328 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
329 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
330 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
331 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
332 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
333 #define DCPLB_DATA16 0xFFE00240 /* Extra Dummy entry */
334
335 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
336 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
337 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
338
339 /* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
340
341 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
342 #define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
343 #define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
344 #define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
345 #define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
346 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability
347 * Protection Lookaside Buffer 0
348 */
349 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability
350 * Protection Lookaside Buffer 1
351 */
352 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability
353 * Protection Lookaside Buffer 2
354 */
355 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability
356 * Protection Lookaside Buffer 3
357 */
358 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability
359 * Protection Lookaside Buffer 4
360 */
361 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability
362 * Protection Lookaside Buffer 5
363 */
364 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability
365 * Protection Lookaside Buffer 6
366 */
367 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability
368 * Protection Lookaside Buffer 7
369 */
370 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability
371 * Protection Lookaside Buffer 8
372 */
373 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability
374 * Protection Lookaside Buffer 9
375 */
376 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability
377 * Protection Lookaside Buffer 10
378 */
379 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability
380 * Protection Lookaside Buffer 11
381 */
382 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability
383 * Protection Lookaside Buffer 12
384 */
385 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability
386 * Protection Lookaside Buffer 13
387 */
388 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability
389 * Protection Lookaside Buffer 14
390 */
391 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability
392 * Protection Lookaside Buffer 15
393 */
394 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
395 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
396 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
397 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
398 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
399 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
400 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
401 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
402 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
403 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
404 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
405 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
406 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
407 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
408 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
409 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
410 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
411 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
412 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
413
414 /* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
415
416 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
417 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
418 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
419 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
420 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
421 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
422 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
423 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
424 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
425 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
426 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
427 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
428 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
429 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
430 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
431 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
432 #define IMASK 0xFFE02104 /* Interrupt Mask Register */
433 #define IPEND 0xFFE02108 /* Interrupt Pending Register */
434 #define ILAT 0xFFE0210C /* Interrupt Latch Register */
435 #define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
436
437 /* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
438
439 #define TCNTL 0xFFE03000 /* Core Timer Control Register */
440 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */
441 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */
442 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */
443
444 /* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
445 #define DSPID 0xFFE05000 /* DSP Processor ID Register for
446 * MP implementations
447 */
448
449 #define DBGSTAT 0xFFE05008 /* Debug Status Register */
450
451 /* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
452
453 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
454 #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
455 #define TBUF 0xFFE06100 /* Trace Buffer */
456
457 /* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
458
459 /* Watchpoint Instruction Address Control Register */
460 #define WPIACTL 0xFFE07000
461 /* Watchpoint Instruction Address Register 0 */
462 #define WPIA0 0xFFE07040
463 /* Watchpoint Instruction Address Register 1 */
464 #define WPIA1 0xFFE07044
465 /* Watchpoint Instruction Address Register 2 */
466 #define WPIA2 0xFFE07048
467 /* Watchpoint Instruction Address Register 3 */
468 #define WPIA3 0xFFE0704C
469 /* Watchpoint Instruction Address Register 4 */
470 #define WPIA4 0xFFE07050
471 /* Watchpoint Instruction Address Register 5 */
472 #define WPIA5 0xFFE07054
473 /* Watchpoint Instruction Address Count Register 0 */
474 #define WPIACNT0 0xFFE07080
475 /* Watchpoint Instruction Address Count Register 1 */
476 #define WPIACNT1 0xFFE07084
477 /* Watchpoint Instruction Address Count Register 2 */
478 #define WPIACNT2 0xFFE07088
479 /* Watchpoint Instruction Address Count Register 3 */
480 #define WPIACNT3 0xFFE0708C
481 /* Watchpoint Instruction Address Count Register 4 */
482 #define WPIACNT4 0xFFE07090
483 /* Watchpoint Instruction Address Count Register 5 */
484 #define WPIACNT5 0xFFE07094
485 /* Watchpoint Data Address Control Register */
486 #define WPDACTL 0xFFE07100
487 /* Watchpoint Data Address Register 0 */
488 #define WPDA0 0xFFE07140
489 /* Watchpoint Data Address Register 1 */
490 #define WPDA1 0xFFE07144
491 /* Watchpoint Data Address Count Value Register 0 */
492 #define WPDACNT0 0xFFE07180
493 /* Watchpoint Data Address Count Value Register 1 */
494 #define WPDACNT1 0xFFE07184
495 /* Watchpoint Status Register */
496 #define WPSTAT 0xFFE07200
497
498 /* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
499
500 /* Performance Monitor Control Register */
501 #define PFCTL 0xFFE08000
502 /* Performance Monitor Counter Register 0 */
503 #define PFCNTR0 0xFFE08100
504 /* Performance Monitor Counter Register 1 */
505 #define PFCNTR1 0xFFE08104
506
507 /****************************************************
508 * Core MMR Register Bits
509 ****************************************************/
510
511 /**************************************************
512 * EVT registers (ILAT, IMASK, and IPEND).
513 **************************************************/
514
515 /* Bit Positions */
516 #define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
517 #define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
518 #define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
519 #define EVT_EVX_P 0x00000003 /* Exception bit position */
520 #define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
521 #define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
522 #define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
523 #define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
524 #define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
525 #define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
526 #define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
527 #define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
528 #define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
529 #define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
530 #define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
531 #define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
532
533 /* Masks */
534 #define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
535 #define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
536 #define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
537 #define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
538 #define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
539 #define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
540 #define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
541 #define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
542 #define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
543 #define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
544 #define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
545 #define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
546 #define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
547 #define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
548 #define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
549 #define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
550
551 /**************************************************
552 * DMEM_CONTROL Register
553 **************************************************/
554 /* Bit Positions */
555 #define ENDM_P 0x00 /* (doesn't really exist) Enable
556 *Data Memory L1
557 */
558 #define DMCTL_ENDM_P ENDM_P /* "" (older define) */
559
560 #define ENDCPLB_P 0x01 /* Enable DCPLBS */
561 #define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
562 #define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
563 #define DMCTL_DMC0_P DMC0_P /* "" (older define) */
564 #define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
565 #define DMCTL_DMC1_P DMC1_P /* "" (older define) */
566 #define DCBS_P 0x04 /* L1 Data Cache Bank Select */
567 #define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
568 #define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
569
570 /* Masks */
571 #define ENDM 0x00000001 /* (doesn't really exist) Enable
572 * Data Memory L1
573 */
574 #define ENDCPLB 0x00000002 /* Enable DCPLB */
575 #define ASRAM_BSRAM 0x00000000
576 #define ACACHE_BSRAM 0x00000008
577 #define ACACHE_BCACHE 0x0000000C
578 #define DCBS 0x00000010 /* L1 Data Cache Bank Select */
579 #define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
580 #define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
581
582 /* IMEM_CONTROL Register */
583 /* Bit Positions */
584 #define ENIM_P 0x00 /* Enable L1 Code Memory */
585 #define IMCTL_ENIM_P 0x00 /* "" (older define) */
586 #define ENICPLB_P 0x01 /* Enable ICPLB */
587 #define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
588 #define IMC_P 0x02 /* Enable */
589 #define IMCTL_IMC_P 0x02 /* Configure L1 code memory as
590 * cache (0=SRAM)
591 */
592 #define ILOC0_P 0x03 /* Lock Way 0 */
593 #define ILOC1_P 0x04 /* Lock Way 1 */
594 #define ILOC2_P 0x05 /* Lock Way 2 */
595 #define ILOC3_P 0x06 /* Lock Way 3 */
596 #define LRUPRIORST_P 0x0D /* Least Recently Used Replacement
597 * Priority
598 */
599 /* Masks */
600 #define ENIM 0x00000001 /* Enable L1 Code Memory */
601 #define ENICPLB 0x00000002 /* Enable ICPLB */
602 #define IMC 0x00000004 /* Configure L1 code memory as
603 * cache (0=SRAM)
604 */
605 #define ILOC0 0x00000008 /* Lock Way 0 */
606 #define ILOC1 0x00000010 /* Lock Way 1 */
607 #define ILOC2 0x00000020 /* Lock Way 2 */
608 #define ILOC3 0x00000040 /* Lock Way 3 */
609 #define LRUPRIORST 0x00002000 /* Least Recently Used Replacement
610 * Priority
611 */
612
613 /* TCNTL Masks */
614 #define TMPWR 0x00000001 /* Timer Low Power Control,
615 * 0=low power mode, 1=active state
616 */
617 #define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
618 #define TAUTORLD 0x00000004 /* Timer auto reload */
619 #define TINT 0x00000008 /* Timer generated interrupt 0=no
620 * interrupt has been generated,
621 * 1=interrupt has been generated
622 * (sticky)
623 */
624
625 /* DCPLB_DATA and ICPLB_DATA Registers */
626 /* Bit Positions */
627 #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
628 #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry
629 * locked
630 */
631 #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access
632 * allowed (user mode)
633 */
634 /* Masks */
635 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
636 #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry
637 * locked
638 */
639 #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access
640 * allowed (user mode)
641 */
642
643 #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
644 #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
645 #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
646 #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
647 #define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
648 * mapped to L1
649 */
650 #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high
651 * priority port
652 */
653 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable
654 * in L1
655 */
656 /* ICPLB_DATA only */
657 #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line,
658 * 1=priority for non-replacement
659 */
660 /* DCPLB_DATA only */
661 #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write
662 * access allowed (user mode)
663 */
664 #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write
665 * access allowed (supervisor mode)
666 */
667 #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
668 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on
669 * write-through writes,
670 * 1= allocate cache lines on
671 * write-through writes.
672 */
673 #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
674
675 #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
676
677 /* TBUFCTL Masks */
678 #define TBUFPWR 0x0001
679 #define TBUFEN 0x0002
680 #define TBUFOVF 0x0004
681 #define TBUFCMPLP_SINGLE 0x0008
682 #define TBUFCMPLP_DOUBLE 0x0010
683 #define TBUFCMPLP (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
684
685 /* TBUFSTAT Masks */
686 #define TBUFCNT 0x001F
687
688 /* ITEST_COMMAND and DTEST_COMMAND Registers */
689 /* Masks */
690 #define TEST_READ 0x00000000 /* Read Access */
691 #define TEST_WRITE 0x00000002 /* Write Access */
692 #define TEST_TAG 0x00000000 /* Access TAG */
693 #define TEST_DATA 0x00000004 /* Access DATA */
694 #define TEST_DW0 0x00000000 /* Select Double Word 0 */
695 #define TEST_DW1 0x00000008 /* Select Double Word 1 */
696 #define TEST_DW2 0x00000010 /* Select Double Word 2 */
697 #define TEST_DW3 0x00000018 /* Select Double Word 3 */
698 #define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
699 #define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
700 #define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
701 #define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
702 #define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
703 #define TEST_WAY0 0x00000000 /* Access Way0 */
704 #define TEST_WAY1 0x04000000 /* Access Way1 */
705 /* ITEST_COMMAND only */
706 #define TEST_WAY2 0x08000000 /* Access Way2 */
707 #define TEST_WAY3 0x0C000000 /* Access Way3 */
708 /* DTEST_COMMAND only */
709 #define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
710 #define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
711
712 #endif /* _DEF_LPBLACKFIN_H */
WRT350N Kernel Patches