Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / include / asm-mips / hazards.h
blob2de638f84c86ab900f8f29e3303100abed7267ac
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
6 * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) MIPS Technologies, Inc.
8 * written by Ralf Baechle <ralf@linux-mips.org>
9 */
10 #ifndef _ASM_HAZARDS_H
11 #define _ASM_HAZARDS_H
13 #ifdef __ASSEMBLY__
14 #define ASMMACRO(name, code...) .macro name; code; .endm
15 #else
17 #include <asm/cpu-features.h>
19 #define ASMMACRO(name, code...) \
20 __asm__(".macro " #name "; " #code "; .endm"); \
22 static inline void name(void) \
23 { \
24 __asm__ __volatile__ (#name); \
28 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
30 extern void mips_ihb(void);
32 #endif
34 ASMMACRO(_ssnop,
35 sll $0, $0, 1
38 ASMMACRO(_ehb,
39 sll $0, $0, 3
43 * TLB hazards
45 #if defined(CONFIG_CPU_MIPSR2)
48 * MIPSR2 defines ehb for hazard avoidance
51 ASMMACRO(mtc0_tlbw_hazard,
52 _ehb
54 ASMMACRO(tlbw_use_hazard,
55 _ehb
57 ASMMACRO(tlb_probe_hazard,
58 _ehb
60 ASMMACRO(irq_enable_hazard,
61 _ehb
63 ASMMACRO(irq_disable_hazard,
64 _ehb
66 ASMMACRO(back_to_back_c0_hazard,
67 _ehb
70 * gcc has a tradition of misscompiling the previous construct using the
71 * address of a label as argument to inline assembler. Gas otoh has the
72 * annoying difference between la and dla which are only usable for 32-bit
73 * rsp. 64-bit code, so can't be used without conditional compilation.
74 * The alterantive is switching the assembler to 64-bit code which happens
75 * to work right even for 32-bit code ...
77 #define instruction_hazard() \
78 do { \
79 unsigned long tmp; \
81 __asm__ __volatile__( \
82 " .set mips64r2 \n" \
83 " dla %0, 1f \n" \
84 " jr.hb %0 \n" \
85 " .set mips0 \n" \
86 "1: \n" \
87 : "=r" (tmp)); \
88 } while (0)
90 #elif defined(CONFIG_CPU_MIPSR1)
93 * These are slightly complicated by the fact that we guarantee R1 kernels to
94 * run fine on R2 processors.
96 ASMMACRO(mtc0_tlbw_hazard,
97 _ssnop; _ssnop; _ehb
99 ASMMACRO(tlbw_use_hazard,
100 _ssnop; _ssnop; _ssnop; _ehb
102 ASMMACRO(tlb_probe_hazard,
103 _ssnop; _ssnop; _ssnop; _ehb
105 ASMMACRO(irq_enable_hazard,
106 _ssnop; _ssnop; _ssnop; _ehb
108 ASMMACRO(irq_disable_hazard,
109 _ssnop; _ssnop; _ssnop; _ehb
111 ASMMACRO(back_to_back_c0_hazard,
112 _ssnop; _ssnop; _ssnop; _ehb
115 * gcc has a tradition of misscompiling the previous construct using the
116 * address of a label as argument to inline assembler. Gas otoh has the
117 * annoying difference between la and dla which are only usable for 32-bit
118 * rsp. 64-bit code, so can't be used without conditional compilation.
119 * The alterantive is switching the assembler to 64-bit code which happens
120 * to work right even for 32-bit code ...
122 #define __instruction_hazard() \
123 do { \
124 unsigned long tmp; \
126 __asm__ __volatile__( \
127 " .set mips64r2 \n" \
128 " dla %0, 1f \n" \
129 " jr.hb %0 \n" \
130 " .set mips0 \n" \
131 "1: \n" \
132 : "=r" (tmp)); \
133 } while (0)
135 #define instruction_hazard() \
136 do { \
137 if (cpu_has_mips_r2) \
138 __instruction_hazard(); \
139 } while (0)
141 #elif defined(CONFIG_CPU_R10000)
144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
147 ASMMACRO(mtc0_tlbw_hazard,
149 ASMMACRO(tlbw_use_hazard,
151 ASMMACRO(tlb_probe_hazard,
153 ASMMACRO(irq_enable_hazard,
155 ASMMACRO(irq_disable_hazard,
157 ASMMACRO(back_to_back_c0_hazard,
159 #define instruction_hazard() do { } while (0)
161 #elif defined(CONFIG_CPU_RM9000)
164 * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
165 * use of the JTLB for instructions should not occur for 4 cpu cycles and use
166 * for data translations should not occur for 3 cpu cycles.
169 ASMMACRO(mtc0_tlbw_hazard,
170 _ssnop; _ssnop; _ssnop; _ssnop
172 ASMMACRO(tlbw_use_hazard,
173 _ssnop; _ssnop; _ssnop; _ssnop
175 ASMMACRO(tlb_probe_hazard,
176 _ssnop; _ssnop; _ssnop; _ssnop
178 ASMMACRO(irq_enable_hazard,
180 ASMMACRO(irq_disable_hazard,
182 ASMMACRO(back_to_back_c0_hazard,
184 #define instruction_hazard() do { } while (0)
186 #elif defined(CONFIG_CPU_SB1)
189 * Mostly like R4000 for historic reasons
191 ASMMACRO(mtc0_tlbw_hazard,
193 ASMMACRO(tlbw_use_hazard,
195 ASMMACRO(tlb_probe_hazard,
197 ASMMACRO(irq_enable_hazard,
199 ASMMACRO(irq_disable_hazard,
200 _ssnop; _ssnop; _ssnop
202 ASMMACRO(back_to_back_c0_hazard,
204 #define instruction_hazard() do { } while (0)
206 #else
209 * Finally the catchall case for all other processors including R4000, R4400,
210 * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
212 * The taken branch will result in a two cycle penalty for the two killed
213 * instructions on R4000 / R4400. Other processors only have a single cycle
214 * hazard so this is nice trick to have an optimal code for a range of
215 * processors.
217 ASMMACRO(mtc0_tlbw_hazard,
218 nop; nop
220 ASMMACRO(tlbw_use_hazard,
221 nop; nop; nop
223 ASMMACRO(tlb_probe_hazard,
224 nop; nop; nop
226 ASMMACRO(irq_enable_hazard,
227 _ssnop; _ssnop; _ssnop;
229 ASMMACRO(irq_disable_hazard,
230 nop; nop; nop
232 ASMMACRO(back_to_back_c0_hazard,
233 _ssnop; _ssnop; _ssnop;
235 #define instruction_hazard() do { } while (0)
237 #endif
240 /* FPU hazards */
242 #if defined(CONFIG_CPU_SB1)
243 ASMMACRO(enable_fpu_hazard,
244 .set push;
245 .set mips64;
246 .set noreorder;
247 _ssnop;
248 bnezl $0, .+4;
249 _ssnop;
250 .set pop
252 ASMMACRO(disable_fpu_hazard,
255 #elif defined(CONFIG_CPU_MIPSR2)
256 ASMMACRO(enable_fpu_hazard,
257 _ehb
259 ASMMACRO(disable_fpu_hazard,
260 _ehb
262 #else
263 ASMMACRO(enable_fpu_hazard,
264 nop; nop; nop; nop
266 ASMMACRO(disable_fpu_hazard,
267 _ehb
269 #endif
271 #endif /* _ASM_HAZARDS_H */