include/asm-mips/mach-db1x00/db1200.h

   1 /*
   2  * AMD Alchemy DB1200 Referrence Board
   3  * Board Registers defines.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  *
  23  */
  24 #ifndef __ASM_DB1200_H
  25 #define __ASM_DB1200_H
  26
  27 #include <linux/types.h>
  28 <<<<<<< HEAD:include/asm-mips/mach-db1x00/db1200.h
  29 =======
  30 #include <asm/mach-au1x00/au1xxx_psc.h>
  31 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-mips/mach-db1x00/db1200.h
  32
  33 // This is defined in au1000.h with bogus value
  34 #undef AU1X00_EXTERNAL_INT
  35
  36 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
  37 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
  38 #define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
  39 #define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
  40
  41 /* SPI and SMB are muxed on the Pb1200 board.
  42    Refer to board documentation.
  43  */
  44 #define SPI_PSC_BASE        PSC0_BASE_ADDR
  45 #define SMBUS_PSC_BASE      PSC0_BASE_ADDR
  46 /* AC97 and I2S are muxed on the Pb1200 board.
  47    Refer to board documentation.
  48  */
  49 #define AC97_PSC_BASE       PSC1_BASE_ADDR
  50 #define I2S_PSC_BASE            PSC1_BASE_ADDR
  51
  52 #define BCSR_KSEG1_ADDR 0xB9800000
  53
  54 typedef volatile struct
  55 {
  56         /*00*/  u16 whoami;
  57                 u16 reserved0;
  58         /*04*/  u16 status;
  59                 u16 reserved1;
  60         /*08*/  u16 switches;
  61                 u16 reserved2;
  62         /*0C*/  u16 resets;
  63                 u16 reserved3;
  64
  65         /*10*/  u16 pcmcia;
  66                 u16 reserved4;
  67         /*14*/  u16 board;
  68                 u16 reserved5;
  69         /*18*/  u16 disk_leds;
  70                 u16 reserved6;
  71         /*1C*/  u16 system;
  72                 u16 reserved7;
  73
  74         /*20*/  u16 intclr;
  75                 u16 reserved8;
  76         /*24*/  u16 intset;
  77                 u16 reserved9;
  78         /*28*/  u16 intclr_mask;
  79                 u16 reserved10;
  80         /*2C*/  u16 intset_mask;
  81                 u16 reserved11;
  82
  83         /*30*/  u16 sig_status;
  84                 u16 reserved12;
  85         /*34*/  u16 int_status;
  86                 u16 reserved13;
  87         /*38*/  u16 reserved14;
  88                 u16 reserved15;
  89         /*3C*/  u16 reserved16;
  90                 u16 reserved17;
  91
  92 } BCSR;
  93
  94 static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
  95
  96 /*
  97  * Register bit definitions for the BCSRs
  98  */
  99 #define BCSR_WHOAMI_DCID        0x000F
 100 #define BCSR_WHOAMI_CPLD        0x00F0
 101 #define BCSR_WHOAMI_BOARD       0x0F00
 102
 103 #define BCSR_STATUS_PCMCIA0VS   0x0003
 104 #define BCSR_STATUS_PCMCIA1VS   0x000C
 105 #define BCSR_STATUS_SWAPBOOT    0x0040
 106 #define BCSR_STATUS_FLASHBUSY   0x0100
 107 #define BCSR_STATUS_IDECBLID    0x0200
 108 #define BCSR_STATUS_SD0WP               0x0400
 109 #define BCSR_STATUS_U0RXD               0x1000
 110 #define BCSR_STATUS_U1RXD               0x2000
 111
 112 #define BCSR_SWITCHES_OCTAL     0x00FF
 113 #define BCSR_SWITCHES_DIP_1     0x0080
 114 #define BCSR_SWITCHES_DIP_2     0x0040
 115 #define BCSR_SWITCHES_DIP_3     0x0020
 116 #define BCSR_SWITCHES_DIP_4     0x0010
 117 #define BCSR_SWITCHES_DIP_5     0x0008
 118 #define BCSR_SWITCHES_DIP_6     0x0004
 119 #define BCSR_SWITCHES_DIP_7     0x0002
 120 #define BCSR_SWITCHES_DIP_8     0x0001
 121 #define BCSR_SWITCHES_ROTARY    0x0F00
 122
 123 #define BCSR_RESETS_ETH         0x0001
 124 #define BCSR_RESETS_CAMERA      0x0002
 125 #define BCSR_RESETS_DC          0x0004
 126 #define BCSR_RESETS_IDE         0x0008
 127 #define BCSR_RESETS_TV          0x0010
 128 /* not resets but in the same register */
 129 #define BCSR_RESETS_PWMR1mUX 0x0800
 130 #define BCSR_RESETS_PCS0MUX     0x1000
 131 #define BCSR_RESETS_PCS1MUX     0x2000
 132 #define BCSR_RESETS_SPISEL      0x4000
 133
 134 #define BCSR_PCMCIA_PC0VPP      0x0003
 135 #define BCSR_PCMCIA_PC0VCC      0x000C
 136 #define BCSR_PCMCIA_PC0DRVEN    0x0010
 137 #define BCSR_PCMCIA_PC0RST      0x0080
 138 #define BCSR_PCMCIA_PC1VPP      0x0300
 139 #define BCSR_PCMCIA_PC1VCC      0x0C00
 140 #define BCSR_PCMCIA_PC1DRVEN    0x1000
 141 #define BCSR_PCMCIA_PC1RST      0x8000
 142
 143 #define BCSR_BOARD_LCDVEE       0x0001
 144 #define BCSR_BOARD_LCDVDD       0x0002
 145 #define BCSR_BOARD_LCDBL        0x0004
 146 #define BCSR_BOARD_CAMSNAP      0x0010
 147 #define BCSR_BOARD_CAMPWR       0x0020
 148 #define BCSR_BOARD_SD0PWR       0x0040
 149
 150 #define BCSR_LEDS_DECIMALS      0x0003
 151 #define BCSR_LEDS_LED0          0x0100
 152 #define BCSR_LEDS_LED1          0x0200
 153 #define BCSR_LEDS_LED2          0x0400
 154 #define BCSR_LEDS_LED3          0x0800
 155
 156 #define BCSR_SYSTEM_POWEROFF    0x4000
 157 #define BCSR_SYSTEM_RESET       0x8000
 158
 159 /* Bit positions for the different interrupt sources */
 160 #define BCSR_INT_IDE            0x0001
 161 #define BCSR_INT_ETH            0x0002
 162 #define BCSR_INT_PC0            0x0004
 163 #define BCSR_INT_PC0STSCHG      0x0008
 164 #define BCSR_INT_PC1            0x0010
 165 #define BCSR_INT_PC1STSCHG      0x0020
 166 #define BCSR_INT_DC                     0x0040
 167 #define BCSR_INT_FLASHBUSY      0x0080
 168 #define BCSR_INT_PC0INSERT      0x0100
 169 #define BCSR_INT_PC0EJECT       0x0200
 170 #define BCSR_INT_PC1INSERT      0x0400
 171 #define BCSR_INT_PC1EJECT       0x0800
 172 #define BCSR_INT_SD0INSERT      0x1000
 173 #define BCSR_INT_SD0EJECT       0x2000
 174
 175 #define AU1XXX_SMC91111_PHYS_ADDR       (0x19000300)
 176 #define AU1XXX_SMC91111_IRQ                     DB1200_ETH_INT
 177
 178 #define AU1XXX_ATA_PHYS_ADDR            (0x18800000)
 179 #define AU1XXX_ATA_PHYS_LEN                     (0x100)
 180 #define AU1XXX_ATA_REG_OFFSET   (5)
 181 #define AU1XXX_ATA_INT                  DB1200_IDE_INT
 182 #define AU1XXX_ATA_DDMA_REQ             DSCR_CMD0_DMA_REQ1;
 183 #define AU1XXX_ATA_RQSIZE               128
 184
 185 #define NAND_PHYS_ADDR   0x20000000
 186
 187 /*
 188  * External Interrupts for Pb1200 as of 8/6/2004.
 189  * Bit positions in the CPLD registers can be calculated by taking
 190  * the interrupt define and subtracting the DB1200_INT_BEGIN value.
 191  *
 192  *   Example: IDE bis pos is  = 64 - 64
 193  *            ETH bit pos is  = 65 - 64
 194  */
 195 enum external_pb1200_ints {
 196         DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
 197
 198         DB1200_IDE_INT          = DB1200_INT_BEGIN,
 199         DB1200_ETH_INT,
 200         DB1200_PC0_INT,
 201         DB1200_PC0_STSCHG_INT,
 202         DB1200_PC1_INT,
 203         DB1200_PC1_STSCHG_INT,
 204         DB1200_DC_INT,
 205         DB1200_FLASHBUSY_INT,
 206         DB1200_PC0_INSERT_INT,
 207         DB1200_PC0_EJECT_INT,
 208         DB1200_PC1_INSERT_INT,
 209         DB1200_PC1_EJECT_INT,
 210         DB1200_SD0_INSERT_INT,
 211         DB1200_SD0_EJECT_INT,
 212
 213         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 214 };
 215
 216
 217 /* For drivers/pcmcia/au1000_db1x00.c */
 218
 219 /* PCMCIA Db1x00 specific defines */
 220
 221 #define PCMCIA_MAX_SOCK 1
 222 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
 223
 224 /* VPP/VCC */
 225 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 226         ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 227
 228 #define BOARD_PC0_INT DB1200_PC0_INT
 229 #define BOARD_PC1_INT DB1200_PC1_INT
 230 #define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
 231
 232 /* Nand chip select */
 233 #define NAND_CS 1
 234
 235 #endif /* __ASM_DB1200_H */
 236