include/asm-xtensa/coprocessor.h

   1 /*
   2  * include/asm-xtensa/coprocessor.h
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
   9  * Copyright (C) 2003 - 2005 Tensilica Inc.
  10 =======
  11  * Copyright (C) 2003 - 2007 Tensilica Inc.
  12 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
  13  */
  14
  15 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
  16 =======
  17
  18 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
  19 #ifndef _XTENSA_COPROCESSOR_H
  20 #define _XTENSA_COPROCESSOR_H
  21
  22 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
  23 #include <asm/variant/core.h>
  24 =======
  25 #include <linux/stringify.h>
  26 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
  27 #include <asm/variant/tie.h>
  28 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
  29 =======
  30 #include <asm/types.h>
  31
  32 #ifdef __ASSEMBLY__
  33 # include <asm/variant/tie-asm.h>
  34
  35 .macro  xchal_sa_start  a b
  36         .set .Lxchal_pofs_, 0
  37         .set .Lxchal_ofs_, 0
  38 .endm
  39
  40 .macro  xchal_sa_align  ptr minofs maxofs ofsalign totalign
  41         .set    .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1
  42         .set    .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_
  43 .endm
  44
  45 #define _SELECT (  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
  46                  | XTHAL_SAS_CC \
  47                  | XTHAL_SAS_CALR | XTHAL_SAS_CALE )
  48
  49 .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset
  50         .if XTREGS_OPT_SIZE > 0
  51                 addi    \clb, \ptr, \offset
  52                 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
  53         .endif
  54 .endm
  55
  56 .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset
  57         .if XTREGS_OPT_SIZE > 0
  58                 addi    \clb, \ptr, \offset
  59                 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
  60         .endif
  61 .endm
  62 #undef _SELECT
  63
  64 #define _SELECT (  XTHAL_SAS_TIE | XTHAL_SAS_OPT \
  65                  | XTHAL_SAS_NOCC \
  66                  | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB )
  67
  68 .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset
  69         .if XTREGS_USER_SIZE > 0
  70                 addi    \clb, \ptr, \offset
  71                 xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT
  72         .endif
  73 .endm
  74
  75 .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset
  76         .if XTREGS_USER_SIZE > 0
  77                 addi    \clb, \ptr, \offset
  78                 xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT
  79         .endif
  80 .endm
  81 #undef _SELECT
  82
  83
  84
  85 #endif  /* __ASSEMBLY__ */
  86 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
  87
  88 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
  89 #if !XCHAL_HAVE_CP
  90
  91 #define XTENSA_CP_EXTRA_OFFSET  0
  92 #define XTENSA_CP_EXTRA_ALIGN   1       /* must be a power of 2 */
  93 #define XTENSA_CP_EXTRA_SIZE    0
  94
  95 #else
  96
  97 #define XTOFS(last_start,last_size,align) \
  98         ((last_start+last_size+align-1) & -align)
  99
 100 #define XTENSA_CP_EXTRA_OFFSET  0
 101 #define XTENSA_CP_EXTRA_ALIGN   XCHAL_EXTRA_SA_ALIGN
 102
 103 #define XTENSA_CPE_CP0_OFFSET   \
 104         XTOFS(XTENSA_CP_EXTRA_OFFSET, XCHAL_EXTRA_SA_SIZE, XCHAL_CP0_SA_ALIGN)
 105 #define XTENSA_CPE_CP1_OFFSET   \
 106         XTOFS(XTENSA_CPE_CP0_OFFSET, XCHAL_CP0_SA_SIZE, XCHAL_CP1_SA_ALIGN)
 107 #define XTENSA_CPE_CP2_OFFSET   \
 108         XTOFS(XTENSA_CPE_CP1_OFFSET, XCHAL_CP1_SA_SIZE, XCHAL_CP2_SA_ALIGN)
 109 #define XTENSA_CPE_CP3_OFFSET   \
 110         XTOFS(XTENSA_CPE_CP2_OFFSET, XCHAL_CP2_SA_SIZE, XCHAL_CP3_SA_ALIGN)
 111 #define XTENSA_CPE_CP4_OFFSET   \
 112         XTOFS(XTENSA_CPE_CP3_OFFSET, XCHAL_CP3_SA_SIZE, XCHAL_CP4_SA_ALIGN)
 113 #define XTENSA_CPE_CP5_OFFSET   \
 114         XTOFS(XTENSA_CPE_CP4_OFFSET, XCHAL_CP4_SA_SIZE, XCHAL_CP5_SA_ALIGN)
 115 #define XTENSA_CPE_CP6_OFFSET   \
 116         XTOFS(XTENSA_CPE_CP5_OFFSET, XCHAL_CP5_SA_SIZE, XCHAL_CP6_SA_ALIGN)
 117 #define XTENSA_CPE_CP7_OFFSET   \
 118         XTOFS(XTENSA_CPE_CP6_OFFSET, XCHAL_CP6_SA_SIZE, XCHAL_CP7_SA_ALIGN)
 119 #define XTENSA_CP_EXTRA_SIZE    \
 120         XTOFS(XTENSA_CPE_CP7_OFFSET, XCHAL_CP7_SA_SIZE, 16)
 121
 122 #if XCHAL_CP_NUM > 0
 123 # ifndef __ASSEMBLY__
 124 =======
 125 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 126 /*
 127 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 128  * Tasks that own contents of (last user) each coprocessor.
 129  * Entries are 0 for not-owned or non-existent coprocessors.
 130  * Note: The size of this structure is fixed to 8 bytes in entry.S
 131 =======
 132  * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured.
 133  *
 134  * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured.
 135  *
 136 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 137  */
 138 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 139 typedef struct {
 140         struct task_struct *owner;      /* owner */
 141         int offset;                     /* offset in cpextra space. */
 142 } coprocessor_info_t;
 143 # else
 144 #  define COPROCESSOR_INFO_OWNER 0
 145 #  define COPROCESSOR_INFO_OFFSET 4
 146 #  define COPROCESSOR_INFO_SIZE 8
 147 # endif
 148 #endif
 149 #endif  /* XCHAL_HAVE_CP */
 150 =======
 151 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 152
 153 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 154 =======
 155 #define XTENSA_HAVE_COPROCESSOR(x)                                      \
 156         ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x)))
 157 #define XTENSA_HAVE_COPROCESSORS                                        \
 158         (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK)
 159 #define XTENSA_HAVE_IO_PORT(x)                                          \
 160         (XCHAL_CP_PORT_MASK & (1 << (x)))
 161 #define XTENSA_HAVE_IO_PORTS                                            \
 162         XCHAL_CP_PORT_MASK
 163 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 164
 165 #ifndef __ASSEMBLY__
 166 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 167 # if XCHAL_CP_NUM > 0
 168 struct task_struct;
 169 extern void release_coprocessors (struct task_struct*);
 170 extern void save_coprocessor_registers(void*, int);
 171 # else
 172 #  define release_coprocessors(task)
 173 # endif
 174 =======
 175 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 176
 177 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 178 typedef unsigned char cp_state_t[XTENSA_CP_EXTRA_SIZE]
 179         __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
 180 =======
 181 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 182
 183 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 184 #endif  /* !__ASSEMBLY__ */
 185 =======
 186 #if XCHAL_HAVE_CP
 187
 188 #define RSR_CPENABLE(x) do {                                              \
 189         __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
 190         } while(0);
 191 #define WSR_CPENABLE(x) do {                                              \
 192         __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync"    \
 193                              :: "a" (x));                                 \
 194         } while(0);
 195 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 196
 197 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 198 =======
 199 #endif /* XCHAL_HAVE_CP */
 200 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 201
 202 <<<<<<< HEAD:include/asm-xtensa/coprocessor.h
 203 =======
 204
 205 /*
 206  * Additional registers.
 207  * We define three types of additional registers:
 208  *  ext: extra registers that are used by the compiler
 209  *  cpn: optional registers that can be used by a user application
 210  *  cpX: coprocessor registers that can only be used if the corresponding
 211  *       CPENABLE bit is set.
 212  */
 213
 214 #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...)  \
 215         __REG ## list (cc, abi, type, name, size, align)
 216
 217 #define __REG0(cc,abi,t,name,s,a)       __REG0_ ## cc (abi,name)
 218 #define __REG1(cc,abi,t,name,s,a)       __REG1_ ## cc (name)
 219 #define __REG2(cc,abi,type,...)         __REG2_ ## type (__VA_ARGS__)
 220
 221 #define __REG0_0(abi,name)
 222 #define __REG0_1(abi,name)              __REG0_1 ## abi (name)
 223 #define __REG0_10(name) __u32 name;
 224 #define __REG0_11(name) __u32 name;
 225 #define __REG0_12(name)
 226
 227 #define __REG1_0(name)  __u32 name;
 228 #define __REG1_1(name)
 229
 230 #define __REG2_0(n,s,a) __u32 name;
 231 #define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
 232 #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a)));
 233
 234 typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t
 235         __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
 236 typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t
 237         __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN)));
 238
 239 #if XTENSA_HAVE_COPROCESSORS
 240
 241 typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t
 242         __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN)));
 243 typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t
 244         __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN)));
 245 typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t
 246         __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN)));
 247 typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t
 248         __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN)));
 249 typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t
 250         __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN)));
 251 typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t
 252         __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN)));
 253 typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t
 254         __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN)));
 255 typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t
 256         __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN)));
 257
 258 extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX];
 259 extern void coprocessor_save(void*, int);
 260 extern void coprocessor_load(void*, int);
 261 extern void coprocessor_flush(struct thread_info*, int);
 262 extern void coprocessor_restore(struct thread_info*, int);
 263
 264 extern void coprocessor_release_all(struct thread_info*);
 265 extern void coprocessor_flush_all(struct thread_info*);
 266
 267 static inline void coprocessor_clear_cpenable(void)
 268 {
 269         unsigned long i = 0;
 270         WSR_CPENABLE(i);
 271 }
 272
 273 #endif  /* XTENSA_HAVE_COPROCESSORS */
 274
 275 #endif  /* !__ASSEMBLY__ */
 276 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/coprocessor.h
 277 #endif  /* _XTENSA_COPROCESSOR_H */