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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / sound / pci / hda / hda_intel.c
blobe48f4d9f65808ff2715470942efd827c056c6535
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
60
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
79
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
82
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
85 * wake up.
86 */
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 #endif
91
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
94 "{Intel, ICH6M},"
95 "{Intel, ICH7},"
96 "{Intel, ESB2},"
97 "{Intel, ICH8},"
98 "{Intel, ICH9},"
99 "{Intel, ICH10},"
100 "{Intel, SCH},"
101 "{ATI, SB450},"
102 "{ATI, SB600},"
103 "{ATI, RS600},"
104 "{ATI, RS690},"
105 "{ATI, RS780},"
106 "{ATI, R600},"
107 "{ATI, RV630},"
108 "{ATI, RV610},"
109 "{ATI, RV670},"
110 "{ATI, RV635},"
111 "{ATI, RV620},"
112 "{ATI, RV770},"
113 "{VIA, VT8251},"
114 "{VIA, VT8237A},"
115 "{SiS, SIS966},"
116 "{ULI, M5461}}");
117 MODULE_DESCRIPTION("Intel HDA driver");
118
119 #define SFX "hda-intel: "
120
121
122 /*
123 * registers
124 */
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
145
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
153
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
159
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
163
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
166
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
178
179 /* PCI space */
180 #define ICH6_PCIREG_TCSEL 0x44
181
182 /*
183 * other constants
184 */
185
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_CAPTURE_INDEX 0
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_PLAYBACK_INDEX 4
191 #define ICH6_NUM_PLAYBACK 4
192
193 /* ULI has 6 playback and 5 capture */
194 #define ULI_CAPTURE_INDEX 0
195 #define ULI_NUM_CAPTURE 5
196 #define ULI_PLAYBACK_INDEX 5
197 #define ULI_NUM_PLAYBACK 6
198
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_CAPTURE_INDEX 0
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_PLAYBACK_INDEX 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* this number is statically defined for simplicity */
206 #define MAX_AZX_DEV 16
207
208 /* max number of fragments - we may use more if allocating more pages for BDL */
209 #define BDL_SIZE PAGE_ALIGN(8192)
210 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
211 /* max buffer size - no h/w limit, you can increase as you like */
212 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
213 /* max number of PCM devics per card */
214 #define AZX_MAX_AUDIO_PCMS 6
215 #define AZX_MAX_MODEM_PCMS 2
216 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
217
218 /* RIRB int mask: overrun[2], response[0] */
219 #define RIRB_INT_RESPONSE 0x01
220 #define RIRB_INT_OVERRUN 0x04
221 #define RIRB_INT_MASK 0x05
222
223 /* STATESTS int mask: SD2,SD1,SD0 */
224 #define AZX_MAX_CODECS 3
225 #define STATESTS_INT_MASK 0x07
226
227 /* SD_CTL bits */
228 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
229 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
230 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
231 #define SD_CTL_STREAM_TAG_SHIFT 20
232
233 /* SD_CTL and SD_STS */
234 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
235 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
236 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
237 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
238 SD_INT_COMPLETE)
239
240 /* SD_STS */
241 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
242
243 /* INTCTL and INTSTS */
244 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
245 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
246 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
247
248 /* GCTL unsolicited response enable bit */
249 #define ICH6_GCTL_UREN (1<<8)
250
251 /* GCTL reset bit */
252 #define ICH6_GCTL_RESET (1<<0)
253
254 /* CORB/RIRB control, read/write pointer */
255 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
256 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
257 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
258 /* below are so far hardcoded - should read registers in future */
259 #define ICH6_MAX_CORB_ENTRIES 256
260 #define ICH6_MAX_RIRB_ENTRIES 256
261
262 /* position fix mode */
263 enum {
264 POS_FIX_AUTO,
265 POS_FIX_NONE,
266 POS_FIX_POSBUF,
267 POS_FIX_FIFO,
268 };
269
270 /* Defines for ATI HD Audio support in SB450 south bridge */
271 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
272 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
273
274 /* Defines for Nvidia HDA support */
275 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
276 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
277
278 <<<<<<< HEAD:sound/pci/hda/hda_intel.c
279 =======
280 /* Defines for Intel SCH HDA snoop control */
281 #define INTEL_SCH_HDA_DEVC 0x78
282 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
283
284
285 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/hda/hda_intel.c
286 /*
287 */
288
289 struct azx_dev {
290 u32 *bdl; /* virtual address of the BDL */
291 dma_addr_t bdl_addr; /* physical address of the BDL */
292 u32 *posbuf; /* position buffer pointer */
293
294 unsigned int bufsize; /* size of the play buffer in bytes */
295 unsigned int fragsize; /* size of each period in bytes */
296 unsigned int frags; /* number for period in the play buffer */
297 unsigned int fifo_size; /* FIFO size */
298
299 void __iomem *sd_addr; /* stream descriptor pointer */
300
301 u32 sd_int_sta_mask; /* stream int status mask */
302
303 /* pcm support */
304 struct snd_pcm_substream *substream; /* assigned substream,
305 * set in PCM open
306 */
307 unsigned int format_val; /* format value to be set in the
308 * controller and the codec
309 */
310 unsigned char stream_tag; /* assigned stream */
311 unsigned char index; /* stream index */
312 /* for sanity check of position buffer */
313 unsigned int period_intr;
314
315 unsigned int opened :1;
316 unsigned int running :1;
317 };
318
319 /* CORB/RIRB */
320 struct azx_rb {
321 u32 *buf; /* CORB/RIRB buffer
322 * Each CORB entry is 4byte, RIRB is 8byte
323 */
324 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
325 /* for RIRB */
326 unsigned short rp, wp; /* read/write pointers */
327 int cmds; /* number of pending requests */
328 u32 res; /* last read value */
329 };
330
331 struct azx {
332 struct snd_card *card;
333 struct pci_dev *pci;
334
335 /* chip type specific */
336 int driver_type;
337 int playback_streams;
338 int playback_index_offset;
339 int capture_streams;
340 int capture_index_offset;
341 int num_streams;
342
343 /* pci resources */
344 unsigned long addr;
345 void __iomem *remap_addr;
346 int irq;
347
348 /* locks */
349 spinlock_t reg_lock;
350 struct mutex open_mutex;
351
352 /* streams (x num_streams) */
353 struct azx_dev *azx_dev;
354
355 /* PCM */
356 unsigned int pcm_devs;
357 struct snd_pcm *pcm[AZX_MAX_PCMS];
358
359 /* HD codec */
360 unsigned short codec_mask;
361 struct hda_bus *bus;
362
363 /* CORB/RIRB */
364 struct azx_rb corb;
365 struct azx_rb rirb;
366
367 /* BDL, CORB/RIRB and position buffers */
368 struct snd_dma_buffer bdl;
369 struct snd_dma_buffer rb;
370 struct snd_dma_buffer posbuf;
371
372 /* flags */
373 int position_fix;
374 unsigned int running :1;
375 unsigned int initialized :1;
376 unsigned int single_cmd :1;
377 unsigned int polling_mode :1;
378 unsigned int msi :1;
379
380 /* for debugging */
381 unsigned int last_cmd; /* last issued command (to sync) */
382 };
383
384 /* driver types */
385 enum {
386 AZX_DRIVER_ICH,
387 AZX_DRIVER_SCH,
388 AZX_DRIVER_ATI,
389 AZX_DRIVER_ATIHDMI,
390 AZX_DRIVER_VIA,
391 AZX_DRIVER_SIS,
392 AZX_DRIVER_ULI,
393 AZX_DRIVER_NVIDIA,
394 };
395
396 static char *driver_short_names[] __devinitdata = {
397 [AZX_DRIVER_ICH] = "HDA Intel",
398 [AZX_DRIVER_SCH] = "HDA Intel MID",
399 [AZX_DRIVER_ATI] = "HDA ATI SB",
400 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
401 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
402 [AZX_DRIVER_SIS] = "HDA SIS966",
403 [AZX_DRIVER_ULI] = "HDA ULI M5461",
404 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
405 };
406
407 /*
408 * macros for easy use
409 */
410 #define azx_writel(chip,reg,value) \
411 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
412 #define azx_readl(chip,reg) \
413 readl((chip)->remap_addr + ICH6_REG_##reg)
414 #define azx_writew(chip,reg,value) \
415 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
416 #define azx_readw(chip,reg) \
417 readw((chip)->remap_addr + ICH6_REG_##reg)
418 #define azx_writeb(chip,reg,value) \
419 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
420 #define azx_readb(chip,reg) \
421 readb((chip)->remap_addr + ICH6_REG_##reg)
422
423 #define azx_sd_writel(dev,reg,value) \
424 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
425 #define azx_sd_readl(dev,reg) \
426 readl((dev)->sd_addr + ICH6_REG_##reg)
427 #define azx_sd_writew(dev,reg,value) \
428 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
429 #define azx_sd_readw(dev,reg) \
430 readw((dev)->sd_addr + ICH6_REG_##reg)
431 #define azx_sd_writeb(dev,reg,value) \
432 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
433 #define azx_sd_readb(dev,reg) \
434 readb((dev)->sd_addr + ICH6_REG_##reg)
435
436 /* for pcm support */
437 #define get_azx_dev(substream) (substream->runtime->private_data)
438
439 /* Get the upper 32bit of the given dma_addr_t
440 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
441 */
442 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
443
444 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
445
446 /*
447 * Interface for HD codec
448 */
449
450 /*
451 * CORB / RIRB interface
452 */
453 static int azx_alloc_cmd_io(struct azx *chip)
454 {
455 int err;
456
457 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
458 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
459 snd_dma_pci_data(chip->pci),
460 PAGE_SIZE, &chip->rb);
461 if (err < 0) {
462 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
463 return err;
464 }
465 return 0;
466 }
467
468 static void azx_init_cmd_io(struct azx *chip)
469 {
470 /* CORB set up */
471 chip->corb.addr = chip->rb.addr;
472 chip->corb.buf = (u32 *)chip->rb.area;
473 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
474 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
475
476 /* set the corb size to 256 entries (ULI requires explicitly) */
477 azx_writeb(chip, CORBSIZE, 0x02);
478 /* set the corb write pointer to 0 */
479 azx_writew(chip, CORBWP, 0);
480 /* reset the corb hw read pointer */
481 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
482 /* enable corb dma */
483 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
484
485 /* RIRB set up */
486 chip->rirb.addr = chip->rb.addr + 2048;
487 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
488 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
489 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
490
491 /* set the rirb size to 256 entries (ULI requires explicitly) */
492 azx_writeb(chip, RIRBSIZE, 0x02);
493 /* reset the rirb hw write pointer */
494 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
495 /* set N=1, get RIRB response interrupt for new entry */
496 azx_writew(chip, RINTCNT, 1);
497 /* enable rirb dma and response irq */
498 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
499 chip->rirb.rp = chip->rirb.cmds = 0;
500 }
501
502 static void azx_free_cmd_io(struct azx *chip)
503 {
504 /* disable ringbuffer DMAs */
505 azx_writeb(chip, RIRBCTL, 0);
506 azx_writeb(chip, CORBCTL, 0);
507 }
508
509 /* send a command */
510 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
511 {
512 struct azx *chip = codec->bus->private_data;
513 unsigned int wp;
514
515 /* add command to corb */
516 wp = azx_readb(chip, CORBWP);
517 wp++;
518 wp %= ICH6_MAX_CORB_ENTRIES;
519
520 spin_lock_irq(&chip->reg_lock);
521 chip->rirb.cmds++;
522 chip->corb.buf[wp] = cpu_to_le32(val);
523 azx_writel(chip, CORBWP, wp);
524 spin_unlock_irq(&chip->reg_lock);
525
526 return 0;
527 }
528
529 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
530
531 /* retrieve RIRB entry - called from interrupt handler */
532 static void azx_update_rirb(struct azx *chip)
533 {
534 unsigned int rp, wp;
535 u32 res, res_ex;
536
537 wp = azx_readb(chip, RIRBWP);
538 if (wp == chip->rirb.wp)
539 return;
540 chip->rirb.wp = wp;
541
542 while (chip->rirb.rp != wp) {
543 chip->rirb.rp++;
544 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
545
546 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
547 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
548 res = le32_to_cpu(chip->rirb.buf[rp]);
549 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
550 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
551 else if (chip->rirb.cmds) {
552 chip->rirb.cmds--;
553 chip->rirb.res = res;
554 }
555 }
556 }
557
558 /* receive a response */
559 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
560 {
561 struct azx *chip = codec->bus->private_data;
562 unsigned long timeout;
563
564 again:
565 timeout = jiffies + msecs_to_jiffies(1000);
566 for (;;) {
567 if (chip->polling_mode) {
568 spin_lock_irq(&chip->reg_lock);
569 azx_update_rirb(chip);
570 spin_unlock_irq(&chip->reg_lock);
571 }
572 if (!chip->rirb.cmds)
573 return chip->rirb.res; /* the last value */
574 if (time_after(jiffies, timeout))
575 break;
576 if (codec->bus->needs_damn_long_delay)
577 msleep(2); /* temporary workaround */
578 else {
579 udelay(10);
580 cond_resched();
581 }
582 }
583
584 if (chip->msi) {
585 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
586 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
587 free_irq(chip->irq, chip);
588 chip->irq = -1;
589 pci_disable_msi(chip->pci);
590 chip->msi = 0;
591 if (azx_acquire_irq(chip, 1) < 0)
592 return -1;
593 goto again;
594 }
595
596 if (!chip->polling_mode) {
597 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
598 "switching to polling mode: last cmd=0x%08x\n",
599 chip->last_cmd);
600 chip->polling_mode = 1;
601 goto again;
602 }
603
604 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
605 "switching to single_cmd mode: last cmd=0x%08x\n",
606 chip->last_cmd);
607 chip->rirb.rp = azx_readb(chip, RIRBWP);
608 chip->rirb.cmds = 0;
609 /* switch to single_cmd mode */
610 chip->single_cmd = 1;
611 azx_free_cmd_io(chip);
612 return -1;
613 }
614
615 /*
616 * Use the single immediate command instead of CORB/RIRB for simplicity
617 *
618 * Note: according to Intel, this is not preferred use. The command was
619 * intended for the BIOS only, and may get confused with unsolicited
620 * responses. So, we shouldn't use it for normal operation from the
621 * driver.
622 * I left the codes, however, for debugging/testing purposes.
623 */
624
625 /* send a command */
626 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
627 {
628 struct azx *chip = codec->bus->private_data;
629 int timeout = 50;
630
631 while (timeout--) {
632 /* check ICB busy bit */
633 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
634 /* Clear IRV valid bit */
635 azx_writew(chip, IRS, azx_readw(chip, IRS) |
636 ICH6_IRS_VALID);
637 azx_writel(chip, IC, val);
638 azx_writew(chip, IRS, azx_readw(chip, IRS) |
639 ICH6_IRS_BUSY);
640 return 0;
641 }
642 udelay(1);
643 }
644 if (printk_ratelimit())
645 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
646 azx_readw(chip, IRS), val);
647 return -EIO;
648 }
649
650 /* receive a response */
651 static unsigned int azx_single_get_response(struct hda_codec *codec)
652 {
653 struct azx *chip = codec->bus->private_data;
654 int timeout = 50;
655
656 while (timeout--) {
657 /* check IRV busy bit */
658 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
659 return azx_readl(chip, IR);
660 udelay(1);
661 }
662 if (printk_ratelimit())
663 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
664 azx_readw(chip, IRS));
665 return (unsigned int)-1;
666 }
667
668 /*
669 * The below are the main callbacks from hda_codec.
670 *
671 * They are just the skeleton to call sub-callbacks according to the
672 * current setting of chip->single_cmd.
673 */
674
675 /* send a command */
676 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
677 int direct, unsigned int verb,
678 unsigned int para)
679 {
680 struct azx *chip = codec->bus->private_data;
681 u32 val;
682
683 val = (u32)(codec->addr & 0x0f) << 28;
684 val |= (u32)direct << 27;
685 val |= (u32)nid << 20;
686 val |= verb << 8;
687 val |= para;
688 chip->last_cmd = val;
689
690 if (chip->single_cmd)
691 return azx_single_send_cmd(codec, val);
692 else
693 return azx_corb_send_cmd(codec, val);
694 }
695
696 /* get a response */
697 static unsigned int azx_get_response(struct hda_codec *codec)
698 {
699 struct azx *chip = codec->bus->private_data;
700 if (chip->single_cmd)
701 return azx_single_get_response(codec);
702 else
703 return azx_rirb_get_response(codec);
704 }
705
706 #ifdef CONFIG_SND_HDA_POWER_SAVE
707 static void azx_power_notify(struct hda_codec *codec);
708 #endif
709
710 /* reset codec link */
711 static int azx_reset(struct azx *chip)
712 {
713 int count;
714
715 /* clear STATESTS */
716 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
717
718 /* reset controller */
719 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
720
721 count = 50;
722 while (azx_readb(chip, GCTL) && --count)
723 msleep(1);
724
725 /* delay for >= 100us for codec PLL to settle per spec
726 * Rev 0.9 section 5.5.1
727 */
728 msleep(1);
729
730 /* Bring controller out of reset */
731 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
732
733 count = 50;
734 while (!azx_readb(chip, GCTL) && --count)
735 msleep(1);
736
737 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
738 msleep(1);
739
740 /* check to see if controller is ready */
741 if (!azx_readb(chip, GCTL)) {
742 snd_printd("azx_reset: controller not ready!\n");
743 return -EBUSY;
744 }
745
746 /* Accept unsolicited responses */
747 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
748
749 /* detect codecs */
750 if (!chip->codec_mask) {
751 chip->codec_mask = azx_readw(chip, STATESTS);
752 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
753 }
754
755 return 0;
756 }
757
758
759 /*
760 * Lowlevel interface
761 */
762
763 /* enable interrupts */
764 static void azx_int_enable(struct azx *chip)
765 {
766 /* enable controller CIE and GIE */
767 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
768 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
769 }
770
771 /* disable interrupts */
772 static void azx_int_disable(struct azx *chip)
773 {
774 int i;
775
776 /* disable interrupts in stream descriptor */
777 for (i = 0; i < chip->num_streams; i++) {
778 struct azx_dev *azx_dev = &chip->azx_dev[i];
779 azx_sd_writeb(azx_dev, SD_CTL,
780 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
781 }
782
783 /* disable SIE for all streams */
784 azx_writeb(chip, INTCTL, 0);
785
786 /* disable controller CIE and GIE */
787 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
788 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
789 }
790
791 /* clear interrupts */
792 static void azx_int_clear(struct azx *chip)
793 {
794 int i;
795
796 /* clear stream status */
797 for (i = 0; i < chip->num_streams; i++) {
798 struct azx_dev *azx_dev = &chip->azx_dev[i];
799 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
800 }
801
802 /* clear STATESTS */
803 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
804
805 /* clear rirb status */
806 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
807
808 /* clear int status */
809 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
810 }
811
812 /* start a stream */
813 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
814 {
815 /* enable SIE */
816 azx_writeb(chip, INTCTL,
817 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
818 /* set DMA start and interrupt mask */
819 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
820 SD_CTL_DMA_START | SD_INT_MASK);
821 }
822
823 /* stop a stream */
824 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
825 {
826 /* stop DMA */
827 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
828 ~(SD_CTL_DMA_START | SD_INT_MASK));
829 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
830 /* disable SIE */
831 azx_writeb(chip, INTCTL,
832 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
833 }
834
835
836 /*
837 * reset and start the controller registers
838 */
839 static void azx_init_chip(struct azx *chip)
840 {
841 if (chip->initialized)
842 return;
843
844 /* reset controller */
845 azx_reset(chip);
846
847 /* initialize interrupts */
848 azx_int_clear(chip);
849 azx_int_enable(chip);
850
851 /* initialize the codec command I/O */
852 if (!chip->single_cmd)
853 azx_init_cmd_io(chip);
854
855 /* program the position buffer */
856 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
857 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
858
859 chip->initialized = 1;
860 }
861
862 /*
863 * initialize the PCI registers
864 */
865 /* update bits in a PCI register byte */
866 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
867 unsigned char mask, unsigned char val)
868 {
869 unsigned char data;
870
871 pci_read_config_byte(pci, reg, &data);
872 data &= ~mask;
873 data |= (val & mask);
874 pci_write_config_byte(pci, reg, data);
875 }
876
877 static void azx_init_pci(struct azx *chip)
878 {
879 <<<<<<< HEAD:sound/pci/hda/hda_intel.c
880 =======
881 unsigned short snoop;
882
883 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/hda/hda_intel.c
884 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
885 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
886 * Ensuring these bits are 0 clears playback static on some HD Audio
887 * codecs
888 */
889 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
890
891 switch (chip->driver_type) {
892 case AZX_DRIVER_ATI:
893 /* For ATI SB450 azalia HD audio, we need to enable snoop */
894 update_pci_byte(chip->pci,
895 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
896 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
897 break;
898 case AZX_DRIVER_NVIDIA:
899 /* For NVIDIA HDA, enable snoop */
900 update_pci_byte(chip->pci,
901 NVIDIA_HDA_TRANSREG_ADDR,
902 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
903 break;
904 <<<<<<< HEAD:sound/pci/hda/hda_intel.c
905 =======
906 case AZX_DRIVER_SCH:
907 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
908 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
909 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
910 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
911 pci_read_config_word(chip->pci,
912 INTEL_SCH_HDA_DEVC, &snoop);
913 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
914 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
915 ? "Failed" : "OK");
916 }
917 break;
918
919 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/hda/hda_intel.c
920 }
921 }
922
923
924 /*
925 * interrupt handler
926 */
927 static irqreturn_t azx_interrupt(int irq, void *dev_id)
928 {
929 struct azx *chip = dev_id;
930 struct azx_dev *azx_dev;
931 u32 status;
932 int i;
933
934 spin_lock(&chip->reg_lock);
935
936 status = azx_readl(chip, INTSTS);
937 if (status == 0) {
938 spin_unlock(&chip->reg_lock);
939 return IRQ_NONE;
940 }
941
942 for (i = 0; i < chip->num_streams; i++) {
943 azx_dev = &chip->azx_dev[i];
944 if (status & azx_dev->sd_int_sta_mask) {
945 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
946 if (azx_dev->substream && azx_dev->running) {
947 azx_dev->period_intr++;
948 spin_unlock(&chip->reg_lock);
949 snd_pcm_period_elapsed(azx_dev->substream);
950 spin_lock(&chip->reg_lock);
951 }
952 }
953 }
954
955 /* clear rirb int */
956 status = azx_readb(chip, RIRBSTS);
957 if (status & RIRB_INT_MASK) {
958 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
959 azx_update_rirb(chip);
960 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
961 }
962
963 #if 0
964 /* clear state status int */
965 if (azx_readb(chip, STATESTS) & 0x04)
966 azx_writeb(chip, STATESTS, 0x04);
967 #endif
968 spin_unlock(&chip->reg_lock);
969
970 return IRQ_HANDLED;
971 }
972
973
974 /*
975 * set up BDL entries
976 */
977 static void azx_setup_periods(struct azx_dev *azx_dev)
978 {
979 u32 *bdl = azx_dev->bdl;
980 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
981 int idx;
982
983 /* reset BDL address */
984 azx_sd_writel(azx_dev, SD_BDLPL, 0);
985 azx_sd_writel(azx_dev, SD_BDLPU, 0);
986
987 /* program the initial BDL entries */
988 for (idx = 0; idx < azx_dev->frags; idx++) {
989 unsigned int off = idx << 2; /* 4 dword step */
990 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
991 /* program the address field of the BDL entry */
992 bdl[off] = cpu_to_le32((u32)addr);
993 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
994
995 /* program the size field of the BDL entry */
996 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
997
998 /* program the IOC to enable interrupt when buffer completes */
999 bdl[off+3] = cpu_to_le32(0x01);
1000 }
1001 }
1002
1003 /*
1004 * set up the SD for streaming
1005 */
1006 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1007 {
1008 unsigned char val;
1009 int timeout;
1010
1011 /* make sure the run bit is zero for SD */
1012 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1013 ~SD_CTL_DMA_START);
1014 /* reset stream */
1015 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1016 SD_CTL_STREAM_RESET);
1017 udelay(3);
1018 timeout = 300;
1019 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1020 --timeout)
1021 ;
1022 val &= ~SD_CTL_STREAM_RESET;
1023 azx_sd_writeb(azx_dev, SD_CTL, val);
1024 udelay(3);
1025
1026 timeout = 300;
1027 /* waiting for hardware to report that the stream is out of reset */
1028 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1029 --timeout)
1030 ;
1031
1032 /* program the stream_tag */
1033 azx_sd_writel(azx_dev, SD_CTL,
1034 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1035 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1036
1037 /* program the length of samples in cyclic buffer */
1038 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1039
1040 /* program the stream format */
1041 /* this value needs to be the same as the one programmed */
1042 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1043
1044 /* program the stream LVI (last valid index) of the BDL */
1045 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1046
1047 /* program the BDL address */
1048 /* lower BDL address */
1049 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1050 /* upper BDL address */
1051 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1052
1053 /* enable the position buffer */
1054 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1055 azx_writel(chip, DPLBASE,
1056 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1057
1058 /* set the interrupt enable bits in the descriptor control register */
1059 azx_sd_writel(azx_dev, SD_CTL,
1060 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1061
1062 return 0;
1063 }
1064
1065
1066 /*
1067 * Codec initialization
1068 */
1069
1070 static unsigned int azx_max_codecs[] __devinitdata = {
1071 [AZX_DRIVER_ICH] = 3,
1072 <<<<<<< HEAD:sound/pci/hda/hda_intel.c
1073 =======
1074 [AZX_DRIVER_SCH] = 3,
1075 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/hda/hda_intel.c
1076 [AZX_DRIVER_ATI] = 4,
1077 [AZX_DRIVER_ATIHDMI] = 4,
1078 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1079 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1080 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1081 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1082 };
1083
1084 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1085 unsigned int codec_probe_mask)
1086 {
1087 struct hda_bus_template bus_temp;
1088 int c, codecs, audio_codecs, err;
1089
1090 memset(&bus_temp, 0, sizeof(bus_temp));
1091 bus_temp.private_data = chip;
1092 bus_temp.modelname = model;
1093 bus_temp.pci = chip->pci;
1094 bus_temp.ops.command = azx_send_cmd;
1095 bus_temp.ops.get_response = azx_get_response;
1096 #ifdef CONFIG_SND_HDA_POWER_SAVE
1097 bus_temp.ops.pm_notify = azx_power_notify;
1098 #endif
1099
1100 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1101 if (err < 0)
1102 return err;
1103
1104 codecs = audio_codecs = 0;
1105 for (c = 0; c < AZX_MAX_CODECS; c++) {
1106 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1107 struct hda_codec *codec;
1108 err = snd_hda_codec_new(chip->bus, c, &codec);
1109 if (err < 0)
1110 continue;
1111 codecs++;
1112 if (codec->afg)
1113 audio_codecs++;
1114 }
1115 }
1116 if (!audio_codecs) {
1117 /* probe additional slots if no codec is found */
1118 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1119 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1120 err = snd_hda_codec_new(chip->bus, c, NULL);
1121 if (err < 0)
1122 continue;
1123 codecs++;
1124 }
1125 }
1126 }
1127 if (!codecs) {
1128 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1129 return -ENXIO;
1130 }
1131
1132 return 0;
1133 }
1134
1135
1136 /*
1137 * PCM support
1138 */
1139
1140 /* assign a stream for the PCM */
1141 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1142 {
1143 int dev, i, nums;
1144 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1145 dev = chip->playback_index_offset;
1146 nums = chip->playback_streams;
1147 } else {
1148 dev = chip->capture_index_offset;
1149 nums = chip->capture_streams;
1150 }
1151 for (i = 0; i < nums; i++, dev++)
1152 if (!chip->azx_dev[dev].opened) {
1153 chip->azx_dev[dev].opened = 1;
1154 return &chip->azx_dev[dev];
1155 }
1156 return NULL;
1157 }
1158
1159 /* release the assigned stream */
1160 static inline void azx_release_device(struct azx_dev *azx_dev)
1161 {
1162 azx_dev->opened = 0;
1163 }
1164
1165 static struct snd_pcm_hardware azx_pcm_hw = {
1166 .info = (SNDRV_PCM_INFO_MMAP |
1167 SNDRV_PCM_INFO_INTERLEAVED |
1168 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1169 SNDRV_PCM_INFO_MMAP_VALID |
1170 /* No full-resume yet implemented */
1171 /* SNDRV_PCM_INFO_RESUME |*/
1172 SNDRV_PCM_INFO_PAUSE),
1173 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1174 .rates = SNDRV_PCM_RATE_48000,
1175 .rate_min = 48000,
1176 .rate_max = 48000,
1177 .channels_min = 2,
1178 .channels_max = 2,
1179 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1180 .period_bytes_min = 128,
1181 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1182 .periods_min = 2,
1183 .periods_max = AZX_MAX_FRAG,
1184 .fifo_size = 0,
1185 };
1186
1187 struct azx_pcm {
1188 struct azx *chip;
1189 struct hda_codec *codec;
1190 struct hda_pcm_stream *hinfo[2];
1191 };
1192
1193 static int azx_pcm_open(struct snd_pcm_substream *substream)
1194 {
1195 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1196 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1197 struct azx *chip = apcm->chip;
1198 struct azx_dev *azx_dev;
1199 struct snd_pcm_runtime *runtime = substream->runtime;
1200 unsigned long flags;
1201 int err;
1202
1203 mutex_lock(&chip->open_mutex);
1204 azx_dev = azx_assign_device(chip, substream->stream);
1205 if (azx_dev == NULL) {
1206 mutex_unlock(&chip->open_mutex);
1207 return -EBUSY;
1208 }
1209 runtime->hw = azx_pcm_hw;
1210 runtime->hw.channels_min = hinfo->channels_min;
1211 runtime->hw.channels_max = hinfo->channels_max;
1212 runtime->hw.formats = hinfo->formats;
1213 runtime->hw.rates = hinfo->rates;
1214 snd_pcm_limit_hw_rates(runtime);
1215 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1216 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1217 128);
1218 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1219 128);
1220 snd_hda_power_up(apcm->codec);
1221 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1222 if (err < 0) {
1223 azx_release_device(azx_dev);
1224 snd_hda_power_down(apcm->codec);
1225 mutex_unlock(&chip->open_mutex);
1226 return err;
1227 }
1228 spin_lock_irqsave(&chip->reg_lock, flags);
1229 azx_dev->substream = substream;
1230 azx_dev->running = 0;
1231 spin_unlock_irqrestore(&chip->reg_lock, flags);
1232
1233 runtime->private_data = azx_dev;
1234 mutex_unlock(&chip->open_mutex);
1235 return 0;
1236 }
1237
1238 static int azx_pcm_close(struct snd_pcm_substream *substream)
1239 {
1240 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1241 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1242 struct azx *chip = apcm->chip;
1243 struct azx_dev *azx_dev = get_azx_dev(substream);
1244 unsigned long flags;
1245
1246 mutex_lock(&chip->open_mutex);
1247 spin_lock_irqsave(&chip->reg_lock, flags);
1248 azx_dev->substream = NULL;
1249 azx_dev->running = 0;
1250 spin_unlock_irqrestore(&chip->reg_lock, flags);
1251 azx_release_device(azx_dev);
1252 hinfo->ops.close(hinfo, apcm->codec, substream);
1253 snd_hda_power_down(apcm->codec);
1254 mutex_unlock(&chip->open_mutex);
1255 return 0;
1256 }
1257
1258 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1259 struct snd_pcm_hw_params *hw_params)
1260 {
1261 return snd_pcm_lib_malloc_pages(substream,
1262 params_buffer_bytes(hw_params));
1263 }
1264
1265 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1266 {
1267 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1268 struct azx_dev *azx_dev = get_azx_dev(substream);
1269 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1270
1271 /* reset BDL address */
1272 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1273 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1274 azx_sd_writel(azx_dev, SD_CTL, 0);
1275
1276 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1277
1278 return snd_pcm_lib_free_pages(substream);
1279 }
1280
1281 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1282 {
1283 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1284 struct azx *chip = apcm->chip;
1285 struct azx_dev *azx_dev = get_azx_dev(substream);
1286 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1287 struct snd_pcm_runtime *runtime = substream->runtime;
1288
1289 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1290 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1291 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1292 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1293 runtime->channels,
1294 runtime->format,
1295 hinfo->maxbps);
1296 if (!azx_dev->format_val) {
1297 snd_printk(KERN_ERR SFX
1298 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1299 runtime->rate, runtime->channels, runtime->format);
1300 return -EINVAL;
1301 }
1302
1303 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1304 "format=0x%x\n",
1305 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1306 azx_setup_periods(azx_dev);
1307 azx_setup_controller(chip, azx_dev);
1308 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1309 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1310 else
1311 azx_dev->fifo_size = 0;
1312
1313 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1314 azx_dev->format_val, substream);
1315 }
1316
1317 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1318 {
1319 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1320 struct azx_dev *azx_dev = get_azx_dev(substream);
1321 struct azx *chip = apcm->chip;
1322 int err = 0;
1323
1324 spin_lock(&chip->reg_lock);
1325 switch (cmd) {
1326 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1327 case SNDRV_PCM_TRIGGER_RESUME:
1328 case SNDRV_PCM_TRIGGER_START:
1329 azx_stream_start(chip, azx_dev);
1330 azx_dev->running = 1;
1331 break;
1332 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1333 case SNDRV_PCM_TRIGGER_SUSPEND:
1334 case SNDRV_PCM_TRIGGER_STOP:
1335 azx_stream_stop(chip, azx_dev);
1336 azx_dev->running = 0;
1337 break;
1338 default:
1339 err = -EINVAL;
1340 }
1341 spin_unlock(&chip->reg_lock);
1342 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1343 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1344 cmd == SNDRV_PCM_TRIGGER_STOP) {
1345 int timeout = 5000;
1346 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1347 --timeout)
1348 ;
1349 }
1350 return err;
1351 }
1352
1353 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1354 {
1355 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1356 struct azx *chip = apcm->chip;
1357 struct azx_dev *azx_dev = get_azx_dev(substream);
1358 unsigned int pos;
1359
1360 if (chip->position_fix == POS_FIX_POSBUF ||
1361 chip->position_fix == POS_FIX_AUTO) {
1362 /* use the position buffer */
1363 pos = le32_to_cpu(*azx_dev->posbuf);
1364 if (chip->position_fix == POS_FIX_AUTO &&
1365 azx_dev->period_intr == 1 && !pos) {
1366 printk(KERN_WARNING
1367 "hda-intel: Invalid position buffer, "
1368 "using LPIB read method instead.\n");
1369 chip->position_fix = POS_FIX_NONE;
1370 goto read_lpib;
1371 }
1372 } else {
1373 read_lpib:
1374 /* read LPIB */
1375 pos = azx_sd_readl(azx_dev, SD_LPIB);
1376 if (chip->position_fix == POS_FIX_FIFO)
1377 pos += azx_dev->fifo_size;
1378 }
1379 if (pos >= azx_dev->bufsize)
1380 pos = 0;
1381 return bytes_to_frames(substream->runtime, pos);
1382 }
1383
1384 static struct snd_pcm_ops azx_pcm_ops = {
1385 .open = azx_pcm_open,
1386 .close = azx_pcm_close,
1387 .ioctl = snd_pcm_lib_ioctl,
1388 .hw_params = azx_pcm_hw_params,
1389 .hw_free = azx_pcm_hw_free,
1390 .prepare = azx_pcm_prepare,
1391 .trigger = azx_pcm_trigger,
1392 .pointer = azx_pcm_pointer,
1393 };
1394
1395 static void azx_pcm_free(struct snd_pcm *pcm)
1396 {
1397 kfree(pcm->private_data);
1398 }
1399
1400 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1401 struct hda_pcm *cpcm, int pcm_dev)
1402 {
1403 int err;
1404 struct snd_pcm *pcm;
1405 struct azx_pcm *apcm;
1406
1407 /* if no substreams are defined for both playback and capture,
1408 * it's just a placeholder. ignore it.
1409 */
1410 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1411 return 0;
1412
1413 snd_assert(cpcm->name, return -EINVAL);
1414
1415 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1416 cpcm->stream[0].substreams,
1417 cpcm->stream[1].substreams,
1418 &pcm);
1419 if (err < 0)
1420 return err;
1421 strcpy(pcm->name, cpcm->name);
1422 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1423 if (apcm == NULL)
1424 return -ENOMEM;
1425 apcm->chip = chip;
1426 apcm->codec = codec;
1427 apcm->hinfo[0] = &cpcm->stream[0];
1428 apcm->hinfo[1] = &cpcm->stream[1];
1429 pcm->private_data = apcm;
1430 pcm->private_free = azx_pcm_free;
1431 if (cpcm->stream[0].substreams)
1432 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1433 if (cpcm->stream[1].substreams)
1434 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1435 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1436 snd_dma_pci_data(chip->pci),
1437 1024 * 64, 1024 * 1024);
1438 chip->pcm[pcm_dev] = pcm;
1439 if (chip->pcm_devs < pcm_dev + 1)
1440 chip->pcm_devs = pcm_dev + 1;
1441
1442 return 0;
1443 }
1444
1445 static int __devinit azx_pcm_create(struct azx *chip)
1446 {
1447 struct hda_codec *codec;
1448 int c, err;
1449 int pcm_dev;
1450
1451 err = snd_hda_build_pcms(chip->bus);
1452 if (err < 0)
1453 return err;
1454
1455 /* create audio PCMs */
1456 pcm_dev = 0;
1457 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1458 for (c = 0; c < codec->num_pcms; c++) {
1459 if (codec->pcm_info[c].is_modem)
1460 continue; /* create later */
1461 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1462 snd_printk(KERN_ERR SFX
1463 "Too many audio PCMs\n");
1464 return -EINVAL;
1465 }
1466 err = create_codec_pcm(chip, codec,
1467 &codec->pcm_info[c], pcm_dev);
1468 if (err < 0)
1469 return err;
1470 pcm_dev++;
1471 }
1472 }
1473
1474 /* create modem PCMs */
1475 pcm_dev = AZX_MAX_AUDIO_PCMS;
1476 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1477 for (c = 0; c < codec->num_pcms; c++) {
1478 if (!codec->pcm_info[c].is_modem)
1479 continue; /* already created */
1480 if (pcm_dev >= AZX_MAX_PCMS) {
1481 snd_printk(KERN_ERR SFX
1482 "Too many modem PCMs\n");
1483 return -EINVAL;
1484 }
1485 err = create_codec_pcm(chip, codec,
1486 &codec->pcm_info[c], pcm_dev);
1487 if (err < 0)
1488 return err;
1489 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1490 pcm_dev++;
1491 }
1492 }
1493 return 0;
1494 }
1495
1496 /*
1497 * mixer creation - all stuff is implemented in hda module
1498 */
1499 static int __devinit azx_mixer_create(struct azx *chip)
1500 {
1501 return snd_hda_build_controls(chip->bus);
1502 }
1503
1504
1505 /*
1506 * initialize SD streams
1507 */
1508 static int __devinit azx_init_stream(struct azx *chip)
1509 {
1510 int i;
1511
1512 /* initialize each stream (aka device)
1513 * assign the starting bdl address to each stream (device)
1514 * and initialize
1515 */
1516 for (i = 0; i < chip->num_streams; i++) {
1517 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1518 struct azx_dev *azx_dev = &chip->azx_dev[i];
1519 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1520 azx_dev->bdl_addr = chip->bdl.addr + off;
1521 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1522 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1523 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1524 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1525 azx_dev->sd_int_sta_mask = 1 << i;
1526 /* stream tag: must be non-zero and unique */
1527 azx_dev->index = i;
1528 azx_dev->stream_tag = i + 1;
1529 }
1530
1531 return 0;
1532 }
1533
1534 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1535 {
1536 if (request_irq(chip->pci->irq, azx_interrupt,
1537 chip->msi ? 0 : IRQF_SHARED,
1538 "HDA Intel", chip)) {
1539 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1540 "disabling device\n", chip->pci->irq);
1541 if (do_disconnect)
1542 snd_card_disconnect(chip->card);
1543 return -1;
1544 }
1545 chip->irq = chip->pci->irq;
1546 pci_intx(chip->pci, !chip->msi);
1547 return 0;
1548 }
1549
1550
1551 static void azx_stop_chip(struct azx *chip)
1552 {
1553 if (!chip->initialized)
1554 return;
1555
1556 /* disable interrupts */
1557 azx_int_disable(chip);
1558 azx_int_clear(chip);
1559
1560 /* disable CORB/RIRB */
1561 azx_free_cmd_io(chip);
1562
1563 /* disable position buffer */
1564 azx_writel(chip, DPLBASE, 0);
1565 azx_writel(chip, DPUBASE, 0);
1566
1567 chip->initialized = 0;
1568 }
1569
1570 #ifdef CONFIG_SND_HDA_POWER_SAVE
1571 /* power-up/down the controller */
1572 static void azx_power_notify(struct hda_codec *codec)
1573 {
1574 struct azx *chip = codec->bus->private_data;
1575 struct hda_codec *c;
1576 int power_on = 0;
1577
1578 list_for_each_entry(c, &codec->bus->codec_list, list) {
1579 if (c->power_on) {
1580 power_on = 1;
1581 break;
1582 }
1583 }
1584 if (power_on)
1585 azx_init_chip(chip);
1586 else if (chip->running && power_save_controller)
1587 azx_stop_chip(chip);
1588 }
1589 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1590
1591 #ifdef CONFIG_PM
1592 /*
1593 * power management
1594 */
1595 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1596 {
1597 struct snd_card *card = pci_get_drvdata(pci);
1598 struct azx *chip = card->private_data;
1599 int i;
1600
1601 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1602 for (i = 0; i < chip->pcm_devs; i++)
1603 snd_pcm_suspend_all(chip->pcm[i]);
1604 if (chip->initialized)
1605 snd_hda_suspend(chip->bus, state);
1606 azx_stop_chip(chip);
1607 if (chip->irq >= 0) {
1608 synchronize_irq(chip->irq);
1609 free_irq(chip->irq, chip);
1610 chip->irq = -1;
1611 }
1612 if (chip->msi)
1613 pci_disable_msi(chip->pci);
1614 pci_disable_device(pci);
1615 pci_save_state(pci);
1616 pci_set_power_state(pci, pci_choose_state(pci, state));
1617 return 0;
1618 }
1619
1620 static int azx_resume(struct pci_dev *pci)
1621 {
1622 struct snd_card *card = pci_get_drvdata(pci);
1623 struct azx *chip = card->private_data;
1624
1625 pci_set_power_state(pci, PCI_D0);
1626 pci_restore_state(pci);
1627 if (pci_enable_device(pci) < 0) {
1628 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1629 "disabling device\n");
1630 snd_card_disconnect(card);
1631 return -EIO;
1632 }
1633 pci_set_master(pci);
1634 if (chip->msi)
1635 if (pci_enable_msi(pci) < 0)
1636 chip->msi = 0;
1637 if (azx_acquire_irq(chip, 1) < 0)
1638 return -EIO;
1639 azx_init_pci(chip);
1640
1641 if (snd_hda_codecs_inuse(chip->bus))
1642 azx_init_chip(chip);
1643
1644 snd_hda_resume(chip->bus);
1645 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1646 return 0;
1647 }
1648 #endif /* CONFIG_PM */
1649
1650
1651 /*
1652 * destructor
1653 */
1654 static int azx_free(struct azx *chip)
1655 {
1656 if (chip->initialized) {
1657 int i;
1658 for (i = 0; i < chip->num_streams; i++)
1659 azx_stream_stop(chip, &chip->azx_dev[i]);
1660 azx_stop_chip(chip);
1661 }
1662
1663 if (chip->irq >= 0) {
1664 synchronize_irq(chip->irq);
1665 free_irq(chip->irq, (void*)chip);
1666 }
1667 if (chip->msi)
1668 pci_disable_msi(chip->pci);
1669 if (chip->remap_addr)
1670 iounmap(chip->remap_addr);
1671
1672 if (chip->bdl.area)
1673 snd_dma_free_pages(&chip->bdl);
1674 if (chip->rb.area)
1675 snd_dma_free_pages(&chip->rb);
1676 if (chip->posbuf.area)
1677 snd_dma_free_pages(&chip->posbuf);
1678 pci_release_regions(chip->pci);
1679 pci_disable_device(chip->pci);
1680 kfree(chip->azx_dev);
1681 kfree(chip);
1682
1683 return 0;
1684 }
1685
1686 static int azx_dev_free(struct snd_device *device)
1687 {
1688 return azx_free(device->device_data);
1689 }
1690
1691 /*
1692 * white/black-listing for position_fix
1693 */
1694 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1695 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1696 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1697 {}
1698 };
1699
1700 static int __devinit check_position_fix(struct azx *chip, int fix)
1701 {
1702 const struct snd_pci_quirk *q;
1703
1704 if (fix == POS_FIX_AUTO) {
1705 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1706 if (q) {
1707 printk(KERN_INFO
1708 "hda_intel: position_fix set to %d "
1709 "for device %04x:%04x\n",
1710 q->value, q->subvendor, q->subdevice);
1711 return q->value;
1712 }
1713 }
1714 return fix;
1715 }
1716
1717 /*
1718 * black-lists for probe_mask
1719 */
1720 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1721 /* Thinkpad often breaks the controller communication when accessing
1722 * to the non-working (or non-existing) modem codec slot.
1723 */
1724 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1725 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1726 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1727 {}
1728 };
1729
1730 static void __devinit check_probe_mask(struct azx *chip, int dev)
1731 {
1732 const struct snd_pci_quirk *q;
1733
1734 if (probe_mask[dev] == -1) {
1735 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1736 if (q) {
1737 printk(KERN_INFO
1738 "hda_intel: probe_mask set to 0x%x "
1739 "for device %04x:%04x\n",
1740 q->value, q->subvendor, q->subdevice);
1741 probe_mask[dev] = q->value;
1742 }
1743 }
1744 }
1745
1746
1747 /*
1748 * constructor
1749 */
1750 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1751 int dev, int driver_type,
1752 struct azx **rchip)
1753 {
1754 struct azx *chip;
1755 int err;
1756 unsigned short gcap;
1757 static struct snd_device_ops ops = {
1758 .dev_free = azx_dev_free,
1759 };
1760
1761 *rchip = NULL;
1762
1763 err = pci_enable_device(pci);
1764 if (err < 0)
1765 return err;
1766
1767 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1768 if (!chip) {
1769 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1770 pci_disable_device(pci);
1771 return -ENOMEM;
1772 }
1773
1774 spin_lock_init(&chip->reg_lock);
1775 mutex_init(&chip->open_mutex);
1776 chip->card = card;
1777 chip->pci = pci;
1778 chip->irq = -1;
1779 chip->driver_type = driver_type;
1780 chip->msi = enable_msi;
1781
1782 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1783 check_probe_mask(chip, dev);
1784
1785 chip->single_cmd = single_cmd;
1786
1787 #if BITS_PER_LONG != 64
1788 /* Fix up base address on ULI M5461 */
1789 if (chip->driver_type == AZX_DRIVER_ULI) {
1790 u16 tmp3;
1791 pci_read_config_word(pci, 0x40, &tmp3);
1792 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1793 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1794 }
1795 #endif
1796
1797 err = pci_request_regions(pci, "ICH HD audio");
1798 if (err < 0) {
1799 kfree(chip);
1800 pci_disable_device(pci);
1801 return err;
1802 }
1803
1804 chip->addr = pci_resource_start(pci, 0);
1805 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1806 if (chip->remap_addr == NULL) {
1807 snd_printk(KERN_ERR SFX "ioremap error\n");
1808 err = -ENXIO;
1809 goto errout;
1810 }
1811
1812 if (chip->msi)
1813 if (pci_enable_msi(pci) < 0)
1814 chip->msi = 0;
1815
1816 if (azx_acquire_irq(chip, 0) < 0) {
1817 err = -EBUSY;
1818 goto errout;
1819 }
1820
1821 pci_set_master(pci);
1822 synchronize_irq(chip->irq);
1823
1824 gcap = azx_readw(chip, GCAP);
1825 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1826
1827 if (gcap) {
1828 /* read number of streams from GCAP register instead of using
1829 * hardcoded value
1830 */
1831 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1832 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1833 <<<<<<< HEAD:sound/pci/hda/hda_intel.c
1834 chip->playback_index_offset = (gcap & (0xF << 12)) >> 12;
1835 =======
1836 chip->playback_index_offset = chip->capture_streams;
1837 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/hda/hda_intel.c
1838 chip->capture_index_offset = 0;
1839 } else {
1840 /* gcap didn't give any info, switching to old method */
1841
1842 switch (chip->driver_type) {
1843 case AZX_DRIVER_ULI:
1844 chip->playback_streams = ULI_NUM_PLAYBACK;
1845 chip->capture_streams = ULI_NUM_CAPTURE;
1846 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1847 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1848 break;
1849 case AZX_DRIVER_ATIHDMI:
1850 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1851 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1852 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1853 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1854 break;
1855 default:
1856 chip->playback_streams = ICH6_NUM_PLAYBACK;
1857 chip->capture_streams = ICH6_NUM_CAPTURE;
1858 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1859 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1860 break;
1861 }
1862 }
1863 chip->num_streams = chip->playback_streams + chip->capture_streams;
1864 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1865 GFP_KERNEL);
1866 if (!chip->azx_dev) {
1867 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1868 goto errout;
1869 }
1870
1871 /* allocate memory for the BDL for each stream */
1872 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1873 snd_dma_pci_data(chip->pci),
1874 BDL_SIZE, &chip->bdl);
1875 if (err < 0) {
1876 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1877 goto errout;
1878 }
1879 /* allocate memory for the position buffer */
1880 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1881 snd_dma_pci_data(chip->pci),
1882 chip->num_streams * 8, &chip->posbuf);
1883 if (err < 0) {
1884 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1885 goto errout;
1886 }
1887 /* allocate CORB/RIRB */
1888 if (!chip->single_cmd) {
1889 err = azx_alloc_cmd_io(chip);
1890 if (err < 0)
1891 goto errout;
1892 }
1893
1894 /* initialize streams */
1895 azx_init_stream(chip);
1896
1897 /* initialize chip */
1898 azx_init_pci(chip);
1899 azx_init_chip(chip);
1900
1901 /* codec detection */
1902 if (!chip->codec_mask) {
1903 snd_printk(KERN_ERR SFX "no codecs found!\n");
1904 err = -ENODEV;
1905 goto errout;
1906 }
1907
1908 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1909 if (err <0) {
1910 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1911 goto errout;
1912 }
1913
1914 strcpy(card->driver, "HDA-Intel");
1915 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1916 sprintf(card->longname, "%s at 0x%lx irq %i",
1917 card->shortname, chip->addr, chip->irq);
1918
1919 *rchip = chip;
1920 return 0;
1921
1922 errout:
1923 azx_free(chip);
1924 return err;
1925 }
1926
1927 static void power_down_all_codecs(struct azx *chip)
1928 {
1929 #ifdef CONFIG_SND_HDA_POWER_SAVE
1930 /* The codecs were powered up in snd_hda_codec_new().
1931 * Now all initialization done, so turn them down if possible
1932 */
1933 struct hda_codec *codec;
1934 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1935 snd_hda_power_down(codec);
1936 }
1937 #endif
1938 }
1939
1940 static int __devinit azx_probe(struct pci_dev *pci,
1941 const struct pci_device_id *pci_id)
1942 {
1943 static int dev;
1944 struct snd_card *card;
1945 struct azx *chip;
1946 int err;
1947
1948 if (dev >= SNDRV_CARDS)
1949 return -ENODEV;
1950 if (!enable[dev]) {
1951 dev++;
1952 return -ENOENT;
1953 }
1954
1955 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1956 if (!card) {
1957 snd_printk(KERN_ERR SFX "Error creating card!\n");
1958 return -ENOMEM;
1959 }
1960
1961 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1962 if (err < 0) {
1963 snd_card_free(card);
1964 return err;
1965 }
1966 card->private_data = chip;
1967
1968 /* create codec instances */
1969 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1970 if (err < 0) {
1971 snd_card_free(card);
1972 return err;
1973 }
1974
1975 /* create PCM streams */
1976 err = azx_pcm_create(chip);
1977 if (err < 0) {
1978 snd_card_free(card);
1979 return err;
1980 }
1981
1982 /* create mixer controls */
1983 err = azx_mixer_create(chip);
1984 if (err < 0) {
1985 snd_card_free(card);
1986 return err;
1987 }
1988
1989 snd_card_set_dev(card, &pci->dev);
1990
1991 err = snd_card_register(card);
1992 if (err < 0) {
1993 snd_card_free(card);
1994 return err;
1995 }
1996
1997 pci_set_drvdata(pci, card);
1998 chip->running = 1;
1999 power_down_all_codecs(chip);
2000
2001 dev++;
2002 return err;
2003 }
2004
2005 static void __devexit azx_remove(struct pci_dev *pci)
2006 {
2007 snd_card_free(pci_get_drvdata(pci));
2008 pci_set_drvdata(pci, NULL);
2009 }
2010
2011 /* PCI IDs */
2012 static struct pci_device_id azx_ids[] = {
2013 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
2014 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
2015 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2016 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2017 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2018 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2019 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2020 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2021 { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2022 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2023 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2024 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2025 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2026 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2027 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2028 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2029 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2030 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2031 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2032 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2033 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2034 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2035 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2036 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2037 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2038 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2039 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2040 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2041 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2042 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2043 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2044 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2045 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2046 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2047 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2048 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2049 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2050 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2051 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2052 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2053 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2054 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2055 { 0, }
2056 };
2057 MODULE_DEVICE_TABLE(pci, azx_ids);
2058
2059 /* pci_driver definition */
2060 static struct pci_driver driver = {
2061 .name = "HDA Intel",
2062 .id_table = azx_ids,
2063 .probe = azx_probe,
2064 .remove = __devexit_p(azx_remove),
2065 #ifdef CONFIG_PM
2066 .suspend = azx_suspend,
2067 .resume = azx_resume,
2068 #endif
2069 };
2070
2071 static int __init alsa_card_azx_init(void)
2072 {
2073 return pci_register_driver(&driver);
2074 }
2075
2076 static void __exit alsa_card_azx_exit(void)
2077 {
2078 pci_unregister_driver(&driver);
2079 }
2080
2081 module_init(alsa_card_azx_init)
2082 module_exit(alsa_card_azx_exit)
WRT350N Kernel Patches