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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / sound / pci / ice1712 / phase.c
blob811bbccf7a0792f5fec29aa30c38dc69ad22c84a
1 /*
2 * ALSA driver for ICEnsemble ICE1724 (Envy24)
3 *
4 * Lowlevel functions for Terratec PHASE 22
5 *
6 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 /* PHASE 22 overview:
25 * Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
26 * Analog chip: AK4524 (partially via Philip's 74HCT125)
27 * Digital receiver: CS8414-CS (not supported in this release)
28 *
29 * Envy connects to AK4524
30 * - CS directly from GPIO 10
31 * - CCLK via 74HCT125's gate #4 from GPIO 4
32 * - CDTI via 74HCT125's gate #2 from GPIO 5
33 * CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
34 */
35
36 #include <asm/io.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/init.h>
40 #include <linux/slab.h>
41 #include <linux/mutex.h>
42
43 #include <sound/core.h>
44
45 #include "ice1712.h"
46 #include "envy24ht.h"
47 #include "phase.h"
48 #include <sound/tlv.h>
49
50 /* AC97 register cache for Phase28 */
51 struct phase28_spec {
52 unsigned short master[2];
53 unsigned short vol[8];
54 <<<<<<< HEAD:sound/pci/ice1712/phase.c
55 } phase28;
56 =======
57 };
58 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/ice1712/phase.c
59
60 /* WM8770 registers */
61 #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
62 #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
63 #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
64 #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
65 #define WM_PHASE_SWAP 0x12 /* DAC phase */
66 #define WM_DAC_CTRL1 0x13 /* DAC control bits */
67 #define WM_MUTE 0x14 /* mute controls */
68 #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
69 #define WM_INT_CTRL 0x16 /* interface control */
70 #define WM_MASTER 0x17 /* master clock and mode */
71 #define WM_POWERDOWN 0x18 /* power-down controls */
72 #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
73 #define WM_ADC_MUX 0x1b /* input MUX */
74 #define WM_OUT_MUX1 0x1c /* output MUX */
75 #define WM_OUT_MUX2 0x1e /* output MUX */
76 #define WM_RESET 0x1f /* software reset */
77
78
79 /*
80 * Logarithmic volume values for WM8770
81 * Computed as 20 * Log10(255 / x)
82 */
83 static const unsigned char wm_vol[256] = {
84 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
85 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
86 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
87 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
88 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
89 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
90 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
91 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
92 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
93 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
94 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
95 0, 0
96 };
97
98 #define WM_VOL_MAX (sizeof(wm_vol) - 1)
99 #define WM_VOL_MUTE 0x8000
100
101 static struct snd_akm4xxx akm_phase22 __devinitdata = {
102 .type = SND_AK4524,
103 .num_dacs = 2,
104 .num_adcs = 2,
105 };
106
107 static struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
108 .caddr = 2,
109 .cif = 1,
110 .data_mask = 1 << 4,
111 .clk_mask = 1 << 5,
112 .cs_mask = 1 << 10,
113 .cs_addr = 1 << 10,
114 .cs_none = 0,
115 .add_flags = 1 << 3,
116 .mask_flags = 0,
117 };
118
119 static int __devinit phase22_init(struct snd_ice1712 *ice)
120 {
121 struct snd_akm4xxx *ak;
122 int err;
123
124 // Configure DAC/ADC description for generic part of ice1724
125 switch (ice->eeprom.subvendor) {
126 case VT1724_SUBDEVICE_PHASE22:
127 ice->num_total_dacs = 2;
128 ice->num_total_adcs = 2;
129 ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
130 break;
131 default:
132 snd_BUG();
133 return -EINVAL;
134 }
135
136 // Initialize analog chips
137 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
138 if (! ak)
139 return -ENOMEM;
140 ice->akm_codecs = 1;
141 switch (ice->eeprom.subvendor) {
142 case VT1724_SUBDEVICE_PHASE22:
143 if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
144 return err;
145 break;
146 }
147
148 return 0;
149 }
150
151 static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
152 {
153 int err = 0;
154
155 switch (ice->eeprom.subvendor) {
156 case VT1724_SUBDEVICE_PHASE22:
157 err = snd_ice1712_akm4xxx_build_controls(ice);
158 if (err < 0)
159 return err;
160 }
161 return 0;
162 }
163
164 static unsigned char phase22_eeprom[] __devinitdata = {
165 [ICE_EEP2_SYSCONF] = 0x00, /* 1xADC, 1xDACs */
166 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
167 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit */
168 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
169 [ICE_EEP2_GPIO_DIR] = 0xff,
170 [ICE_EEP2_GPIO_DIR1] = 0xff,
171 [ICE_EEP2_GPIO_DIR2] = 0xff,
172 [ICE_EEP2_GPIO_MASK] = 0x00,
173 [ICE_EEP2_GPIO_MASK1] = 0x00,
174 [ICE_EEP2_GPIO_MASK2] = 0x00,
175 [ICE_EEP2_GPIO_STATE] = 0x00,
176 [ICE_EEP2_GPIO_STATE1] = 0x00,
177 [ICE_EEP2_GPIO_STATE2] = 0x00,
178 };
179
180 static unsigned char phase28_eeprom[] __devinitdata = {
181 [ICE_EEP2_SYSCONF] = 0x0b, /* clock 512, spdif-in/ADC, 4DACs */
182 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
183 [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
184 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
185 [ICE_EEP2_GPIO_DIR] = 0xff,
186 [ICE_EEP2_GPIO_DIR1] = 0xff,
187 [ICE_EEP2_GPIO_DIR2] = 0x5f,
188 [ICE_EEP2_GPIO_MASK] = 0x00,
189 [ICE_EEP2_GPIO_MASK1] = 0x00,
190 [ICE_EEP2_GPIO_MASK2] = 0x00,
191 [ICE_EEP2_GPIO_STATE] = 0x00,
192 [ICE_EEP2_GPIO_STATE1] = 0x00,
193 [ICE_EEP2_GPIO_STATE2] = 0x00,
194 };
195
196 /*
197 * write data in the SPI mode
198 */
199 static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
200 {
201 unsigned int tmp;
202 int i;
203
204 tmp = snd_ice1712_gpio_read(ice);
205
206 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
207 PHASE28_WM_CS));
208 tmp |= PHASE28_WM_RW;
209 tmp &= ~cs;
210 snd_ice1712_gpio_write(ice, tmp);
211 udelay(1);
212
213 for (i = bits - 1; i >= 0; i--) {
214 tmp &= ~PHASE28_SPI_CLK;
215 snd_ice1712_gpio_write(ice, tmp);
216 udelay(1);
217 if (data & (1 << i))
218 tmp |= PHASE28_SPI_MOSI;
219 else
220 tmp &= ~PHASE28_SPI_MOSI;
221 snd_ice1712_gpio_write(ice, tmp);
222 udelay(1);
223 tmp |= PHASE28_SPI_CLK;
224 snd_ice1712_gpio_write(ice, tmp);
225 udelay(1);
226 }
227
228 tmp &= ~PHASE28_SPI_CLK;
229 tmp |= cs;
230 snd_ice1712_gpio_write(ice, tmp);
231 udelay(1);
232 tmp |= PHASE28_SPI_CLK;
233 snd_ice1712_gpio_write(ice, tmp);
234 udelay(1);
235 }
236
237 /*
238 * get the current register value of WM codec
239 */
240 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
241 {
242 reg <<= 1;
243 return ((unsigned short)ice->akm[0].images[reg] << 8) |
244 ice->akm[0].images[reg + 1];
245 }
246
247 /*
248 * set the register value of WM codec
249 */
250 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
251 {
252 phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
253 }
254
255 /*
256 * set the register value of WM codec and remember it
257 */
258 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
259 {
260 wm_put_nocache(ice, reg, val);
261 reg <<= 1;
262 ice->akm[0].images[reg] = val >> 8;
263 ice->akm[0].images[reg + 1] = val;
264 }
265
266 static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
267 {
268 unsigned char nvol;
269
270 if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
271 nvol = 0;
272 else
273 nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
274
275 wm_put(ice, index, nvol);
276 wm_put_nocache(ice, index, 0x180 | nvol);
277 }
278
279 /*
280 * DAC mute control
281 */
282 #define wm_pcm_mute_info snd_ctl_boolean_mono_info
283
284 static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
285 {
286 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
287
288 mutex_lock(&ice->gpio_mutex);
289 ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
290 mutex_unlock(&ice->gpio_mutex);
291 return 0;
292 }
293
294 static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
295 {
296 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
297 unsigned short nval, oval;
298 int change;
299
300 snd_ice1712_save_gpio_status(ice);
301 oval = wm_get(ice, WM_MUTE);
302 nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
303 if ((change = (nval != oval)))
304 wm_put(ice, WM_MUTE, nval);
305 snd_ice1712_restore_gpio_status(ice);
306
307 return change;
308 }
309
310 /*
311 * Master volume attenuation mixer control
312 */
313 static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
314 {
315 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
316 uinfo->count = 2;
317 uinfo->value.integer.min = 0;
318 uinfo->value.integer.max = WM_VOL_MAX;
319 return 0;
320 }
321
322 static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
323 {
324 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
325 struct phase28_spec *spec = ice->spec;
326 int i;
327 for (i=0; i<2; i++)
328 ucontrol->value.integer.value[i] = spec->master[i] & ~WM_VOL_MUTE;
329 return 0;
330 }
331
332 static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
333 {
334 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
335 struct phase28_spec *spec = ice->spec;
336 int ch, change = 0;
337
338 snd_ice1712_save_gpio_status(ice);
339 for (ch = 0; ch < 2; ch++) {
340 unsigned int vol = ucontrol->value.integer.value[ch];
341 if (vol > WM_VOL_MAX)
342 continue;
343 vol |= spec->master[ch] & WM_VOL_MUTE;
344 if (vol != spec->master[ch]) {
345 int dac;
346 spec->master[ch] = vol;
347 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
348 wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
349 spec->vol[dac + ch],
350 spec->master[ch]);
351 change = 1;
352 }
353 }
354 snd_ice1712_restore_gpio_status(ice);
355 return change;
356 }
357
358 static int __devinit phase28_init(struct snd_ice1712 *ice)
359 {
360 static const unsigned short wm_inits_phase28[] = {
361 /* These come first to reduce init pop noise */
362 0x1b, 0x044, /* ADC Mux (AC'97 source) */
363 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
364 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
365
366 0x18, 0x000, /* All power-up */
367
368 0x16, 0x122, /* I2S, normal polarity, 24bit */
369 0x17, 0x022, /* 256fs, slave mode */
370 0x00, 0, /* DAC1 analog mute */
371 0x01, 0, /* DAC2 analog mute */
372 0x02, 0, /* DAC3 analog mute */
373 0x03, 0, /* DAC4 analog mute */
374 0x04, 0, /* DAC5 analog mute */
375 0x05, 0, /* DAC6 analog mute */
376 0x06, 0, /* DAC7 analog mute */
377 0x07, 0, /* DAC8 analog mute */
378 0x08, 0x100, /* master analog mute */
379 0x09, 0xff, /* DAC1 digital full */
380 0x0a, 0xff, /* DAC2 digital full */
381 0x0b, 0xff, /* DAC3 digital full */
382 0x0c, 0xff, /* DAC4 digital full */
383 0x0d, 0xff, /* DAC5 digital full */
384 0x0e, 0xff, /* DAC6 digital full */
385 0x0f, 0xff, /* DAC7 digital full */
386 0x10, 0xff, /* DAC8 digital full */
387 0x11, 0x1ff, /* master digital full */
388 0x12, 0x000, /* phase normal */
389 0x13, 0x090, /* unmute DAC L/R */
390 0x14, 0x000, /* all unmute */
391 0x15, 0x000, /* no deemphasis, no ZFLG */
392 0x19, 0x000, /* -12dB ADC/L */
393 0x1a, 0x000, /* -12dB ADC/R */
394 (unsigned short)-1
395 };
396
397 unsigned int tmp;
398 struct snd_akm4xxx *ak;
399 struct phase28_spec *spec;
400 const unsigned short *p;
401 int i;
402
403 ice->num_total_dacs = 8;
404 ice->num_total_adcs = 2;
405
406 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
407 if (!spec)
408 return -ENOMEM;
409 ice->spec = spec;
410
411 // Initialize analog chips
412 ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
413 if (!ak)
414 return -ENOMEM;
415 ice->akm_codecs = 1;
416
417 snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
418
419 /* reset the wm codec as the SPI mode */
420 snd_ice1712_save_gpio_status(ice);
421 snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
422
423 tmp = snd_ice1712_gpio_read(ice);
424 tmp &= ~PHASE28_WM_RESET;
425 snd_ice1712_gpio_write(ice, tmp);
426 udelay(1);
427 tmp |= PHASE28_WM_CS;
428 snd_ice1712_gpio_write(ice, tmp);
429 udelay(1);
430 tmp |= PHASE28_WM_RESET;
431 snd_ice1712_gpio_write(ice, tmp);
432 udelay(1);
433
434 p = wm_inits_phase28;
435 for (; *p != (unsigned short)-1; p += 2)
436 wm_put(ice, p[0], p[1]);
437
438 snd_ice1712_restore_gpio_status(ice);
439
440 spec->master[0] = WM_VOL_MUTE;
441 spec->master[1] = WM_VOL_MUTE;
442 for (i = 0; i < ice->num_total_dacs; i++) {
443 spec->vol[i] = WM_VOL_MUTE;
444 wm_set_vol(ice, i, spec->vol[i], spec->master[i % 2]);
445 }
446
447 return 0;
448 }
449
450 /*
451 * DAC volume attenuation mixer control
452 */
453 static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
454 {
455 int voices = kcontrol->private_value >> 8;
456 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
457 uinfo->count = voices;
458 uinfo->value.integer.min = 0; /* mute (-101dB) */
459 uinfo->value.integer.max = 0x7F; /* 0dB */
460 return 0;
461 }
462
463 static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
464 {
465 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
466 struct phase28_spec *spec = ice->spec;
467 int i, ofs, voices;
468
469 voices = kcontrol->private_value >> 8;
470 ofs = kcontrol->private_value & 0xff;
471 for (i = 0; i < voices; i++)
472 ucontrol->value.integer.value[i] =
473 spec->vol[ofs+i] & ~WM_VOL_MUTE;
474 return 0;
475 }
476
477 static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
478 {
479 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
480 struct phase28_spec *spec = ice->spec;
481 int i, idx, ofs, voices;
482 int change = 0;
483
484 voices = kcontrol->private_value >> 8;
485 ofs = kcontrol->private_value & 0xff;
486 snd_ice1712_save_gpio_status(ice);
487 for (i = 0; i < voices; i++) {
488 unsigned int vol;
489 vol = ucontrol->value.integer.value[i];
490 if (vol > 0x7f)
491 continue;
492 vol |= spec->vol[ofs+i] & WM_VOL_MUTE;
493 if (vol != spec->vol[ofs+i]) {
494 spec->vol[ofs+i] = vol;
495 idx = WM_DAC_ATTEN + ofs + i;
496 wm_set_vol(ice, idx, spec->vol[ofs+i],
497 spec->master[i]);
498 change = 1;
499 }
500 }
501 snd_ice1712_restore_gpio_status(ice);
502 return change;
503 }
504
505 /*
506 * WM8770 mute control
507 */
508 static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
509 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
510 uinfo->count = kcontrol->private_value >> 8;
511 uinfo->value.integer.min = 0;
512 uinfo->value.integer.max = 1;
513 return 0;
514 }
515
516 static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
517 {
518 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
519 struct phase28_spec *spec = ice->spec;
520 int voices, ofs, i;
521
522 voices = kcontrol->private_value >> 8;
523 ofs = kcontrol->private_value & 0xFF;
524
525 for (i = 0; i < voices; i++)
526 ucontrol->value.integer.value[i] =
527 (spec->vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
528 return 0;
529 }
530
531 static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
532 {
533 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
534 struct phase28_spec *spec = ice->spec;
535 int change = 0, voices, ofs, i;
536
537 voices = kcontrol->private_value >> 8;
538 ofs = kcontrol->private_value & 0xFF;
539
540 snd_ice1712_save_gpio_status(ice);
541 for (i = 0; i < voices; i++) {
542 int val = (spec->vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
543 if (ucontrol->value.integer.value[i] != val) {
544 spec->vol[ofs + i] &= ~WM_VOL_MUTE;
545 spec->vol[ofs + i] |=
546 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
547 wm_set_vol(ice, ofs + i, spec->vol[ofs + i],
548 spec->master[i]);
549 change = 1;
550 }
551 }
552 snd_ice1712_restore_gpio_status(ice);
553
554 return change;
555 }
556
557 /*
558 * WM8770 master mute control
559 */
560 #define wm_master_mute_info snd_ctl_boolean_stereo_info
561
562 static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
563 {
564 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
565 struct phase28_spec *spec = ice->spec;
566
567 ucontrol->value.integer.value[0] =
568 (spec->master[0] & WM_VOL_MUTE) ? 0 : 1;
569 ucontrol->value.integer.value[1] =
570 (spec->master[1] & WM_VOL_MUTE) ? 0 : 1;
571 return 0;
572 }
573
574 static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
575 {
576 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
577 struct phase28_spec *spec = ice->spec;
578 int change = 0, i;
579
580 snd_ice1712_save_gpio_status(ice);
581 for (i = 0; i < 2; i++) {
582 int val = (spec->master[i] & WM_VOL_MUTE) ? 0 : 1;
583 if (ucontrol->value.integer.value[i] != val) {
584 int dac;
585 spec->master[i] &= ~WM_VOL_MUTE;
586 spec->master[i] |=
587 ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
588 for (dac = 0; dac < ice->num_total_dacs; dac += 2)
589 wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
590 spec->vol[dac + i],
591 spec->master[i]);
592 change = 1;
593 }
594 }
595 snd_ice1712_restore_gpio_status(ice);
596
597 return change;
598 }
599
600 /* digital master volume */
601 #define PCM_0dB 0xff
602 #define PCM_RES 128 /* -64dB */
603 #define PCM_MIN (PCM_0dB - PCM_RES)
604 static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
605 {
606 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
607 uinfo->count = 1;
608 uinfo->value.integer.min = 0; /* mute (-64dB) */
609 uinfo->value.integer.max = PCM_RES; /* 0dB */
610 return 0;
611 }
612
613 static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
614 {
615 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
616 unsigned short val;
617
618 mutex_lock(&ice->gpio_mutex);
619 val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
620 val = val > PCM_MIN ? (val - PCM_MIN) : 0;
621 ucontrol->value.integer.value[0] = val;
622 mutex_unlock(&ice->gpio_mutex);
623 return 0;
624 }
625
626 static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
627 {
628 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
629 unsigned short ovol, nvol;
630 int change = 0;
631
632 nvol = ucontrol->value.integer.value[0];
633 if (nvol > PCM_RES)
634 return -EINVAL;
635 snd_ice1712_save_gpio_status(ice);
636 nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
637 ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
638 if (ovol != nvol) {
639 wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
640 wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
641 change = 1;
642 }
643 snd_ice1712_restore_gpio_status(ice);
644 return change;
645 }
646
647 /*
648 * Deemphasis
649 */
650 #define phase28_deemp_info snd_ctl_boolean_mono_info
651
652 static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
653 {
654 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
655 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
656 return 0;
657 }
658
659 static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
660 {
661 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
662 int temp, temp2;
663 temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
664 if (ucontrol->value.integer.value[0])
665 temp |= 0xf;
666 else
667 temp &= ~0xf;
668 if (temp != temp2) {
669 wm_put(ice, WM_DAC_CTRL2, temp);
670 return 1;
671 }
672 return 0;
673 }
674
675 /*
676 * ADC Oversampling
677 */
678 static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
679 {
680 static char *texts[2] = { "128x", "64x" };
681
682 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
683 uinfo->count = 1;
684 uinfo->value.enumerated.items = 2;
685
686 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
687 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
688 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
689
690 return 0;
691 }
692
693 static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
694 {
695 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
696 ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
697 return 0;
698 }
699
700 static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
701 {
702 int temp, temp2;
703 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
704
705 temp2 = temp = wm_get(ice, WM_MASTER);
706
707 if (ucontrol->value.enumerated.item[0])
708 temp |= 0x8;
709 else
710 temp &= ~0x8;
711
712 if (temp != temp2) {
713 wm_put(ice, WM_MASTER, temp);
714 return 1;
715 }
716 return 0;
717 }
718
719 static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
720 static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
721
722 static struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
723 {
724 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
725 .name = "Master Playback Switch",
726 .info = wm_master_mute_info,
727 .get = wm_master_mute_get,
728 .put = wm_master_mute_put
729 },
730 {
731 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
732 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
733 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
734 .name = "Master Playback Volume",
735 .info = wm_master_vol_info,
736 .get = wm_master_vol_get,
737 .put = wm_master_vol_put,
738 .tlv = { .p = db_scale_wm_dac }
739 },
740 {
741 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
742 .name = "Front Playback Switch",
743 .info = wm_mute_info,
744 .get = wm_mute_get,
745 .put = wm_mute_put,
746 .private_value = (2 << 8) | 0
747 },
748 {
749 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
750 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
751 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
752 .name = "Front Playback Volume",
753 .info = wm_vol_info,
754 .get = wm_vol_get,
755 .put = wm_vol_put,
756 .private_value = (2 << 8) | 0,
757 .tlv = { .p = db_scale_wm_dac }
758 },
759 {
760 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
761 .name = "Rear Playback Switch",
762 .info = wm_mute_info,
763 .get = wm_mute_get,
764 .put = wm_mute_put,
765 .private_value = (2 << 8) | 2
766 },
767 {
768 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
769 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
770 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
771 .name = "Rear Playback Volume",
772 .info = wm_vol_info,
773 .get = wm_vol_get,
774 .put = wm_vol_put,
775 .private_value = (2 << 8) | 2,
776 .tlv = { .p = db_scale_wm_dac }
777 },
778 {
779 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
780 .name = "Center Playback Switch",
781 .info = wm_mute_info,
782 .get = wm_mute_get,
783 .put = wm_mute_put,
784 .private_value = (1 << 8) | 4
785 },
786 {
787 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
788 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
789 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
790 .name = "Center Playback Volume",
791 .info = wm_vol_info,
792 .get = wm_vol_get,
793 .put = wm_vol_put,
794 .private_value = (1 << 8) | 4,
795 .tlv = { .p = db_scale_wm_dac }
796 },
797 {
798 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
799 .name = "LFE Playback Switch",
800 .info = wm_mute_info,
801 .get = wm_mute_get,
802 .put = wm_mute_put,
803 .private_value = (1 << 8) | 5
804 },
805 {
806 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
807 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
808 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
809 .name = "LFE Playback Volume",
810 .info = wm_vol_info,
811 .get = wm_vol_get,
812 .put = wm_vol_put,
813 .private_value = (1 << 8) | 5,
814 .tlv = { .p = db_scale_wm_dac }
815 },
816 {
817 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
818 .name = "Side Playback Switch",
819 .info = wm_mute_info,
820 .get = wm_mute_get,
821 .put = wm_mute_put,
822 .private_value = (2 << 8) | 6
823 },
824 {
825 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
826 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
827 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
828 .name = "Side Playback Volume",
829 .info = wm_vol_info,
830 .get = wm_vol_get,
831 .put = wm_vol_put,
832 .private_value = (2 << 8) | 6,
833 .tlv = { .p = db_scale_wm_dac }
834 }
835 };
836
837 static struct snd_kcontrol_new wm_controls[] __devinitdata = {
838 {
839 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
840 .name = "PCM Playback Switch",
841 .info = wm_pcm_mute_info,
842 .get = wm_pcm_mute_get,
843 .put = wm_pcm_mute_put
844 },
845 {
846 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
847 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
848 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
849 .name = "PCM Playback Volume",
850 .info = wm_pcm_vol_info,
851 .get = wm_pcm_vol_get,
852 .put = wm_pcm_vol_put,
853 .tlv = { .p = db_scale_wm_pcm }
854 },
855 {
856 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
857 .name = "DAC Deemphasis Switch",
858 .info = phase28_deemp_info,
859 .get = phase28_deemp_get,
860 .put = phase28_deemp_put
861 },
862 {
863 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
864 .name = "ADC Oversampling",
865 .info = phase28_oversampling_info,
866 .get = phase28_oversampling_get,
867 .put = phase28_oversampling_put
868 }
869 };
870
871 static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
872 {
873 unsigned int i, counts;
874 int err;
875
876 counts = ARRAY_SIZE(phase28_dac_controls);
877 for (i = 0; i < counts; i++) {
878 err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
879 if (err < 0)
880 return err;
881 }
882
883 for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
884 err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
885 if (err < 0)
886 return err;
887 }
888
889 return 0;
890 }
891
892 struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
893 {
894 .subvendor = VT1724_SUBDEVICE_PHASE22,
895 .name = "Terratec PHASE 22",
896 .model = "phase22",
897 .chip_init = phase22_init,
898 .build_controls = phase22_add_controls,
899 .eeprom_size = sizeof(phase22_eeprom),
900 .eeprom_data = phase22_eeprom,
901 },
902 {
903 .subvendor = VT1724_SUBDEVICE_PHASE28,
904 .name = "Terratec PHASE 28",
905 .model = "phase28",
906 .chip_init = phase28_init,
907 .build_controls = phase28_add_controls,
908 .eeprom_size = sizeof(phase28_eeprom),
909 .eeprom_data = phase28_eeprom,
910 },
911 { } /* terminator */
912 };
WRT350N Kernel Patches