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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / sound / pci / oxygen / oxygen_lib.c
blobf9d5211021fe81c3c7c123fb5ec2980140e3ecac
1 /*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
30 #include "oxygen.h"
31 #include "cm9780.h"
32
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL");
36
37
38 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
39 {
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
42
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
44 if (!status)
45 return IRQ_NONE;
46
47 spin_lock(&chip->reg_lock);
48
49 clear = status & (OXYGEN_CHANNEL_A |
50 OXYGEN_CHANNEL_B |
51 OXYGEN_CHANNEL_C |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
54 OXYGEN_CHANNEL_AC97 |
55 OXYGEN_INT_SPDIF_IN_DETECT |
56 OXYGEN_INT_GPIO |
57 OXYGEN_INT_AC97);
58 if (clear) {
59 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
60 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
62 chip->interrupt_mask & ~clear);
63 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
64 chip->interrupt_mask);
65 }
66
67 elapsed_streams = status & chip->pcm_running;
68
69 spin_unlock(&chip->reg_lock);
70
71 for (i = 0; i < PCM_COUNT; ++i)
72 if ((elapsed_streams & (1 << i)) && chip->streams[i])
73 snd_pcm_period_elapsed(chip->streams[i]);
74
75 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
76 spin_lock(&chip->reg_lock);
77 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
78 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
79 OXYGEN_SPDIF_RATE_INT)) {
80 /* write the interrupt bit(s) to clear */
81 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
82 schedule_work(&chip->spdif_input_bits_work);
83 }
84 spin_unlock(&chip->reg_lock);
85 }
86
87 if (status & OXYGEN_INT_GPIO)
88 schedule_work(&chip->gpio_work);
89
90 if ((status & OXYGEN_INT_MIDI) && chip->midi)
91 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
92
93 if (status & OXYGEN_INT_AC97)
94 wake_up(&chip->ac97_waitqueue);
95
96 return IRQ_HANDLED;
97 }
98
99 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
100 {
101 struct oxygen *chip = container_of(work, struct oxygen,
102 spdif_input_bits_work);
103 u32 reg;
104
105 /*
106 * This function gets called when there is new activity on the SPDIF
107 * input, or when we lose lock on the input signal, or when the rate
108 * changes.
109 */
110 msleep(1);
111 spin_lock_irq(&chip->reg_lock);
112 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
113 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
114 OXYGEN_SPDIF_LOCK_STATUS))
115 == OXYGEN_SPDIF_SENSE_STATUS) {
116 /*
117 * If we detect activity on the SPDIF input but cannot lock to
118 * a signal, the clock bit is likely to be wrong.
119 */
120 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
121 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
122 spin_unlock_irq(&chip->reg_lock);
123 msleep(1);
124 spin_lock_irq(&chip->reg_lock);
125 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
126 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
127 OXYGEN_SPDIF_LOCK_STATUS))
128 == OXYGEN_SPDIF_SENSE_STATUS) {
129 /* nothing detected with either clock; give up */
130 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
131 == OXYGEN_SPDIF_IN_CLOCK_192) {
132 /*
133 * Reset clock to <= 96 kHz because this is
134 * more likely to be received next time.
135 */
136 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
137 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
138 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
139 }
140 }
141 }
142 spin_unlock_irq(&chip->reg_lock);
143
144 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
145 spin_lock_irq(&chip->reg_lock);
146 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
147 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
148 chip->interrupt_mask);
149 spin_unlock_irq(&chip->reg_lock);
150
151 /*
152 * We don't actually know that any channel status bits have
153 * changed, but let's send a notification just to be sure.
154 */
155 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
156 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
157 }
158 }
159
160 static void oxygen_gpio_changed(struct work_struct *work)
161 {
162 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
163
164 if (chip->model->gpio_changed)
165 chip->model->gpio_changed(chip);
166 }
167
168 #ifdef CONFIG_PROC_FS
169 static void oxygen_proc_read(struct snd_info_entry *entry,
170 struct snd_info_buffer *buffer)
171 {
172 struct oxygen *chip = entry->private_data;
173 int i, j;
174
175 snd_iprintf(buffer, "CMI8788\n\n");
176 for (i = 0; i < 0x100; i += 0x10) {
177 snd_iprintf(buffer, "%02x:", i);
178 for (j = 0; j < 0x10; ++j)
179 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
180 snd_iprintf(buffer, "\n");
181 }
182 if (mutex_lock_interruptible(&chip->mutex) < 0)
183 return;
184 if (chip->has_ac97_0) {
185 snd_iprintf(buffer, "\nAC97\n");
186 for (i = 0; i < 0x80; i += 0x10) {
187 snd_iprintf(buffer, "%02x:", i);
188 for (j = 0; j < 0x10; j += 2)
189 snd_iprintf(buffer, " %04x",
190 oxygen_read_ac97(chip, 0, i + j));
191 snd_iprintf(buffer, "\n");
192 }
193 }
194 if (chip->has_ac97_1) {
195 snd_iprintf(buffer, "\nAC97 2\n");
196 for (i = 0; i < 0x80; i += 0x10) {
197 snd_iprintf(buffer, "%02x:", i);
198 for (j = 0; j < 0x10; j += 2)
199 snd_iprintf(buffer, " %04x",
200 oxygen_read_ac97(chip, 1, i + j));
201 snd_iprintf(buffer, "\n");
202 }
203 }
204 mutex_unlock(&chip->mutex);
205 }
206
207 <<<<<<< HEAD:sound/pci/oxygen/oxygen_lib.c
208 static void __devinit oxygen_proc_init(struct oxygen *chip)
209 =======
210 static void oxygen_proc_init(struct oxygen *chip)
211 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/oxygen/oxygen_lib.c
212 {
213 struct snd_info_entry *entry;
214
215 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
216 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
217 }
218 #else
219 #define oxygen_proc_init(chip)
220 #endif
221
222 <<<<<<< HEAD:sound/pci/oxygen/oxygen_lib.c
223 static void __devinit oxygen_init(struct oxygen *chip)
224 =======
225 static void oxygen_init(struct oxygen *chip)
226 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/oxygen/oxygen_lib.c
227 {
228 unsigned int i;
229
230 chip->dac_routing = 1;
231 for (i = 0; i < 8; ++i)
232 chip->dac_volume[i] = 0xff;
233 chip->spdif_playback_enable = 1;
234 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
235 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
236 chip->spdif_pcm_bits = chip->spdif_bits;
237
238 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
239 chip->revision = 2;
240 else
241 chip->revision = 1;
242
243 if (chip->revision == 1)
244 oxygen_set_bits8(chip, OXYGEN_MISC,
245 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
246
247 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
248 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
249 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
250
251 oxygen_set_bits8(chip, OXYGEN_FUNCTION,
252 OXYGEN_FUNCTION_RESET_CODEC |
253 chip->model->function_flags);
254 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
255 OXYGEN_FUNCTION_SPI,
256 OXYGEN_FUNCTION_2WIRE_SPI_MASK);
257 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
258 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
259 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
260 OXYGEN_PLAY_CHANNELS_2 |
261 OXYGEN_DMA_A_BURST_8 |
262 OXYGEN_DMA_MULTICH_BURST_8);
263 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
264 oxygen_write8_masked(chip, OXYGEN_MISC, 0,
265 OXYGEN_MISC_WRITE_PCI_SUBID |
266 OXYGEN_MISC_REC_C_FROM_SPDIF |
267 OXYGEN_MISC_REC_B_FROM_AC97 |
268 OXYGEN_MISC_REC_A_FROM_MULTICH);
269 oxygen_write8(chip, OXYGEN_REC_FORMAT,
270 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
271 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
272 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
273 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
274 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
275 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
276 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
277 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
278 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
279 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
280 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
281 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
282 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
283 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
284 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
285 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
286 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
287 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
288 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
289 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
290 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
291 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
292 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
293 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
294 OXYGEN_SPDIF_SENSE_MASK |
295 OXYGEN_SPDIF_LOCK_MASK |
296 OXYGEN_SPDIF_RATE_MASK |
297 OXYGEN_SPDIF_LOCK_PAR |
298 OXYGEN_SPDIF_IN_CLOCK_96,
299 OXYGEN_SPDIF_OUT_ENABLE |
300 OXYGEN_SPDIF_LOOPBACK |
301 OXYGEN_SPDIF_SENSE_MASK |
302 OXYGEN_SPDIF_LOCK_MASK |
303 OXYGEN_SPDIF_RATE_MASK |
304 OXYGEN_SPDIF_SENSE_PAR |
305 OXYGEN_SPDIF_LOCK_PAR |
306 OXYGEN_SPDIF_IN_CLOCK_MASK);
307 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
308 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
309 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
310 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
311 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
312 OXYGEN_PLAY_MULTICH_I2S_DAC |
313 OXYGEN_PLAY_SPDIF_SPDIF |
314 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
315 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
316 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
317 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
318 oxygen_write8(chip, OXYGEN_REC_ROUTING,
319 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
320 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
321 OXYGEN_REC_C_ROUTE_SPDIF);
322 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
323 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
324 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
325 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
326 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
327 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
328
329 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
330 OXYGEN_AC97_INT_READ_DONE |
331 OXYGEN_AC97_INT_WRITE_DONE);
332 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
333 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
334 if (!(chip->has_ac97_0 | chip->has_ac97_1))
335 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
336 OXYGEN_AC97_CLOCK_DISABLE);
337 if (!chip->has_ac97_0) {
338 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
339 OXYGEN_AC97_NO_CODEC_0);
340 } else {
341 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
342 msleep(1);
343 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
344 CM9780_GPIO0IO | CM9780_GPIO1IO);
345 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
346 CM9780_BSTSEL | CM9780_STRO_MIC |
347 CM9780_MIX2FR | CM9780_PCBSW);
348 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
349 CM9780_RSOE | CM9780_CBOE |
350 CM9780_SSOE | CM9780_FROE |
351 CM9780_MIC2MIC | CM9780_LI2LI);
352 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
353 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
354 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
355 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
356 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
357 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
358 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
359 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
360 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
361 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
362 /* power down unused ADCs and DACs */
363 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
364 AC97_PD_PR0 | AC97_PD_PR1);
365 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
366 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
367 }
368 if (chip->has_ac97_1) {
369 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
370 OXYGEN_AC97_CODEC1_SLOT3 |
371 OXYGEN_AC97_CODEC1_SLOT4);
372 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
373 msleep(1);
374 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
375 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
376 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
377 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
378 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
379 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
380 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
381 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
382 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
383 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
384 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
385 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
386 }
387 }
388
389 static void oxygen_card_free(struct snd_card *card)
390 {
391 struct oxygen *chip = card->private_data;
392
393 spin_lock_irq(&chip->reg_lock);
394 chip->interrupt_mask = 0;
395 chip->pcm_running = 0;
396 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
397 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
398 spin_unlock_irq(&chip->reg_lock);
399 if (chip->irq >= 0) {
400 free_irq(chip->irq, chip);
401 synchronize_irq(chip->irq);
402 }
403 flush_scheduled_work();
404 chip->model->cleanup(chip);
405 mutex_destroy(&chip->mutex);
406 pci_release_regions(chip->pci);
407 pci_disable_device(chip->pci);
408 }
409
410 <<<<<<< HEAD:sound/pci/oxygen/oxygen_lib.c
411 int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
412 int midi, const struct oxygen_model *model)
413 =======
414 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
415 int midi, const struct oxygen_model *model)
416 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/oxygen/oxygen_lib.c
417 {
418 struct snd_card *card;
419 struct oxygen *chip;
420 int err;
421
422 card = snd_card_new(index, id, model->owner,
423 sizeof *chip + model->model_data_size);
424 if (!card)
425 return -ENOMEM;
426
427 chip = card->private_data;
428 chip->card = card;
429 chip->pci = pci;
430 chip->irq = -1;
431 chip->model = model;
432 chip->model_data = chip + 1;
433 spin_lock_init(&chip->reg_lock);
434 mutex_init(&chip->mutex);
435 INIT_WORK(&chip->spdif_input_bits_work,
436 oxygen_spdif_input_bits_changed);
437 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
438 init_waitqueue_head(&chip->ac97_waitqueue);
439
440 err = pci_enable_device(pci);
441 if (err < 0)
442 goto err_card;
443
444 err = pci_request_regions(pci, model->chip);
445 if (err < 0) {
446 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
447 goto err_pci_enable;
448 }
449
450 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
451 pci_resource_len(pci, 0) < 0x100) {
452 snd_printk(KERN_ERR "invalid PCI I/O range\n");
453 err = -ENXIO;
454 goto err_pci_regions;
455 }
456 chip->addr = pci_resource_start(pci, 0);
457
458 pci_set_master(pci);
459 snd_card_set_dev(card, &pci->dev);
460 card->private_free = oxygen_card_free;
461
462 oxygen_init(chip);
463 model->init(chip);
464
465 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
466 model->chip, chip);
467 if (err < 0) {
468 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
469 goto err_card;
470 }
471 chip->irq = pci->irq;
472
473 strcpy(card->driver, model->chip);
474 strcpy(card->shortname, model->shortname);
475 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
476 model->longname, chip->revision, chip->addr, chip->irq);
477 strcpy(card->mixername, model->chip);
478 snd_component_add(card, model->chip);
479
480 err = oxygen_pcm_init(chip);
481 if (err < 0)
482 goto err_card;
483
484 err = oxygen_mixer_init(chip);
485 if (err < 0)
486 goto err_card;
487
488 oxygen_write8_masked(chip, OXYGEN_MISC,
489 midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
490 if (midi) {
491 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
492 chip->addr + OXYGEN_MPU401,
493 MPU401_INFO_INTEGRATED, 0, 0,
494 &chip->midi);
495 if (err < 0)
496 goto err_card;
497 }
498
499 oxygen_proc_init(chip);
500
501 spin_lock_irq(&chip->reg_lock);
502 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT | OXYGEN_INT_AC97;
503 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
504 spin_unlock_irq(&chip->reg_lock);
505
506 err = snd_card_register(card);
507 if (err < 0)
508 goto err_card;
509
510 pci_set_drvdata(pci, card);
511 return 0;
512
513 err_pci_regions:
514 pci_release_regions(pci);
515 err_pci_enable:
516 pci_disable_device(pci);
517 err_card:
518 snd_card_free(card);
519 return err;
520 }
521 EXPORT_SYMBOL(oxygen_pci_probe);
522
523 <<<<<<< HEAD:sound/pci/oxygen/oxygen_lib.c
524 void __devexit oxygen_pci_remove(struct pci_dev *pci)
525 =======
526 void oxygen_pci_remove(struct pci_dev *pci)
527 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/oxygen/oxygen_lib.c
528 {
529 snd_card_free(pci_get_drvdata(pci));
530 pci_set_drvdata(pci, NULL);
531 }
532 EXPORT_SYMBOL(oxygen_pci_remove);
WRT350N Kernel Patches