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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / sound / pci / rme9652 / hdsp.c
blob890505aaba0c791c48cda83451d258e2ba995acb
1 /*
2 * ALSA driver for RME Hammerfall DSP audio interface(s)
3 *
4 * Copyright (c) 2002 Paul Davis
5 * Marcus Andersson
6 * Thomas Charbonnel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/slab.h>
28 #include <linux/pci.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31
32 #include <sound/core.h>
33 #include <sound/control.h>
34 #include <sound/pcm.h>
35 #include <sound/info.h>
36 #include <sound/asoundef.h>
37 #include <sound/rawmidi.h>
38 #include <sound/hwdep.h>
39 #include <sound/initval.h>
40 #include <sound/hdsp.h>
41
42 #include <asm/byteorder.h>
43 #include <asm/current.h>
44 #include <asm/io.h>
45
46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
49
50 module_param_array(index, int, NULL, 0444);
51 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
52 module_param_array(id, charp, NULL, 0444);
53 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
54 module_param_array(enable, bool, NULL, 0444);
55 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
56 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
57 MODULE_DESCRIPTION("RME Hammerfall DSP");
58 MODULE_LICENSE("GPL");
59 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
60 "{RME HDSP-9652},"
61 "{RME HDSP-9632}}");
62 #ifdef HDSP_FW_LOADER
63 MODULE_FIRMWARE("multiface_firmware.bin");
64 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
65 MODULE_FIRMWARE("digiface_firmware.bin");
66 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
67 #endif
68
69 #define HDSP_MAX_CHANNELS 26
70 #define HDSP_MAX_DS_CHANNELS 14
71 #define HDSP_MAX_QS_CHANNELS 8
72 #define DIGIFACE_SS_CHANNELS 26
73 #define DIGIFACE_DS_CHANNELS 14
74 #define MULTIFACE_SS_CHANNELS 18
75 #define MULTIFACE_DS_CHANNELS 14
76 #define H9652_SS_CHANNELS 26
77 #define H9652_DS_CHANNELS 14
78 /* This does not include possible Analog Extension Boards
79 AEBs are detected at card initialization
80 */
81 #define H9632_SS_CHANNELS 12
82 #define H9632_DS_CHANNELS 8
83 #define H9632_QS_CHANNELS 4
84
85 /* Write registers. These are defined as byte-offsets from the iobase value.
86 */
87 #define HDSP_resetPointer 0
88 #define HDSP_freqReg 0
89 #define HDSP_outputBufferAddress 32
90 #define HDSP_inputBufferAddress 36
91 #define HDSP_controlRegister 64
92 #define HDSP_interruptConfirmation 96
93 #define HDSP_outputEnable 128
94 #define HDSP_control2Reg 256
95 #define HDSP_midiDataOut0 352
96 #define HDSP_midiDataOut1 356
97 #define HDSP_fifoData 368
98 #define HDSP_inputEnable 384
99
100 /* Read registers. These are defined as byte-offsets from the iobase value
101 */
102
103 #define HDSP_statusRegister 0
104 #define HDSP_timecode 128
105 #define HDSP_status2Register 192
106 #define HDSP_midiDataIn0 360
107 #define HDSP_midiDataIn1 364
108 #define HDSP_midiStatusOut0 384
109 #define HDSP_midiStatusOut1 388
110 #define HDSP_midiStatusIn0 392
111 #define HDSP_midiStatusIn1 396
112 #define HDSP_fifoStatus 400
113
114 /* the meters are regular i/o-mapped registers, but offset
115 considerably from the rest. the peak registers are reset
116 when read; the least-significant 4 bits are full-scale counters;
117 the actual peak value is in the most-significant 24 bits.
118 */
119
120 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */
121 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */
122 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */
123 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */
124 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */
125
126
127 /* This is for H9652 cards
128 Peak values are read downward from the base
129 Rms values are read upward
130 There are rms values for the outputs too
131 26*3 values are read in ss mode
132 14*3 in ds mode, with no gap between values
133 */
134 #define HDSP_9652_peakBase 7164
135 #define HDSP_9652_rmsBase 4096
136
137 /* c.f. the hdsp_9632_meters_t struct */
138 #define HDSP_9632_metersBase 4096
139
140 #define HDSP_IO_EXTENT 7168
141
142 /* control2 register bits */
143
144 #define HDSP_TMS 0x01
145 #define HDSP_TCK 0x02
146 #define HDSP_TDI 0x04
147 #define HDSP_JTAG 0x08
148 #define HDSP_PWDN 0x10
149 #define HDSP_PROGRAM 0x020
150 #define HDSP_CONFIG_MODE_0 0x040
151 #define HDSP_CONFIG_MODE_1 0x080
152 #define HDSP_VERSION_BIT 0x100
153 #define HDSP_BIGENDIAN_MODE 0x200
154 #define HDSP_RD_MULTIPLE 0x400
155 #define HDSP_9652_ENABLE_MIXER 0x800
156 #define HDSP_TDO 0x10000000
157
158 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
159 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
160
161 /* Control Register bits */
162
163 #define HDSP_Start (1<<0) /* start engine */
164 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */
165 #define HDSP_Latency1 (1<<2) /* [ see above ] */
166 #define HDSP_Latency2 (1<<3) /* [ see above ] */
167 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */
168 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */
169 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
170 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */
171 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
172 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */
173 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */
174 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */
175 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
176 #define HDSP_SyncRef2 (1<<13)
177 #define HDSP_SPDIFInputSelect0 (1<<14)
178 #define HDSP_SPDIFInputSelect1 (1<<15)
179 #define HDSP_SyncRef0 (1<<16)
180 #define HDSP_SyncRef1 (1<<17)
181 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
182 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */
183 #define HDSP_Midi0InterruptEnable (1<<22)
184 #define HDSP_Midi1InterruptEnable (1<<23)
185 #define HDSP_LineOut (1<<24)
186 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */
187 #define HDSP_ADGain1 (1<<26)
188 #define HDSP_DAGain0 (1<<27)
189 #define HDSP_DAGain1 (1<<28)
190 #define HDSP_PhoneGain0 (1<<29)
191 #define HDSP_PhoneGain1 (1<<30)
192 #define HDSP_QuadSpeed (1<<31)
193
194 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
195 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask
196 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
197 #define HDSP_ADGainLowGain 0
198
199 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
200 #define HDSP_DAGainHighGain HDSP_DAGainMask
201 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
202 #define HDSP_DAGainMinus10dBV 0
203
204 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
205 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask
206 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
207 #define HDSP_PhoneGainMinus12dB 0
208
209 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
210 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
211
212 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
213 #define HDSP_SPDIFInputADAT1 0
214 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
215 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
216 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
217
218 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
219 #define HDSP_SyncRef_ADAT1 0
220 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
221 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
222 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
223 #define HDSP_SyncRef_WORD (HDSP_SyncRef2)
224 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
225
226 /* Sample Clock Sources */
227
228 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0
229 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
230 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
231 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
232 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
233 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
234 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
235 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
236 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
237 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
238
239 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
240
241 #define HDSP_SYNC_FROM_WORD 0
242 #define HDSP_SYNC_FROM_SPDIF 1
243 #define HDSP_SYNC_FROM_ADAT1 2
244 #define HDSP_SYNC_FROM_ADAT_SYNC 3
245 #define HDSP_SYNC_FROM_ADAT2 4
246 #define HDSP_SYNC_FROM_ADAT3 5
247
248 /* SyncCheck status */
249
250 #define HDSP_SYNC_CHECK_NO_LOCK 0
251 #define HDSP_SYNC_CHECK_LOCK 1
252 #define HDSP_SYNC_CHECK_SYNC 2
253
254 /* AutoSync references - used by "autosync_ref" control switch */
255
256 #define HDSP_AUTOSYNC_FROM_WORD 0
257 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
258 #define HDSP_AUTOSYNC_FROM_SPDIF 2
259 #define HDSP_AUTOSYNC_FROM_NONE 3
260 #define HDSP_AUTOSYNC_FROM_ADAT1 4
261 #define HDSP_AUTOSYNC_FROM_ADAT2 5
262 #define HDSP_AUTOSYNC_FROM_ADAT3 6
263
264 /* Possible sources of S/PDIF input */
265
266 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */
267 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */
268 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
269 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/
270
271 #define HDSP_Frequency32KHz HDSP_Frequency0
272 #define HDSP_Frequency44_1KHz HDSP_Frequency1
273 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
274 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
275 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
276 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
277 /* For H9632 cards */
278 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
279 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
280 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
281 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
282 return 104857600000000 / rate; // 100 MHz
283 return 110100480000000 / rate; // 105 MHz
284 */
285 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */
286
287 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
288 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
289
290 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
291 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
292
293 /* Status Register bits */
294
295 #define HDSP_audioIRQPending (1<<0)
296 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */
297 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */
298 #define HDSP_Lock1 (1<<2)
299 #define HDSP_Lock0 (1<<3)
300 #define HDSP_SPDIFSync (1<<4)
301 #define HDSP_TimecodeLock (1<<5)
302 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
303 #define HDSP_Sync2 (1<<16)
304 #define HDSP_Sync1 (1<<17)
305 #define HDSP_Sync0 (1<<18)
306 #define HDSP_DoubleSpeedStatus (1<<19)
307 #define HDSP_ConfigError (1<<20)
308 #define HDSP_DllError (1<<21)
309 #define HDSP_spdifFrequency0 (1<<22)
310 #define HDSP_spdifFrequency1 (1<<23)
311 #define HDSP_spdifFrequency2 (1<<24)
312 #define HDSP_SPDIFErrorFlag (1<<25)
313 #define HDSP_BufferID (1<<26)
314 #define HDSP_TimecodeSync (1<<27)
315 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */
316 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */
317 #define HDSP_midi0IRQPending (1<<30)
318 #define HDSP_midi1IRQPending (1<<31)
319
320 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
321
322 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
323 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
324 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
325
326 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
327 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
328 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
329
330 /* This is for H9632 cards */
331 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask
332 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
333 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
334
335 /* Status2 Register bits */
336
337 #define HDSP_version0 (1<<0)
338 #define HDSP_version1 (1<<1)
339 #define HDSP_version2 (1<<2)
340 #define HDSP_wc_lock (1<<3)
341 #define HDSP_wc_sync (1<<4)
342 #define HDSP_inp_freq0 (1<<5)
343 #define HDSP_inp_freq1 (1<<6)
344 #define HDSP_inp_freq2 (1<<7)
345 #define HDSP_SelSyncRef0 (1<<8)
346 #define HDSP_SelSyncRef1 (1<<9)
347 #define HDSP_SelSyncRef2 (1<<10)
348
349 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
350
351 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
352 #define HDSP_systemFrequency32 (HDSP_inp_freq0)
353 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
354 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
355 #define HDSP_systemFrequency64 (HDSP_inp_freq2)
356 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
357 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
358 /* FIXME : more values for 9632 cards ? */
359
360 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
361 #define HDSP_SelSyncRef_ADAT1 0
362 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
363 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
364 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
365 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
366 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
367
368 /* Card state flags */
369
370 #define HDSP_InitializationComplete (1<<0)
371 #define HDSP_FirmwareLoaded (1<<1)
372 #define HDSP_FirmwareCached (1<<2)
373
374 /* FIFO wait times, defined in terms of 1/10ths of msecs */
375
376 #define HDSP_LONG_WAIT 5000
377 #define HDSP_SHORT_WAIT 30
378
379 #define UNITY_GAIN 32768
380 #define MINUS_INFINITY_GAIN 0
381
382 /* the size of a substream (1 mono data stream) */
383
384 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
385 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
386
387 /* the size of the area we need to allocate for DMA transfers. the
388 size is the same regardless of the number of channels - the
389 Multiface still uses the same memory area.
390
391 Note that we allocate 1 more channel than is apparently needed
392 because the h/w seems to write 1 byte beyond the end of the last
393 page. Sigh.
394 */
395
396 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
397 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
398
399 /* use hotplug firmeare loader? */
400 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
401 #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP)
402 #define HDSP_FW_LOADER
403 #endif
404 #endif
405
406 struct hdsp_9632_meters {
407 u32 input_peak[16];
408 u32 playback_peak[16];
409 u32 output_peak[16];
410 u32 xxx_peak[16];
411 u32 padding[64];
412 u32 input_rms_low[16];
413 u32 playback_rms_low[16];
414 u32 output_rms_low[16];
415 u32 xxx_rms_low[16];
416 u32 input_rms_high[16];
417 u32 playback_rms_high[16];
418 u32 output_rms_high[16];
419 u32 xxx_rms_high[16];
420 };
421
422 struct hdsp_midi {
423 struct hdsp *hdsp;
424 int id;
425 struct snd_rawmidi *rmidi;
426 struct snd_rawmidi_substream *input;
427 struct snd_rawmidi_substream *output;
428 char istimer; /* timer in use */
429 struct timer_list timer;
430 spinlock_t lock;
431 int pending;
432 };
433
434 struct hdsp {
435 spinlock_t lock;
436 struct snd_pcm_substream *capture_substream;
437 struct snd_pcm_substream *playback_substream;
438 struct hdsp_midi midi[2];
439 struct tasklet_struct midi_tasklet;
440 int use_midi_tasklet;
441 int precise_ptr;
442 u32 control_register; /* cached value */
443 u32 control2_register; /* cached value */
444 u32 creg_spdif;
445 u32 creg_spdif_stream;
446 int clock_source_locked;
447 char *card_name; /* digiface/multiface */
448 enum HDSP_IO_Type io_type; /* ditto, but for code use */
449 unsigned short firmware_rev;
450 unsigned short state; /* stores state bits */
451 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */
452 size_t period_bytes; /* guess what this is */
453 unsigned char max_channels;
454 unsigned char qs_in_channels; /* quad speed mode for H9632 */
455 unsigned char ds_in_channels;
456 unsigned char ss_in_channels; /* different for multiface/digiface */
457 unsigned char qs_out_channels;
458 unsigned char ds_out_channels;
459 unsigned char ss_out_channels;
460
461 struct snd_dma_buffer capture_dma_buf;
462 struct snd_dma_buffer playback_dma_buf;
463 unsigned char *capture_buffer; /* suitably aligned address */
464 unsigned char *playback_buffer; /* suitably aligned address */
465
466 pid_t capture_pid;
467 pid_t playback_pid;
468 int running;
469 int system_sample_rate;
470 char *channel_map;
471 int dev;
472 int irq;
473 unsigned long port;
474 void __iomem *iobase;
475 struct snd_card *card;
476 struct snd_pcm *pcm;
477 struct snd_hwdep *hwdep;
478 struct pci_dev *pci;
479 struct snd_kcontrol *spdif_ctl;
480 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
481 unsigned int dds_value; /* last value written to freq register */
482 };
483
484 /* These tables map the ALSA channels 1..N to the channels that we
485 need to use in order to find the relevant channel buffer. RME
486 refer to this kind of mapping as between "the ADAT channel and
487 the DMA channel." We index it using the logical audio channel,
488 and the value is the DMA channel (i.e. channel buffer number)
489 where the data for that channel can be read/written from/to.
490 */
491
492 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
493 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
494 18, 19, 20, 21, 22, 23, 24, 25
495 };
496
497 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
498 /* Analog */
499 0, 1, 2, 3, 4, 5, 6, 7,
500 /* ADAT 2 */
501 16, 17, 18, 19, 20, 21, 22, 23,
502 /* SPDIF */
503 24, 25,
504 -1, -1, -1, -1, -1, -1, -1, -1
505 };
506
507 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
508 /* ADAT channels are remapped */
509 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
510 /* channels 12 and 13 are S/PDIF */
511 24, 25,
512 /* others don't exist */
513 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
514 };
515
516 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
517 /* ADAT channels */
518 0, 1, 2, 3, 4, 5, 6, 7,
519 /* SPDIF */
520 8, 9,
521 /* Analog */
522 10, 11,
523 /* AO4S-192 and AI4S-192 extension boards */
524 12, 13, 14, 15,
525 /* others don't exist */
526 -1, -1, -1, -1, -1, -1, -1, -1,
527 -1, -1
528 };
529
530 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
531 /* ADAT */
532 1, 3, 5, 7,
533 /* SPDIF */
534 8, 9,
535 /* Analog */
536 10, 11,
537 /* AO4S-192 and AI4S-192 extension boards */
538 12, 13, 14, 15,
539 /* others don't exist */
540 -1, -1, -1, -1, -1, -1, -1, -1,
541 -1, -1, -1, -1, -1, -1
542 };
543
544 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
545 /* ADAT is disabled in this mode */
546 /* SPDIF */
547 8, 9,
548 /* Analog */
549 10, 11,
550 /* AO4S-192 and AI4S-192 extension boards */
551 12, 13, 14, 15,
552 /* others don't exist */
553 -1, -1, -1, -1, -1, -1, -1, -1,
554 -1, -1, -1, -1, -1, -1, -1, -1,
555 -1, -1
556 };
557
558 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
559 {
560 dmab->dev.type = SNDRV_DMA_TYPE_DEV;
561 dmab->dev.dev = snd_dma_pci_data(pci);
562 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) {
563 if (dmab->bytes >= size)
564 return 0;
565 }
566 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
567 size, dmab) < 0)
568 return -ENOMEM;
569 return 0;
570 }
571
572 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
573 {
574 if (dmab->area) {
575 dmab->dev.dev = NULL; /* make it anonymous */
576 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci));
577 }
578 }
579
580
581 static struct pci_device_id snd_hdsp_ids[] = {
582 {
583 .vendor = PCI_VENDOR_ID_XILINX,
584 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
585 .subvendor = PCI_ANY_ID,
586 .subdevice = PCI_ANY_ID,
587 }, /* RME Hammerfall-DSP */
588 { 0, },
589 };
590
591 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
592
593 /* prototypes */
594 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
595 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
596 static int snd_hdsp_enable_io (struct hdsp *hdsp);
597 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
598 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
599 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
600 static int hdsp_autosync_ref(struct hdsp *hdsp);
601 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
602 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
603
604 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
605 {
606 switch (hdsp->io_type) {
607 case Multiface:
608 case Digiface:
609 default:
610 if (hdsp->firmware_rev == 0xa)
611 return (64 * out) + (32 + (in));
612 else
613 return (52 * out) + (26 + (in));
614 case H9632:
615 return (32 * out) + (16 + (in));
616 case H9652:
617 return (52 * out) + (26 + (in));
618 }
619 }
620
621 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
622 {
623 switch (hdsp->io_type) {
624 case Multiface:
625 case Digiface:
626 default:
627 if (hdsp->firmware_rev == 0xa)
628 return (64 * out) + in;
629 else
630 return (52 * out) + in;
631 case H9632:
632 return (32 * out) + in;
633 case H9652:
634 return (52 * out) + in;
635 }
636 }
637
638 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
639 {
640 writel(val, hdsp->iobase + reg);
641 }
642
643 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
644 {
645 return readl (hdsp->iobase + reg);
646 }
647
648 static int hdsp_check_for_iobox (struct hdsp *hdsp)
649 {
650
651 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
652 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) {
653 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n");
654 hdsp->state &= ~HDSP_FirmwareLoaded;
655 return -EIO;
656 }
657 return 0;
658
659 }
660
661 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
662
663 int i;
664 unsigned long flags;
665
666 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
667
668 snd_printk ("Hammerfall-DSP: loading firmware\n");
669
670 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
671 hdsp_write (hdsp, HDSP_fifoData, 0);
672
673 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
674 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
675 return -EIO;
676 }
677
678 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
679
680 for (i = 0; i < 24413; ++i) {
681 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]);
682 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
683 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
684 return -EIO;
685 }
686 }
687
688 ssleep(3);
689
690 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
691 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n");
692 return -EIO;
693 }
694
695 #ifdef SNDRV_BIG_ENDIAN
696 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
697 #else
698 hdsp->control2_register = 0;
699 #endif
700 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
701 snd_printk ("Hammerfall-DSP: finished firmware loading\n");
702
703 }
704 if (hdsp->state & HDSP_InitializationComplete) {
705 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
706 spin_lock_irqsave(&hdsp->lock, flags);
707 snd_hdsp_set_defaults(hdsp);
708 spin_unlock_irqrestore(&hdsp->lock, flags);
709 }
710
711 hdsp->state |= HDSP_FirmwareLoaded;
712
713 return 0;
714 }
715
716 static int hdsp_get_iobox_version (struct hdsp *hdsp)
717 {
718 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
719
720 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM);
721 hdsp_write (hdsp, HDSP_fifoData, 0);
722 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0)
723 return -EIO;
724
725 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
726 hdsp_write (hdsp, HDSP_fifoData, 0);
727
728 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) {
729 hdsp->io_type = Multiface;
730 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT);
731 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
732 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT);
733 } else {
734 hdsp->io_type = Digiface;
735 }
736 } else {
737 /* firmware was already loaded, get iobox type */
738 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
739 hdsp->io_type = Multiface;
740 else
741 hdsp->io_type = Digiface;
742 }
743 return 0;
744 }
745
746
747 #ifdef HDSP_FW_LOADER
748 <<<<<<< HEAD:sound/pci/rme9652/hdsp.c
749 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp);
750 =======
751 static int hdsp_request_fw_loader(struct hdsp *hdsp);
752 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/rme9652/hdsp.c
753 #endif
754
755 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
756 {
757 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
758 return 0;
759 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
760 hdsp->state &= ~HDSP_FirmwareLoaded;
761 if (! load_on_demand)
762 return -EIO;
763 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
764 /* try to load firmware */
765 if (! (hdsp->state & HDSP_FirmwareCached)) {
766 #ifdef HDSP_FW_LOADER
767 if (! hdsp_request_fw_loader(hdsp))
768 return 0;
769 #endif
770 snd_printk(KERN_ERR
771 "Hammerfall-DSP: No firmware loaded nor "
772 "cached, please upload firmware.\n");
773 return -EIO;
774 }
775 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
776 snd_printk(KERN_ERR
777 "Hammerfall-DSP: Firmware loading from "
778 "cache failed, please upload manually.\n");
779 return -EIO;
780 }
781 }
782 return 0;
783 }
784
785
786 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
787 {
788 int i;
789
790 /* the fifoStatus registers reports on how many words
791 are available in the command FIFO.
792 */
793
794 for (i = 0; i < timeout; i++) {
795
796 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
797 return 0;
798
799 /* not very friendly, but we only do this during a firmware
800 load and changing the mixer, so we just put up with it.
801 */
802
803 udelay (100);
804 }
805
806 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
807 count, timeout);
808 return -1;
809 }
810
811 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
812 {
813 if (addr >= HDSP_MATRIX_MIXER_SIZE)
814 return 0;
815
816 return hdsp->mixer_matrix[addr];
817 }
818
819 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
820 {
821 unsigned int ad;
822
823 if (addr >= HDSP_MATRIX_MIXER_SIZE)
824 return -1;
825
826 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
827
828 /* from martin bjornsen:
829
830 "You can only write dwords to the
831 mixer memory which contain two
832 mixer values in the low and high
833 word. So if you want to change
834 value 0 you have to read value 1
835 from the cache and write both to
836 the first dword in the mixer
837 memory."
838 */
839
840 if (hdsp->io_type == H9632 && addr >= 512)
841 return 0;
842
843 if (hdsp->io_type == H9652 && addr >= 1352)
844 return 0;
845
846 hdsp->mixer_matrix[addr] = data;
847
848
849 /* `addr' addresses a 16-bit wide address, but
850 the address space accessed via hdsp_write
851 uses byte offsets. put another way, addr
852 varies from 0 to 1351, but to access the
853 corresponding memory location, we need
854 to access 0 to 2703 ...
855 */
856 ad = addr/2;
857
858 hdsp_write (hdsp, 4096 + (ad*4),
859 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
860 hdsp->mixer_matrix[addr&0x7fe]);
861
862 return 0;
863
864 } else {
865
866 ad = (addr << 16) + data;
867
868 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
869 return -1;
870
871 hdsp_write (hdsp, HDSP_fifoData, ad);
872 hdsp->mixer_matrix[addr] = data;
873
874 }
875
876 return 0;
877 }
878
879 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
880 {
881 unsigned long flags;
882 int ret = 1;
883
884 spin_lock_irqsave(&hdsp->lock, flags);
885 if ((hdsp->playback_pid != hdsp->capture_pid) &&
886 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
887 ret = 0;
888 spin_unlock_irqrestore(&hdsp->lock, flags);
889 return ret;
890 }
891
892 static int hdsp_external_sample_rate (struct hdsp *hdsp)
893 {
894 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
895 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
896
897 switch (rate_bits) {
898 case HDSP_systemFrequency32: return 32000;
899 case HDSP_systemFrequency44_1: return 44100;
900 case HDSP_systemFrequency48: return 48000;
901 case HDSP_systemFrequency64: return 64000;
902 case HDSP_systemFrequency88_2: return 88200;
903 case HDSP_systemFrequency96: return 96000;
904 default:
905 return 0;
906 }
907 }
908
909 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
910 {
911 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
912 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
913
914 if (status & HDSP_SPDIFErrorFlag)
915 return 0;
916
917 switch (rate_bits) {
918 case HDSP_spdifFrequency32KHz: return 32000;
919 case HDSP_spdifFrequency44_1KHz: return 44100;
920 case HDSP_spdifFrequency48KHz: return 48000;
921 case HDSP_spdifFrequency64KHz: return 64000;
922 case HDSP_spdifFrequency88_2KHz: return 88200;
923 case HDSP_spdifFrequency96KHz: return 96000;
924 case HDSP_spdifFrequency128KHz:
925 if (hdsp->io_type == H9632) return 128000;
926 break;
927 case HDSP_spdifFrequency176_4KHz:
928 if (hdsp->io_type == H9632) return 176400;
929 break;
930 case HDSP_spdifFrequency192KHz:
931 if (hdsp->io_type == H9632) return 192000;
932 break;
933 default:
934 break;
935 }
936 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
937 return 0;
938 }
939
940 static void hdsp_compute_period_size(struct hdsp *hdsp)
941 {
942 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
943 }
944
945 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
946 {
947 int position;
948
949 position = hdsp_read(hdsp, HDSP_statusRegister);
950
951 if (!hdsp->precise_ptr)
952 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
953
954 position &= HDSP_BufferPositionMask;
955 position /= 4;
956 position &= (hdsp->period_bytes/2) - 1;
957 return position;
958 }
959
960 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
961 {
962 hdsp_write (hdsp, HDSP_resetPointer, 0);
963 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
964 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
965 * requires (?) to write again DDS value after a reset pointer
966 * (at least, it works like this) */
967 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
968 }
969
970 static void hdsp_start_audio(struct hdsp *s)
971 {
972 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
973 hdsp_write(s, HDSP_controlRegister, s->control_register);
974 }
975
976 static void hdsp_stop_audio(struct hdsp *s)
977 {
978 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
979 hdsp_write(s, HDSP_controlRegister, s->control_register);
980 }
981
982 static void hdsp_silence_playback(struct hdsp *hdsp)
983 {
984 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
985 }
986
987 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
988 {
989 int n;
990
991 spin_lock_irq(&s->lock);
992
993 frames >>= 7;
994 n = 0;
995 while (frames) {
996 n++;
997 frames >>= 1;
998 }
999
1000 s->control_register &= ~HDSP_LatencyMask;
1001 s->control_register |= hdsp_encode_latency(n);
1002
1003 hdsp_write(s, HDSP_controlRegister, s->control_register);
1004
1005 hdsp_compute_period_size(s);
1006
1007 spin_unlock_irq(&s->lock);
1008
1009 return 0;
1010 }
1011
1012 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1013 {
1014 u64 n;
1015 u32 r;
1016
1017 if (rate >= 112000)
1018 rate /= 4;
1019 else if (rate >= 56000)
1020 rate /= 2;
1021
1022 n = DDS_NUMERATOR;
1023 div64_32(&n, rate, &r);
1024 /* n should be less than 2^32 for being written to FREQ register */
1025 snd_assert((n >> 32) == 0);
1026 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1027 value to write it after a reset */
1028 hdsp->dds_value = n;
1029 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1030 }
1031
1032 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1033 {
1034 int reject_if_open = 0;
1035 int current_rate;
1036 int rate_bits;
1037
1038 /* ASSUMPTION: hdsp->lock is either held, or
1039 there is no need for it (e.g. during module
1040 initialization).
1041 */
1042
1043 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1044 if (called_internally) {
1045 /* request from ctl or card initialization */
1046 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1047 return -1;
1048 } else {
1049 /* hw_param request while in AutoSync mode */
1050 int external_freq = hdsp_external_sample_rate(hdsp);
1051 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1052
1053 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1054 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1055 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1056 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1057 else if (rate != external_freq) {
1058 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1059 return -1;
1060 }
1061 }
1062 }
1063
1064 current_rate = hdsp->system_sample_rate;
1065
1066 /* Changing from a "single speed" to a "double speed" rate is
1067 not allowed if any substreams are open. This is because
1068 such a change causes a shift in the location of
1069 the DMA buffers and a reduction in the number of available
1070 buffers.
1071
1072 Note that a similar but essentially insoluble problem
1073 exists for externally-driven rate changes. All we can do
1074 is to flag rate changes in the read/write routines. */
1075
1076 if (rate > 96000 && hdsp->io_type != H9632)
1077 return -EINVAL;
1078
1079 switch (rate) {
1080 case 32000:
1081 if (current_rate > 48000)
1082 reject_if_open = 1;
1083 rate_bits = HDSP_Frequency32KHz;
1084 break;
1085 case 44100:
1086 if (current_rate > 48000)
1087 reject_if_open = 1;
1088 rate_bits = HDSP_Frequency44_1KHz;
1089 break;
1090 case 48000:
1091 if (current_rate > 48000)
1092 reject_if_open = 1;
1093 rate_bits = HDSP_Frequency48KHz;
1094 break;
1095 case 64000:
1096 if (current_rate <= 48000 || current_rate > 96000)
1097 reject_if_open = 1;
1098 rate_bits = HDSP_Frequency64KHz;
1099 break;
1100 case 88200:
1101 if (current_rate <= 48000 || current_rate > 96000)
1102 reject_if_open = 1;
1103 rate_bits = HDSP_Frequency88_2KHz;
1104 break;
1105 case 96000:
1106 if (current_rate <= 48000 || current_rate > 96000)
1107 reject_if_open = 1;
1108 rate_bits = HDSP_Frequency96KHz;
1109 break;
1110 case 128000:
1111 if (current_rate < 128000)
1112 reject_if_open = 1;
1113 rate_bits = HDSP_Frequency128KHz;
1114 break;
1115 case 176400:
1116 if (current_rate < 128000)
1117 reject_if_open = 1;
1118 rate_bits = HDSP_Frequency176_4KHz;
1119 break;
1120 case 192000:
1121 if (current_rate < 128000)
1122 reject_if_open = 1;
1123 rate_bits = HDSP_Frequency192KHz;
1124 break;
1125 default:
1126 return -EINVAL;
1127 }
1128
1129 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1130 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1131 hdsp->capture_pid,
1132 hdsp->playback_pid);
1133 return -EBUSY;
1134 }
1135
1136 hdsp->control_register &= ~HDSP_FrequencyMask;
1137 hdsp->control_register |= rate_bits;
1138 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1139
1140 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1141 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1142 hdsp_set_dds_value(hdsp, rate);
1143
1144 if (rate >= 128000) {
1145 hdsp->channel_map = channel_map_H9632_qs;
1146 } else if (rate > 48000) {
1147 if (hdsp->io_type == H9632)
1148 hdsp->channel_map = channel_map_H9632_ds;
1149 else
1150 hdsp->channel_map = channel_map_ds;
1151 } else {
1152 switch (hdsp->io_type) {
1153 case Multiface:
1154 hdsp->channel_map = channel_map_mf_ss;
1155 break;
1156 case Digiface:
1157 case H9652:
1158 hdsp->channel_map = channel_map_df_ss;
1159 break;
1160 case H9632:
1161 hdsp->channel_map = channel_map_H9632_ss;
1162 break;
1163 default:
1164 /* should never happen */
1165 break;
1166 }
1167 }
1168
1169 hdsp->system_sample_rate = rate;
1170
1171 return 0;
1172 }
1173
1174 /*----------------------------------------------------------------------------
1175 MIDI
1176 ----------------------------------------------------------------------------*/
1177
1178 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1179 {
1180 /* the hardware already does the relevant bit-mask with 0xff */
1181 if (id)
1182 return hdsp_read(hdsp, HDSP_midiDataIn1);
1183 else
1184 return hdsp_read(hdsp, HDSP_midiDataIn0);
1185 }
1186
1187 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1188 {
1189 /* the hardware already does the relevant bit-mask with 0xff */
1190 if (id)
1191 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1192 else
1193 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1194 }
1195
1196 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1197 {
1198 if (id)
1199 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1200 else
1201 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1202 }
1203
1204 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1205 {
1206 int fifo_bytes_used;
1207
1208 if (id)
1209 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1210 else
1211 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1212
1213 if (fifo_bytes_used < 128)
1214 return 128 - fifo_bytes_used;
1215 else
1216 return 0;
1217 }
1218
1219 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1220 {
1221 while (snd_hdsp_midi_input_available (hdsp, id))
1222 snd_hdsp_midi_read_byte (hdsp, id);
1223 }
1224
1225 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1226 {
1227 unsigned long flags;
1228 int n_pending;
1229 int to_write;
1230 int i;
1231 unsigned char buf[128];
1232
1233 /* Output is not interrupt driven */
1234
1235 spin_lock_irqsave (&hmidi->lock, flags);
1236 if (hmidi->output) {
1237 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1238 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1239 if (n_pending > (int)sizeof (buf))
1240 n_pending = sizeof (buf);
1241
1242 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1243 for (i = 0; i < to_write; ++i)
1244 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1245 }
1246 }
1247 }
1248 }
1249 spin_unlock_irqrestore (&hmidi->lock, flags);
1250 return 0;
1251 }
1252
1253 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1254 {
1255 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1256 unsigned long flags;
1257 int n_pending;
1258 int i;
1259
1260 spin_lock_irqsave (&hmidi->lock, flags);
1261 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1262 if (hmidi->input) {
1263 if (n_pending > (int)sizeof (buf))
1264 n_pending = sizeof (buf);
1265 for (i = 0; i < n_pending; ++i)
1266 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1267 if (n_pending)
1268 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1269 } else {
1270 /* flush the MIDI input FIFO */
1271 while (--n_pending)
1272 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1273 }
1274 }
1275 hmidi->pending = 0;
1276 if (hmidi->id)
1277 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1278 else
1279 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1280 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1281 spin_unlock_irqrestore (&hmidi->lock, flags);
1282 return snd_hdsp_midi_output_write (hmidi);
1283 }
1284
1285 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1286 {
1287 struct hdsp *hdsp;
1288 struct hdsp_midi *hmidi;
1289 unsigned long flags;
1290 u32 ie;
1291
1292 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1293 hdsp = hmidi->hdsp;
1294 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1295 spin_lock_irqsave (&hdsp->lock, flags);
1296 if (up) {
1297 if (!(hdsp->control_register & ie)) {
1298 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1299 hdsp->control_register |= ie;
1300 }
1301 } else {
1302 hdsp->control_register &= ~ie;
1303 tasklet_kill(&hdsp->midi_tasklet);
1304 }
1305
1306 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1307 spin_unlock_irqrestore (&hdsp->lock, flags);
1308 }
1309
1310 static void snd_hdsp_midi_output_timer(unsigned long data)
1311 {
1312 struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1313 unsigned long flags;
1314
1315 snd_hdsp_midi_output_write(hmidi);
1316 spin_lock_irqsave (&hmidi->lock, flags);
1317
1318 /* this does not bump hmidi->istimer, because the
1319 kernel automatically removed the timer when it
1320 expired, and we are now adding it back, thus
1321 leaving istimer wherever it was set before.
1322 */
1323
1324 if (hmidi->istimer) {
1325 hmidi->timer.expires = 1 + jiffies;
1326 add_timer(&hmidi->timer);
1327 }
1328
1329 spin_unlock_irqrestore (&hmidi->lock, flags);
1330 }
1331
1332 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1333 {
1334 struct hdsp_midi *hmidi;
1335 unsigned long flags;
1336
1337 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1338 spin_lock_irqsave (&hmidi->lock, flags);
1339 if (up) {
1340 if (!hmidi->istimer) {
1341 init_timer(&hmidi->timer);
1342 hmidi->timer.function = snd_hdsp_midi_output_timer;
1343 hmidi->timer.data = (unsigned long) hmidi;
1344 hmidi->timer.expires = 1 + jiffies;
1345 add_timer(&hmidi->timer);
1346 hmidi->istimer++;
1347 }
1348 } else {
1349 if (hmidi->istimer && --hmidi->istimer <= 0)
1350 del_timer (&hmidi->timer);
1351 }
1352 spin_unlock_irqrestore (&hmidi->lock, flags);
1353 if (up)
1354 snd_hdsp_midi_output_write(hmidi);
1355 }
1356
1357 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1358 {
1359 struct hdsp_midi *hmidi;
1360
1361 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1362 spin_lock_irq (&hmidi->lock);
1363 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1364 hmidi->input = substream;
1365 spin_unlock_irq (&hmidi->lock);
1366
1367 return 0;
1368 }
1369
1370 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1371 {
1372 struct hdsp_midi *hmidi;
1373
1374 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1375 spin_lock_irq (&hmidi->lock);
1376 hmidi->output = substream;
1377 spin_unlock_irq (&hmidi->lock);
1378
1379 return 0;
1380 }
1381
1382 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1383 {
1384 struct hdsp_midi *hmidi;
1385
1386 snd_hdsp_midi_input_trigger (substream, 0);
1387
1388 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1389 spin_lock_irq (&hmidi->lock);
1390 hmidi->input = NULL;
1391 spin_unlock_irq (&hmidi->lock);
1392
1393 return 0;
1394 }
1395
1396 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1397 {
1398 struct hdsp_midi *hmidi;
1399
1400 snd_hdsp_midi_output_trigger (substream, 0);
1401
1402 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1403 spin_lock_irq (&hmidi->lock);
1404 hmidi->output = NULL;
1405 spin_unlock_irq (&hmidi->lock);
1406
1407 return 0;
1408 }
1409
1410 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1411 {
1412 .open = snd_hdsp_midi_output_open,
1413 .close = snd_hdsp_midi_output_close,
1414 .trigger = snd_hdsp_midi_output_trigger,
1415 };
1416
1417 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1418 {
1419 .open = snd_hdsp_midi_input_open,
1420 .close = snd_hdsp_midi_input_close,
1421 .trigger = snd_hdsp_midi_input_trigger,
1422 };
1423
1424 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1425 {
1426 char buf[32];
1427
1428 hdsp->midi[id].id = id;
1429 hdsp->midi[id].rmidi = NULL;
1430 hdsp->midi[id].input = NULL;
1431 hdsp->midi[id].output = NULL;
1432 hdsp->midi[id].hdsp = hdsp;
1433 hdsp->midi[id].istimer = 0;
1434 hdsp->midi[id].pending = 0;
1435 spin_lock_init (&hdsp->midi[id].lock);
1436
1437 sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1438 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1439 return -1;
1440
1441 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1);
1442 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1443
1444 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1445 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1446
1447 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1448 SNDRV_RAWMIDI_INFO_INPUT |
1449 SNDRV_RAWMIDI_INFO_DUPLEX;
1450
1451 return 0;
1452 }
1453
1454 /*-----------------------------------------------------------------------------
1455 Control Interface
1456 ----------------------------------------------------------------------------*/
1457
1458 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1459 {
1460 u32 val = 0;
1461 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1462 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1463 if (val & HDSP_SPDIFProfessional)
1464 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1465 else
1466 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1467 return val;
1468 }
1469
1470 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1471 {
1472 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1473 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1474 if (val & HDSP_SPDIFProfessional)
1475 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1476 else
1477 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1478 }
1479
1480 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1481 {
1482 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1483 uinfo->count = 1;
1484 return 0;
1485 }
1486
1487 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1488 {
1489 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1490
1491 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1492 return 0;
1493 }
1494
1495 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1496 {
1497 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1498 int change;
1499 u32 val;
1500
1501 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1502 spin_lock_irq(&hdsp->lock);
1503 change = val != hdsp->creg_spdif;
1504 hdsp->creg_spdif = val;
1505 spin_unlock_irq(&hdsp->lock);
1506 return change;
1507 }
1508
1509 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1510 {
1511 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1512 uinfo->count = 1;
1513 return 0;
1514 }
1515
1516 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1517 {
1518 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1519
1520 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1521 return 0;
1522 }
1523
1524 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1525 {
1526 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1527 int change;
1528 u32 val;
1529
1530 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1531 spin_lock_irq(&hdsp->lock);
1532 change = val != hdsp->creg_spdif_stream;
1533 hdsp->creg_spdif_stream = val;
1534 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1535 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1536 spin_unlock_irq(&hdsp->lock);
1537 return change;
1538 }
1539
1540 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1541 {
1542 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1543 uinfo->count = 1;
1544 return 0;
1545 }
1546
1547 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1548 {
1549 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1550 return 0;
1551 }
1552
1553 #define HDSP_SPDIF_IN(xname, xindex) \
1554 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1555 .name = xname, \
1556 .index = xindex, \
1557 .info = snd_hdsp_info_spdif_in, \
1558 .get = snd_hdsp_get_spdif_in, \
1559 .put = snd_hdsp_put_spdif_in }
1560
1561 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1562 {
1563 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1564 }
1565
1566 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1567 {
1568 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1569 hdsp->control_register |= hdsp_encode_spdif_in(in);
1570 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1571 return 0;
1572 }
1573
1574 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1575 {
1576 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1578
1579 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1580 uinfo->count = 1;
1581 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1582 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1583 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1584 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1585 return 0;
1586 }
1587
1588 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1589 {
1590 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1591
1592 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1593 return 0;
1594 }
1595
1596 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1597 {
1598 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1599 int change;
1600 unsigned int val;
1601
1602 if (!snd_hdsp_use_is_exclusive(hdsp))
1603 return -EBUSY;
1604 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1605 spin_lock_irq(&hdsp->lock);
1606 change = val != hdsp_spdif_in(hdsp);
1607 if (change)
1608 hdsp_set_spdif_input(hdsp, val);
1609 spin_unlock_irq(&hdsp->lock);
1610 return change;
1611 }
1612
1613 #define HDSP_SPDIF_OUT(xname, xindex) \
1614 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1615 .info = snd_hdsp_info_spdif_bits, \
1616 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out }
1617
1618 static int hdsp_spdif_out(struct hdsp *hdsp)
1619 {
1620 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0;
1621 }
1622
1623 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out)
1624 {
1625 if (out)
1626 hdsp->control_register |= HDSP_SPDIFOpticalOut;
1627 else
1628 hdsp->control_register &= ~HDSP_SPDIFOpticalOut;
1629 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1630 return 0;
1631 }
1632
1633 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info
1634
1635 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1636 {
1637 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1638
1639 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp);
1640 return 0;
1641 }
1642
1643 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1644 {
1645 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1646 int change;
1647 unsigned int val;
1648
1649 if (!snd_hdsp_use_is_exclusive(hdsp))
1650 return -EBUSY;
1651 val = ucontrol->value.integer.value[0] & 1;
1652 spin_lock_irq(&hdsp->lock);
1653 change = (int)val != hdsp_spdif_out(hdsp);
1654 hdsp_set_spdif_output(hdsp, val);
1655 spin_unlock_irq(&hdsp->lock);
1656 return change;
1657 }
1658
1659 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \
1660 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1661 .info = snd_hdsp_info_spdif_bits, \
1662 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional }
1663
1664 static int hdsp_spdif_professional(struct hdsp *hdsp)
1665 {
1666 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0;
1667 }
1668
1669 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val)
1670 {
1671 if (val)
1672 hdsp->control_register |= HDSP_SPDIFProfessional;
1673 else
1674 hdsp->control_register &= ~HDSP_SPDIFProfessional;
1675 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1676 return 0;
1677 }
1678
1679 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1680 {
1681 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1682
1683 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp);
1684 return 0;
1685 }
1686
1687 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1688 {
1689 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1690 int change;
1691 unsigned int val;
1692
1693 if (!snd_hdsp_use_is_exclusive(hdsp))
1694 return -EBUSY;
1695 val = ucontrol->value.integer.value[0] & 1;
1696 spin_lock_irq(&hdsp->lock);
1697 change = (int)val != hdsp_spdif_professional(hdsp);
1698 hdsp_set_spdif_professional(hdsp, val);
1699 spin_unlock_irq(&hdsp->lock);
1700 return change;
1701 }
1702
1703 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \
1704 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1705 .info = snd_hdsp_info_spdif_bits, \
1706 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis }
1707
1708 static int hdsp_spdif_emphasis(struct hdsp *hdsp)
1709 {
1710 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0;
1711 }
1712
1713 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val)
1714 {
1715 if (val)
1716 hdsp->control_register |= HDSP_SPDIFEmphasis;
1717 else
1718 hdsp->control_register &= ~HDSP_SPDIFEmphasis;
1719 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1720 return 0;
1721 }
1722
1723 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1724 {
1725 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1726
1727 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp);
1728 return 0;
1729 }
1730
1731 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1732 {
1733 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1734 int change;
1735 unsigned int val;
1736
1737 if (!snd_hdsp_use_is_exclusive(hdsp))
1738 return -EBUSY;
1739 val = ucontrol->value.integer.value[0] & 1;
1740 spin_lock_irq(&hdsp->lock);
1741 change = (int)val != hdsp_spdif_emphasis(hdsp);
1742 hdsp_set_spdif_emphasis(hdsp, val);
1743 spin_unlock_irq(&hdsp->lock);
1744 return change;
1745 }
1746
1747 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \
1748 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
1749 .info = snd_hdsp_info_spdif_bits, \
1750 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio }
1751
1752 static int hdsp_spdif_nonaudio(struct hdsp *hdsp)
1753 {
1754 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0;
1755 }
1756
1757 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val)
1758 {
1759 if (val)
1760 hdsp->control_register |= HDSP_SPDIFNonAudio;
1761 else
1762 hdsp->control_register &= ~HDSP_SPDIFNonAudio;
1763 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1764 return 0;
1765 }
1766
1767 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1768 {
1769 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1770
1771 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp);
1772 return 0;
1773 }
1774
1775 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1776 {
1777 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1778 int change;
1779 unsigned int val;
1780
1781 if (!snd_hdsp_use_is_exclusive(hdsp))
1782 return -EBUSY;
1783 val = ucontrol->value.integer.value[0] & 1;
1784 spin_lock_irq(&hdsp->lock);
1785 change = (int)val != hdsp_spdif_nonaudio(hdsp);
1786 hdsp_set_spdif_nonaudio(hdsp, val);
1787 spin_unlock_irq(&hdsp->lock);
1788 return change;
1789 }
1790
1791 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1792 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1793 .name = xname, \
1794 .index = xindex, \
1795 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1796 .info = snd_hdsp_info_spdif_sample_rate, \
1797 .get = snd_hdsp_get_spdif_sample_rate \
1798 }
1799
1800 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1801 {
1802 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1804
1805 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1806 uinfo->count = 1;
1807 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1808 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1809 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1810 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1811 return 0;
1812 }
1813
1814 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1815 {
1816 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1817
1818 switch (hdsp_spdif_sample_rate(hdsp)) {
1819 case 32000:
1820 ucontrol->value.enumerated.item[0] = 0;
1821 break;
1822 case 44100:
1823 ucontrol->value.enumerated.item[0] = 1;
1824 break;
1825 case 48000:
1826 ucontrol->value.enumerated.item[0] = 2;
1827 break;
1828 case 64000:
1829 ucontrol->value.enumerated.item[0] = 3;
1830 break;
1831 case 88200:
1832 ucontrol->value.enumerated.item[0] = 4;
1833 break;
1834 case 96000:
1835 ucontrol->value.enumerated.item[0] = 5;
1836 break;
1837 case 128000:
1838 ucontrol->value.enumerated.item[0] = 7;
1839 break;
1840 case 176400:
1841 ucontrol->value.enumerated.item[0] = 8;
1842 break;
1843 case 192000:
1844 ucontrol->value.enumerated.item[0] = 9;
1845 break;
1846 default:
1847 ucontrol->value.enumerated.item[0] = 6;
1848 }
1849 return 0;
1850 }
1851
1852 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1853 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1854 .name = xname, \
1855 .index = xindex, \
1856 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1857 .info = snd_hdsp_info_system_sample_rate, \
1858 .get = snd_hdsp_get_system_sample_rate \
1859 }
1860
1861 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1862 {
1863 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1864 uinfo->count = 1;
1865 return 0;
1866 }
1867
1868 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1869 {
1870 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1871
1872 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1873 return 0;
1874 }
1875
1876 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1877 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1878 .name = xname, \
1879 .index = xindex, \
1880 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1881 .info = snd_hdsp_info_autosync_sample_rate, \
1882 .get = snd_hdsp_get_autosync_sample_rate \
1883 }
1884
1885 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1886 {
1887 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1888 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1889 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1890 uinfo->count = 1;
1891 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1892 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1893 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1894 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1895 return 0;
1896 }
1897
1898 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1899 {
1900 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1901
1902 switch (hdsp_external_sample_rate(hdsp)) {
1903 case 32000:
1904 ucontrol->value.enumerated.item[0] = 0;
1905 break;
1906 case 44100:
1907 ucontrol->value.enumerated.item[0] = 1;
1908 break;
1909 case 48000:
1910 ucontrol->value.enumerated.item[0] = 2;
1911 break;
1912 case 64000:
1913 ucontrol->value.enumerated.item[0] = 3;
1914 break;
1915 case 88200:
1916 ucontrol->value.enumerated.item[0] = 4;
1917 break;
1918 case 96000:
1919 ucontrol->value.enumerated.item[0] = 5;
1920 break;
1921 case 128000:
1922 ucontrol->value.enumerated.item[0] = 7;
1923 break;
1924 case 176400:
1925 ucontrol->value.enumerated.item[0] = 8;
1926 break;
1927 case 192000:
1928 ucontrol->value.enumerated.item[0] = 9;
1929 break;
1930 default:
1931 ucontrol->value.enumerated.item[0] = 6;
1932 }
1933 return 0;
1934 }
1935
1936 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1937 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1938 .name = xname, \
1939 .index = xindex, \
1940 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1941 .info = snd_hdsp_info_system_clock_mode, \
1942 .get = snd_hdsp_get_system_clock_mode \
1943 }
1944
1945 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1946 {
1947 if (hdsp->control_register & HDSP_ClockModeMaster)
1948 return 0;
1949 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1950 return 0;
1951 return 1;
1952 }
1953
1954 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1955 {
1956 static char *texts[] = {"Master", "Slave" };
1957
1958 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1959 uinfo->count = 1;
1960 uinfo->value.enumerated.items = 2;
1961 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1962 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1963 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1964 return 0;
1965 }
1966
1967 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1968 {
1969 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1970
1971 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1972 return 0;
1973 }
1974
1975 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1976 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1977 .name = xname, \
1978 .index = xindex, \
1979 .info = snd_hdsp_info_clock_source, \
1980 .get = snd_hdsp_get_clock_source, \
1981 .put = snd_hdsp_put_clock_source \
1982 }
1983
1984 static int hdsp_clock_source(struct hdsp *hdsp)
1985 {
1986 if (hdsp->control_register & HDSP_ClockModeMaster) {
1987 switch (hdsp->system_sample_rate) {
1988 case 32000:
1989 return 1;
1990 case 44100:
1991 return 2;
1992 case 48000:
1993 return 3;
1994 case 64000:
1995 return 4;
1996 case 88200:
1997 return 5;
1998 case 96000:
1999 return 6;
2000 case 128000:
2001 return 7;
2002 case 176400:
2003 return 8;
2004 case 192000:
2005 return 9;
2006 default:
2007 return 3;
2008 }
2009 } else {
2010 return 0;
2011 }
2012 }
2013
2014 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
2015 {
2016 int rate;
2017 switch (mode) {
2018 case HDSP_CLOCK_SOURCE_AUTOSYNC:
2019 if (hdsp_external_sample_rate(hdsp) != 0) {
2020 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
2021 hdsp->control_register &= ~HDSP_ClockModeMaster;
2022 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2023 return 0;
2024 }
2025 }
2026 return -1;
2027 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2028 rate = 32000;
2029 break;
2030 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2031 rate = 44100;
2032 break;
2033 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2034 rate = 48000;
2035 break;
2036 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2037 rate = 64000;
2038 break;
2039 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2040 rate = 88200;
2041 break;
2042 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2043 rate = 96000;
2044 break;
2045 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2046 rate = 128000;
2047 break;
2048 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2049 rate = 176400;
2050 break;
2051 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2052 rate = 192000;
2053 break;
2054 default:
2055 rate = 48000;
2056 }
2057 hdsp->control_register |= HDSP_ClockModeMaster;
2058 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2059 hdsp_set_rate(hdsp, rate, 1);
2060 return 0;
2061 }
2062
2063 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2064 {
2065 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2066 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2067
2068 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2069 uinfo->count = 1;
2070 if (hdsp->io_type == H9632)
2071 uinfo->value.enumerated.items = 10;
2072 else
2073 uinfo->value.enumerated.items = 7;
2074 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2075 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2076 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2077 return 0;
2078 }
2079
2080 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2081 {
2082 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2083
2084 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2085 return 0;
2086 }
2087
2088 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2089 {
2090 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2091 int change;
2092 int val;
2093
2094 if (!snd_hdsp_use_is_exclusive(hdsp))
2095 return -EBUSY;
2096 val = ucontrol->value.enumerated.item[0];
2097 if (val < 0) val = 0;
2098 if (hdsp->io_type == H9632) {
2099 if (val > 9)
2100 val = 9;
2101 } else {
2102 if (val > 6)
2103 val = 6;
2104 }
2105 spin_lock_irq(&hdsp->lock);
2106 if (val != hdsp_clock_source(hdsp))
2107 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2108 else
2109 change = 0;
2110 spin_unlock_irq(&hdsp->lock);
2111 return change;
2112 }
2113
2114 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2115
2116 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2117 {
2118 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2119
2120 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2121 return 0;
2122 }
2123
2124 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2125 {
2126 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2127 int change;
2128
2129 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2130 if (change)
2131 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2132 return change;
2133 }
2134
2135 #define HDSP_DA_GAIN(xname, xindex) \
2136 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2137 .name = xname, \
2138 .index = xindex, \
2139 .info = snd_hdsp_info_da_gain, \
2140 .get = snd_hdsp_get_da_gain, \
2141 .put = snd_hdsp_put_da_gain \
2142 }
2143
2144 static int hdsp_da_gain(struct hdsp *hdsp)
2145 {
2146 switch (hdsp->control_register & HDSP_DAGainMask) {
2147 case HDSP_DAGainHighGain:
2148 return 0;
2149 case HDSP_DAGainPlus4dBu:
2150 return 1;
2151 case HDSP_DAGainMinus10dBV:
2152 return 2;
2153 default:
2154 return 1;
2155 }
2156 }
2157
2158 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2159 {
2160 hdsp->control_register &= ~HDSP_DAGainMask;
2161 switch (mode) {
2162 case 0:
2163 hdsp->control_register |= HDSP_DAGainHighGain;
2164 break;
2165 case 1:
2166 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2167 break;
2168 case 2:
2169 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2170 break;
2171 default:
2172 return -1;
2173
2174 }
2175 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2176 return 0;
2177 }
2178
2179 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2180 {
2181 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2182
2183 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2184 uinfo->count = 1;
2185 uinfo->value.enumerated.items = 3;
2186 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2187 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2188 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2189 return 0;
2190 }
2191
2192 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2193 {
2194 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2195
2196 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2197 return 0;
2198 }
2199
2200 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2201 {
2202 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2203 int change;
2204 int val;
2205
2206 if (!snd_hdsp_use_is_exclusive(hdsp))
2207 return -EBUSY;
2208 val = ucontrol->value.enumerated.item[0];
2209 if (val < 0) val = 0;
2210 if (val > 2) val = 2;
2211 spin_lock_irq(&hdsp->lock);
2212 if (val != hdsp_da_gain(hdsp))
2213 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2214 else
2215 change = 0;
2216 spin_unlock_irq(&hdsp->lock);
2217 return change;
2218 }
2219
2220 #define HDSP_AD_GAIN(xname, xindex) \
2221 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2222 .name = xname, \
2223 .index = xindex, \
2224 .info = snd_hdsp_info_ad_gain, \
2225 .get = snd_hdsp_get_ad_gain, \
2226 .put = snd_hdsp_put_ad_gain \
2227 }
2228
2229 static int hdsp_ad_gain(struct hdsp *hdsp)
2230 {
2231 switch (hdsp->control_register & HDSP_ADGainMask) {
2232 case HDSP_ADGainMinus10dBV:
2233 return 0;
2234 case HDSP_ADGainPlus4dBu:
2235 return 1;
2236 case HDSP_ADGainLowGain:
2237 return 2;
2238 default:
2239 return 1;
2240 }
2241 }
2242
2243 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2244 {
2245 hdsp->control_register &= ~HDSP_ADGainMask;
2246 switch (mode) {
2247 case 0:
2248 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2249 break;
2250 case 1:
2251 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2252 break;
2253 case 2:
2254 hdsp->control_register |= HDSP_ADGainLowGain;
2255 break;
2256 default:
2257 return -1;
2258
2259 }
2260 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2261 return 0;
2262 }
2263
2264 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2265 {
2266 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2267
2268 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2269 uinfo->count = 1;
2270 uinfo->value.enumerated.items = 3;
2271 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2272 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2273 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2274 return 0;
2275 }
2276
2277 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2278 {
2279 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2280
2281 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2282 return 0;
2283 }
2284
2285 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2286 {
2287 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2288 int change;
2289 int val;
2290
2291 if (!snd_hdsp_use_is_exclusive(hdsp))
2292 return -EBUSY;
2293 val = ucontrol->value.enumerated.item[0];
2294 if (val < 0) val = 0;
2295 if (val > 2) val = 2;
2296 spin_lock_irq(&hdsp->lock);
2297 if (val != hdsp_ad_gain(hdsp))
2298 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2299 else
2300 change = 0;
2301 spin_unlock_irq(&hdsp->lock);
2302 return change;
2303 }
2304
2305 #define HDSP_PHONE_GAIN(xname, xindex) \
2306 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2307 .name = xname, \
2308 .index = xindex, \
2309 .info = snd_hdsp_info_phone_gain, \
2310 .get = snd_hdsp_get_phone_gain, \
2311 .put = snd_hdsp_put_phone_gain \
2312 }
2313
2314 static int hdsp_phone_gain(struct hdsp *hdsp)
2315 {
2316 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2317 case HDSP_PhoneGain0dB:
2318 return 0;
2319 case HDSP_PhoneGainMinus6dB:
2320 return 1;
2321 case HDSP_PhoneGainMinus12dB:
2322 return 2;
2323 default:
2324 return 0;
2325 }
2326 }
2327
2328 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2329 {
2330 hdsp->control_register &= ~HDSP_PhoneGainMask;
2331 switch (mode) {
2332 case 0:
2333 hdsp->control_register |= HDSP_PhoneGain0dB;
2334 break;
2335 case 1:
2336 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2337 break;
2338 case 2:
2339 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2340 break;
2341 default:
2342 return -1;
2343
2344 }
2345 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2346 return 0;
2347 }
2348
2349 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2350 {
2351 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2352
2353 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2354 uinfo->count = 1;
2355 uinfo->value.enumerated.items = 3;
2356 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2357 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2358 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2359 return 0;
2360 }
2361
2362 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2363 {
2364 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2365
2366 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2367 return 0;
2368 }
2369
2370 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2371 {
2372 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2373 int change;
2374 int val;
2375
2376 if (!snd_hdsp_use_is_exclusive(hdsp))
2377 return -EBUSY;
2378 val = ucontrol->value.enumerated.item[0];
2379 if (val < 0) val = 0;
2380 if (val > 2) val = 2;
2381 spin_lock_irq(&hdsp->lock);
2382 if (val != hdsp_phone_gain(hdsp))
2383 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2384 else
2385 change = 0;
2386 spin_unlock_irq(&hdsp->lock);
2387 return change;
2388 }
2389
2390 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \
2391 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2392 .name = xname, \
2393 .index = xindex, \
2394 .info = snd_hdsp_info_xlr_breakout_cable, \
2395 .get = snd_hdsp_get_xlr_breakout_cable, \
2396 .put = snd_hdsp_put_xlr_breakout_cable \
2397 }
2398
2399 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp)
2400 {
2401 if (hdsp->control_register & HDSP_XLRBreakoutCable)
2402 return 1;
2403 return 0;
2404 }
2405
2406 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode)
2407 {
2408 if (mode)
2409 hdsp->control_register |= HDSP_XLRBreakoutCable;
2410 else
2411 hdsp->control_register &= ~HDSP_XLRBreakoutCable;
2412 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2413 return 0;
2414 }
2415
2416 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info
2417
2418 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2419 {
2420 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2421
2422 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp);
2423 return 0;
2424 }
2425
2426 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2427 {
2428 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2429 int change;
2430 int val;
2431
2432 if (!snd_hdsp_use_is_exclusive(hdsp))
2433 return -EBUSY;
2434 val = ucontrol->value.integer.value[0] & 1;
2435 spin_lock_irq(&hdsp->lock);
2436 change = (int)val != hdsp_xlr_breakout_cable(hdsp);
2437 hdsp_set_xlr_breakout_cable(hdsp, val);
2438 spin_unlock_irq(&hdsp->lock);
2439 return change;
2440 }
2441
2442 /* (De)activates old RME Analog Extension Board
2443 These are connected to the internal ADAT connector
2444 Switching this on desactivates external ADAT
2445 */
2446 #define HDSP_AEB(xname, xindex) \
2447 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2448 .name = xname, \
2449 .index = xindex, \
2450 .info = snd_hdsp_info_aeb, \
2451 .get = snd_hdsp_get_aeb, \
2452 .put = snd_hdsp_put_aeb \
2453 }
2454
2455 static int hdsp_aeb(struct hdsp *hdsp)
2456 {
2457 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
2458 return 1;
2459 return 0;
2460 }
2461
2462 static int hdsp_set_aeb(struct hdsp *hdsp, int mode)
2463 {
2464 if (mode)
2465 hdsp->control_register |= HDSP_AnalogExtensionBoard;
2466 else
2467 hdsp->control_register &= ~HDSP_AnalogExtensionBoard;
2468 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2469 return 0;
2470 }
2471
2472 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info
2473
2474 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2475 {
2476 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2477
2478 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp);
2479 return 0;
2480 }
2481
2482 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2483 {
2484 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2485 int change;
2486 int val;
2487
2488 if (!snd_hdsp_use_is_exclusive(hdsp))
2489 return -EBUSY;
2490 val = ucontrol->value.integer.value[0] & 1;
2491 spin_lock_irq(&hdsp->lock);
2492 change = (int)val != hdsp_aeb(hdsp);
2493 hdsp_set_aeb(hdsp, val);
2494 spin_unlock_irq(&hdsp->lock);
2495 return change;
2496 }
2497
2498 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2499 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2500 .name = xname, \
2501 .index = xindex, \
2502 .info = snd_hdsp_info_pref_sync_ref, \
2503 .get = snd_hdsp_get_pref_sync_ref, \
2504 .put = snd_hdsp_put_pref_sync_ref \
2505 }
2506
2507 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2508 {
2509 /* Notice that this looks at the requested sync source,
2510 not the one actually in use.
2511 */
2512
2513 switch (hdsp->control_register & HDSP_SyncRefMask) {
2514 case HDSP_SyncRef_ADAT1:
2515 return HDSP_SYNC_FROM_ADAT1;
2516 case HDSP_SyncRef_ADAT2:
2517 return HDSP_SYNC_FROM_ADAT2;
2518 case HDSP_SyncRef_ADAT3:
2519 return HDSP_SYNC_FROM_ADAT3;
2520 case HDSP_SyncRef_SPDIF:
2521 return HDSP_SYNC_FROM_SPDIF;
2522 case HDSP_SyncRef_WORD:
2523 return HDSP_SYNC_FROM_WORD;
2524 case HDSP_SyncRef_ADAT_SYNC:
2525 return HDSP_SYNC_FROM_ADAT_SYNC;
2526 default:
2527 return HDSP_SYNC_FROM_WORD;
2528 }
2529 return 0;
2530 }
2531
2532 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2533 {
2534 hdsp->control_register &= ~HDSP_SyncRefMask;
2535 switch (pref) {
2536 case HDSP_SYNC_FROM_ADAT1:
2537 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2538 break;
2539 case HDSP_SYNC_FROM_ADAT2:
2540 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2541 break;
2542 case HDSP_SYNC_FROM_ADAT3:
2543 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2544 break;
2545 case HDSP_SYNC_FROM_SPDIF:
2546 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2547 break;
2548 case HDSP_SYNC_FROM_WORD:
2549 hdsp->control_register |= HDSP_SyncRef_WORD;
2550 break;
2551 case HDSP_SYNC_FROM_ADAT_SYNC:
2552 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2553 break;
2554 default:
2555 return -1;
2556 }
2557 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2558 return 0;
2559 }
2560
2561 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2562 {
2563 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2564 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2565
2566 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2567 uinfo->count = 1;
2568
2569 switch (hdsp->io_type) {
2570 case Digiface:
2571 case H9652:
2572 uinfo->value.enumerated.items = 6;
2573 break;
2574 case Multiface:
2575 uinfo->value.enumerated.items = 4;
2576 break;
2577 case H9632:
2578 uinfo->value.enumerated.items = 3;
2579 break;
2580 default:
2581 uinfo->value.enumerated.items = 0;
2582 break;
2583 }
2584
2585 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2586 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2587 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2588 return 0;
2589 }
2590
2591 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2592 {
2593 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2594
2595 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2596 return 0;
2597 }
2598
2599 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2600 {
2601 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2602 int change, max;
2603 unsigned int val;
2604
2605 if (!snd_hdsp_use_is_exclusive(hdsp))
2606 return -EBUSY;
2607
2608 switch (hdsp->io_type) {
2609 case Digiface:
2610 case H9652:
2611 max = 6;
2612 break;
2613 case Multiface:
2614 max = 4;
2615 break;
2616 case H9632:
2617 max = 3;
2618 break;
2619 default:
2620 return -EIO;
2621 }
2622
2623 val = ucontrol->value.enumerated.item[0] % max;
2624 spin_lock_irq(&hdsp->lock);
2625 change = (int)val != hdsp_pref_sync_ref(hdsp);
2626 hdsp_set_pref_sync_ref(hdsp, val);
2627 spin_unlock_irq(&hdsp->lock);
2628 return change;
2629 }
2630
2631 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2632 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2633 .name = xname, \
2634 .index = xindex, \
2635 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2636 .info = snd_hdsp_info_autosync_ref, \
2637 .get = snd_hdsp_get_autosync_ref, \
2638 }
2639
2640 static int hdsp_autosync_ref(struct hdsp *hdsp)
2641 {
2642 /* This looks at the autosync selected sync reference */
2643 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2644
2645 switch (status2 & HDSP_SelSyncRefMask) {
2646 case HDSP_SelSyncRef_WORD:
2647 return HDSP_AUTOSYNC_FROM_WORD;
2648 case HDSP_SelSyncRef_ADAT_SYNC:
2649 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2650 case HDSP_SelSyncRef_SPDIF:
2651 return HDSP_AUTOSYNC_FROM_SPDIF;
2652 case HDSP_SelSyncRefMask:
2653 return HDSP_AUTOSYNC_FROM_NONE;
2654 case HDSP_SelSyncRef_ADAT1:
2655 return HDSP_AUTOSYNC_FROM_ADAT1;
2656 case HDSP_SelSyncRef_ADAT2:
2657 return HDSP_AUTOSYNC_FROM_ADAT2;
2658 case HDSP_SelSyncRef_ADAT3:
2659 return HDSP_AUTOSYNC_FROM_ADAT3;
2660 default:
2661 return HDSP_AUTOSYNC_FROM_WORD;
2662 }
2663 return 0;
2664 }
2665
2666 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2667 {
2668 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2669
2670 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2671 uinfo->count = 1;
2672 uinfo->value.enumerated.items = 7;
2673 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2674 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2675 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2676 return 0;
2677 }
2678
2679 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2680 {
2681 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2682
2683 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2684 return 0;
2685 }
2686
2687 #define HDSP_LINE_OUT(xname, xindex) \
2688 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2689 .name = xname, \
2690 .index = xindex, \
2691 .info = snd_hdsp_info_line_out, \
2692 .get = snd_hdsp_get_line_out, \
2693 .put = snd_hdsp_put_line_out \
2694 }
2695
2696 static int hdsp_line_out(struct hdsp *hdsp)
2697 {
2698 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0;
2699 }
2700
2701 static int hdsp_set_line_output(struct hdsp *hdsp, int out)
2702 {
2703 if (out)
2704 hdsp->control_register |= HDSP_LineOut;
2705 else
2706 hdsp->control_register &= ~HDSP_LineOut;
2707 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2708 return 0;
2709 }
2710
2711 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info
2712
2713 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2714 {
2715 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2716
2717 spin_lock_irq(&hdsp->lock);
2718 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp);
2719 spin_unlock_irq(&hdsp->lock);
2720 return 0;
2721 }
2722
2723 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2724 {
2725 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2726 int change;
2727 unsigned int val;
2728
2729 if (!snd_hdsp_use_is_exclusive(hdsp))
2730 return -EBUSY;
2731 val = ucontrol->value.integer.value[0] & 1;
2732 spin_lock_irq(&hdsp->lock);
2733 change = (int)val != hdsp_line_out(hdsp);
2734 hdsp_set_line_output(hdsp, val);
2735 spin_unlock_irq(&hdsp->lock);
2736 return change;
2737 }
2738
2739 #define HDSP_PRECISE_POINTER(xname, xindex) \
2740 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2741 .name = xname, \
2742 .index = xindex, \
2743 .info = snd_hdsp_info_precise_pointer, \
2744 .get = snd_hdsp_get_precise_pointer, \
2745 .put = snd_hdsp_put_precise_pointer \
2746 }
2747
2748 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2749 {
2750 if (precise)
2751 hdsp->precise_ptr = 1;
2752 else
2753 hdsp->precise_ptr = 0;
2754 return 0;
2755 }
2756
2757 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2758
2759 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2760 {
2761 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2762
2763 spin_lock_irq(&hdsp->lock);
2764 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2765 spin_unlock_irq(&hdsp->lock);
2766 return 0;
2767 }
2768
2769 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2770 {
2771 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2772 int change;
2773 unsigned int val;
2774
2775 if (!snd_hdsp_use_is_exclusive(hdsp))
2776 return -EBUSY;
2777 val = ucontrol->value.integer.value[0] & 1;
2778 spin_lock_irq(&hdsp->lock);
2779 change = (int)val != hdsp->precise_ptr;
2780 hdsp_set_precise_pointer(hdsp, val);
2781 spin_unlock_irq(&hdsp->lock);
2782 return change;
2783 }
2784
2785 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2786 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2787 .name = xname, \
2788 .index = xindex, \
2789 .info = snd_hdsp_info_use_midi_tasklet, \
2790 .get = snd_hdsp_get_use_midi_tasklet, \
2791 .put = snd_hdsp_put_use_midi_tasklet \
2792 }
2793
2794 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2795 {
2796 if (use_tasklet)
2797 hdsp->use_midi_tasklet = 1;
2798 else
2799 hdsp->use_midi_tasklet = 0;
2800 return 0;
2801 }
2802
2803 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2804
2805 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2806 {
2807 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2808
2809 spin_lock_irq(&hdsp->lock);
2810 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2811 spin_unlock_irq(&hdsp->lock);
2812 return 0;
2813 }
2814
2815 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2816 {
2817 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2818 int change;
2819 unsigned int val;
2820
2821 if (!snd_hdsp_use_is_exclusive(hdsp))
2822 return -EBUSY;
2823 val = ucontrol->value.integer.value[0] & 1;
2824 spin_lock_irq(&hdsp->lock);
2825 change = (int)val != hdsp->use_midi_tasklet;
2826 hdsp_set_use_midi_tasklet(hdsp, val);
2827 spin_unlock_irq(&hdsp->lock);
2828 return change;
2829 }
2830
2831 #define HDSP_MIXER(xname, xindex) \
2832 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2833 .name = xname, \
2834 .index = xindex, \
2835 .device = 0, \
2836 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2837 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2838 .info = snd_hdsp_info_mixer, \
2839 .get = snd_hdsp_get_mixer, \
2840 .put = snd_hdsp_put_mixer \
2841 }
2842
2843 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2844 {
2845 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2846 uinfo->count = 3;
2847 uinfo->value.integer.min = 0;
2848 uinfo->value.integer.max = 65536;
2849 uinfo->value.integer.step = 1;
2850 return 0;
2851 }
2852
2853 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2854 {
2855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2856 int source;
2857 int destination;
2858 int addr;
2859
2860 source = ucontrol->value.integer.value[0];
2861 destination = ucontrol->value.integer.value[1];
2862
2863 if (source >= hdsp->max_channels)
2864 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2865 else
2866 addr = hdsp_input_to_output_key(hdsp,source, destination);
2867
2868 spin_lock_irq(&hdsp->lock);
2869 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2870 spin_unlock_irq(&hdsp->lock);
2871 return 0;
2872 }
2873
2874 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2875 {
2876 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2877 int change;
2878 int source;
2879 int destination;
2880 int gain;
2881 int addr;
2882
2883 if (!snd_hdsp_use_is_exclusive(hdsp))
2884 return -EBUSY;
2885
2886 source = ucontrol->value.integer.value[0];
2887 destination = ucontrol->value.integer.value[1];
2888
2889 if (source >= hdsp->max_channels)
2890 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2891 else
2892 addr = hdsp_input_to_output_key(hdsp,source, destination);
2893
2894 gain = ucontrol->value.integer.value[2];
2895
2896 spin_lock_irq(&hdsp->lock);
2897 change = gain != hdsp_read_gain(hdsp, addr);
2898 if (change)
2899 hdsp_write_gain(hdsp, addr, gain);
2900 spin_unlock_irq(&hdsp->lock);
2901 return change;
2902 }
2903
2904 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2905 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2906 .name = xname, \
2907 .index = xindex, \
2908 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2909 .info = snd_hdsp_info_sync_check, \
2910 .get = snd_hdsp_get_wc_sync_check \
2911 }
2912
2913 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2914 {
2915 static char *texts[] = {"No Lock", "Lock", "Sync" };
2916 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2917 uinfo->count = 1;
2918 uinfo->value.enumerated.items = 3;
2919 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2920 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2921 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2922 return 0;
2923 }
2924
2925 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2926 {
2927 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2928 if (status2 & HDSP_wc_lock) {
2929 if (status2 & HDSP_wc_sync)
2930 return 2;
2931 else
2932 return 1;
2933 } else
2934 return 0;
2935 return 0;
2936 }
2937
2938 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2939 {
2940 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2941
2942 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2943 return 0;
2944 }
2945
2946 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2947 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2948 .name = xname, \
2949 .index = xindex, \
2950 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2951 .info = snd_hdsp_info_sync_check, \
2952 .get = snd_hdsp_get_spdif_sync_check \
2953 }
2954
2955 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2956 {
2957 int status = hdsp_read(hdsp, HDSP_statusRegister);
2958 if (status & HDSP_SPDIFErrorFlag)
2959 return 0;
2960 else {
2961 if (status & HDSP_SPDIFSync)
2962 return 2;
2963 else
2964 return 1;
2965 }
2966 return 0;
2967 }
2968
2969 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2970 {
2971 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2972
2973 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2974 return 0;
2975 }
2976
2977 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2978 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2979 .name = xname, \
2980 .index = xindex, \
2981 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2982 .info = snd_hdsp_info_sync_check, \
2983 .get = snd_hdsp_get_adatsync_sync_check \
2984 }
2985
2986 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2987 {
2988 int status = hdsp_read(hdsp, HDSP_statusRegister);
2989 if (status & HDSP_TimecodeLock) {
2990 if (status & HDSP_TimecodeSync)
2991 return 2;
2992 else
2993 return 1;
2994 } else
2995 return 0;
2996 }
2997
2998 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2999 {
3000 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3001
3002 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
3003 return 0;
3004 }
3005
3006 #define HDSP_ADAT_SYNC_CHECK \
3007 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3008 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3009 .info = snd_hdsp_info_sync_check, \
3010 .get = snd_hdsp_get_adat_sync_check \
3011 }
3012
3013 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
3014 {
3015 int status = hdsp_read(hdsp, HDSP_statusRegister);
3016
3017 if (status & (HDSP_Lock0>>idx)) {
3018 if (status & (HDSP_Sync0>>idx))
3019 return 2;
3020 else
3021 return 1;
3022 } else
3023 return 0;
3024 }
3025
3026 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3027 {
3028 int offset;
3029 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3030
3031 offset = ucontrol->id.index - 1;
3032 snd_assert(offset >= 0);
3033
3034 switch (hdsp->io_type) {
3035 case Digiface:
3036 case H9652:
3037 if (offset >= 3)
3038 return -EINVAL;
3039 break;
3040 case Multiface:
3041 case H9632:
3042 if (offset >= 1)
3043 return -EINVAL;
3044 break;
3045 default:
3046 return -EIO;
3047 }
3048
3049 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
3050 return 0;
3051 }
3052
3053 #define HDSP_DDS_OFFSET(xname, xindex) \
3054 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3055 .name = xname, \
3056 .index = xindex, \
3057 .info = snd_hdsp_info_dds_offset, \
3058 .get = snd_hdsp_get_dds_offset, \
3059 .put = snd_hdsp_put_dds_offset \
3060 }
3061
3062 static int hdsp_dds_offset(struct hdsp *hdsp)
3063 {
3064 u64 n;
3065 u32 r;
3066 unsigned int dds_value = hdsp->dds_value;
3067 int system_sample_rate = hdsp->system_sample_rate;
3068
3069 if (!dds_value)
3070 return 0;
3071
3072 n = DDS_NUMERATOR;
3073 /*
3074 * dds_value = n / rate
3075 * rate = n / dds_value
3076 */
3077 div64_32(&n, dds_value, &r);
3078 if (system_sample_rate >= 112000)
3079 n *= 4;
3080 else if (system_sample_rate >= 56000)
3081 n *= 2;
3082 return ((int)n) - system_sample_rate;
3083 }
3084
3085 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
3086 {
3087 int rate = hdsp->system_sample_rate + offset_hz;
3088 hdsp_set_dds_value(hdsp, rate);
3089 return 0;
3090 }
3091
3092 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3093 {
3094 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3095 uinfo->count = 1;
3096 uinfo->value.integer.min = -5000;
3097 uinfo->value.integer.max = 5000;
3098 return 0;
3099 }
3100
3101 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3102 {
3103 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3104
3105 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
3106 return 0;
3107 }
3108
3109 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3110 {
3111 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3112 int change;
3113 int val;
3114
3115 if (!snd_hdsp_use_is_exclusive(hdsp))
3116 return -EBUSY;
3117 val = ucontrol->value.enumerated.item[0];
3118 spin_lock_irq(&hdsp->lock);
3119 if (val != hdsp_dds_offset(hdsp))
3120 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
3121 else
3122 change = 0;
3123 spin_unlock_irq(&hdsp->lock);
3124 return change;
3125 }
3126
3127 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
3128 HDSP_DA_GAIN("DA Gain", 0),
3129 HDSP_AD_GAIN("AD Gain", 0),
3130 HDSP_PHONE_GAIN("Phones Gain", 0),
3131 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0),
3132 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
3133 };
3134
3135 static struct snd_kcontrol_new snd_hdsp_controls[] = {
3136 {
3137 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3138 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
3139 .info = snd_hdsp_control_spdif_info,
3140 .get = snd_hdsp_control_spdif_get,
3141 .put = snd_hdsp_control_spdif_put,
3142 },
3143 {
3144 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
3145 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3146 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
3147 .info = snd_hdsp_control_spdif_stream_info,
3148 .get = snd_hdsp_control_spdif_stream_get,
3149 .put = snd_hdsp_control_spdif_stream_put,
3150 },
3151 {
3152 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3153 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3154 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
3155 .info = snd_hdsp_control_spdif_mask_info,
3156 .get = snd_hdsp_control_spdif_mask_get,
3157 .private_value = IEC958_AES0_NONAUDIO |
3158 IEC958_AES0_PROFESSIONAL |
3159 IEC958_AES0_CON_EMPHASIS,
3160 },
3161 {
3162 .access = SNDRV_CTL_ELEM_ACCESS_READ,
3163 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
3164 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
3165 .info = snd_hdsp_control_spdif_mask_info,
3166 .get = snd_hdsp_control_spdif_mask_get,
3167 .private_value = IEC958_AES0_NONAUDIO |
3168 IEC958_AES0_PROFESSIONAL |
3169 IEC958_AES0_PRO_EMPHASIS,
3170 },
3171 HDSP_MIXER("Mixer", 0),
3172 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
3173 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0),
3174 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0),
3175 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0),
3176 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0),
3177 /* 'Sample Clock Source' complies with the alsa control naming scheme */
3178 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
3179 {
3180 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3181 .name = "Sample Clock Source Locking",
3182 .info = snd_hdsp_info_clock_source_lock,
3183 .get = snd_hdsp_get_clock_source_lock,
3184 .put = snd_hdsp_put_clock_source_lock,
3185 },
3186 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3187 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3188 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3189 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3190 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3191 /* 'External Rate' complies with the alsa control naming scheme */
3192 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3193 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3194 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3195 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3196 HDSP_LINE_OUT("Line Out", 0),
3197 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3198 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3199 };
3200
3201 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0);
3202 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3203
3204 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3205 {
3206 unsigned int idx;
3207 int err;
3208 struct snd_kcontrol *kctl;
3209
3210 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3211 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3212 return err;
3213 if (idx == 1) /* IEC958 (S/PDIF) Stream */
3214 hdsp->spdif_ctl = kctl;
3215 }
3216
3217 /* ADAT SyncCheck status */
3218 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3219 snd_hdsp_adat_sync_check.index = 1;
3220 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3221 return err;
3222 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3223 for (idx = 1; idx < 3; ++idx) {
3224 snd_hdsp_adat_sync_check.index = idx+1;
3225 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3226 return err;
3227 }
3228 }
3229
3230 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3231 if (hdsp->io_type == H9632) {
3232 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3233 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3234 return err;
3235 }
3236 }
3237
3238 /* AEB control for H96xx card */
3239 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3240 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3241 return err;
3242 }
3243
3244 return 0;
3245 }
3246
3247 /*------------------------------------------------------------
3248 /proc interface
3249 ------------------------------------------------------------*/
3250
3251 static void
3252 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3253 {
3254 struct hdsp *hdsp = (struct hdsp *) entry->private_data;
3255 unsigned int status;
3256 unsigned int status2;
3257 char *pref_sync_ref;
3258 char *autosync_ref;
3259 char *system_clock_mode;
3260 char *clock_source;
3261 int x;
3262
3263 if (hdsp_check_for_iobox (hdsp)) {
3264 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n");
3265 return;
3266 }
3267
3268 if (hdsp_check_for_firmware(hdsp, 0)) {
3269 if (hdsp->state & HDSP_FirmwareCached) {
3270 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3271 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n");
3272 return;
3273 }
3274 } else {
3275 int err = -EINVAL;
3276 #ifdef HDSP_FW_LOADER
3277 err = hdsp_request_fw_loader(hdsp);
3278 #endif
3279 if (err < 0) {
3280 snd_iprintf(buffer,
3281 "No firmware loaded nor cached, "
3282 "please upload firmware.\n");
3283 return;
3284 }
3285 }
3286 }
3287
3288 status = hdsp_read(hdsp, HDSP_statusRegister);
3289 status2 = hdsp_read(hdsp, HDSP_status2Register);
3290
3291 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1);
3292 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3293 hdsp->capture_buffer, hdsp->playback_buffer);
3294 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3295 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3296 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3297 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register);
3298 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3299 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3300 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3301 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3302 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3303 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3304 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3305 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3306
3307 snd_iprintf(buffer, "\n");
3308
3309 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3310
3311 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3312 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3313 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3314 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3315
3316 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3317
3318 snd_iprintf(buffer, "\n");
3319
3320
3321 switch (hdsp_clock_source(hdsp)) {
3322 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3323 clock_source = "AutoSync";
3324 break;
3325 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3326 clock_source = "Internal 32 kHz";
3327 break;
3328 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3329 clock_source = "Internal 44.1 kHz";
3330 break;
3331 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3332 clock_source = "Internal 48 kHz";
3333 break;
3334 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3335 clock_source = "Internal 64 kHz";
3336 break;
3337 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3338 clock_source = "Internal 88.2 kHz";
3339 break;
3340 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3341 clock_source = "Internal 96 kHz";
3342 break;
3343 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3344 clock_source = "Internal 128 kHz";
3345 break;
3346 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3347 clock_source = "Internal 176.4 kHz";
3348 break;
3349 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3350 clock_source = "Internal 192 kHz";
3351 break;
3352 default:
3353 clock_source = "Error";
3354 }
3355 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3356
3357 if (hdsp_system_clock_mode(hdsp))
3358 system_clock_mode = "Slave";
3359 else
3360 system_clock_mode = "Master";
3361
3362 switch (hdsp_pref_sync_ref (hdsp)) {
3363 case HDSP_SYNC_FROM_WORD:
3364 pref_sync_ref = "Word Clock";
3365 break;
3366 case HDSP_SYNC_FROM_ADAT_SYNC:
3367 pref_sync_ref = "ADAT Sync";
3368 break;
3369 case HDSP_SYNC_FROM_SPDIF:
3370 pref_sync_ref = "SPDIF";
3371 break;
3372 case HDSP_SYNC_FROM_ADAT1:
3373 pref_sync_ref = "ADAT1";
3374 break;
3375 case HDSP_SYNC_FROM_ADAT2:
3376 pref_sync_ref = "ADAT2";
3377 break;
3378 case HDSP_SYNC_FROM_ADAT3:
3379 pref_sync_ref = "ADAT3";
3380 break;
3381 default:
3382 pref_sync_ref = "Word Clock";
3383 break;
3384 }
3385 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3386
3387 switch (hdsp_autosync_ref (hdsp)) {
3388 case HDSP_AUTOSYNC_FROM_WORD:
3389 autosync_ref = "Word Clock";
3390 break;
3391 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3392 autosync_ref = "ADAT Sync";
3393 break;
3394 case HDSP_AUTOSYNC_FROM_SPDIF:
3395 autosync_ref = "SPDIF";
3396 break;
3397 case HDSP_AUTOSYNC_FROM_NONE:
3398 autosync_ref = "None";
3399 break;
3400 case HDSP_AUTOSYNC_FROM_ADAT1:
3401 autosync_ref = "ADAT1";
3402 break;
3403 case HDSP_AUTOSYNC_FROM_ADAT2:
3404 autosync_ref = "ADAT2";
3405 break;
3406 case HDSP_AUTOSYNC_FROM_ADAT3:
3407 autosync_ref = "ADAT3";
3408 break;
3409 default:
3410 autosync_ref = "---";
3411 break;
3412 }
3413 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3414
3415 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3416
3417 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3418
3419 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3420 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3421
3422 snd_iprintf(buffer, "\n");
3423
3424 switch (hdsp_spdif_in(hdsp)) {
3425 case HDSP_SPDIFIN_OPTICAL:
3426 snd_iprintf(buffer, "IEC958 input: Optical\n");
3427 break;
3428 case HDSP_SPDIFIN_COAXIAL:
3429 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3430 break;
3431 case HDSP_SPDIFIN_INTERNAL:
3432 snd_iprintf(buffer, "IEC958 input: Internal\n");
3433 break;
3434 case HDSP_SPDIFIN_AES:
3435 snd_iprintf(buffer, "IEC958 input: AES\n");
3436 break;
3437 default:
3438 snd_iprintf(buffer, "IEC958 input: ???\n");
3439 break;
3440 }
3441
3442 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3443 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3444 else
3445 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3446
3447 if (hdsp->control_register & HDSP_SPDIFProfessional)
3448 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3449 else
3450 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3451
3452 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3453 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3454 else
3455 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3456
3457 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3458 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3459 else
3460 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3461 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0)
3462 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x);
3463 else
3464 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n");
3465
3466 snd_iprintf(buffer, "\n");
3467
3468 /* Sync Check */
3469 x = status & HDSP_Sync0;
3470 if (status & HDSP_Lock0)
3471 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3472 else
3473 snd_iprintf(buffer, "ADAT1: No Lock\n");
3474
3475 switch (hdsp->io_type) {
3476 case Digiface:
3477 case H9652:
3478 x = status & HDSP_Sync1;
3479 if (status & HDSP_Lock1)
3480 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3481 else
3482 snd_iprintf(buffer, "ADAT2: No Lock\n");
3483 x = status & HDSP_Sync2;
3484 if (status & HDSP_Lock2)
3485 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3486 else
3487 snd_iprintf(buffer, "ADAT3: No Lock\n");
3488 break;
3489 default:
3490 /* relax */
3491 break;
3492 }
3493
3494 x = status & HDSP_SPDIFSync;
3495 if (status & HDSP_SPDIFErrorFlag)
3496 snd_iprintf (buffer, "SPDIF: No Lock\n");
3497 else
3498 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3499
3500 x = status2 & HDSP_wc_sync;
3501 if (status2 & HDSP_wc_lock)
3502 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3503 else
3504 snd_iprintf (buffer, "Word Clock: No Lock\n");
3505
3506 x = status & HDSP_TimecodeSync;
3507 if (status & HDSP_TimecodeLock)
3508 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3509 else
3510 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3511
3512 snd_iprintf(buffer, "\n");
3513
3514 /* Informations about H9632 specific controls */
3515 if (hdsp->io_type == H9632) {
3516 char *tmp;
3517
3518 switch (hdsp_ad_gain(hdsp)) {
3519 case 0:
3520 tmp = "-10 dBV";
3521 break;
3522 case 1:
3523 tmp = "+4 dBu";
3524 break;
3525 default:
3526 tmp = "Lo Gain";
3527 break;
3528 }
3529 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3530
3531 switch (hdsp_da_gain(hdsp)) {
3532 case 0:
3533 tmp = "Hi Gain";
3534 break;
3535 case 1:
3536 tmp = "+4 dBu";
3537 break;
3538 default:
3539 tmp = "-10 dBV";
3540 break;
3541 }
3542 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3543
3544 switch (hdsp_phone_gain(hdsp)) {
3545 case 0:
3546 tmp = "0 dB";
3547 break;
3548 case 1:
3549 tmp = "-6 dB";
3550 break;
3551 default:
3552 tmp = "-12 dB";
3553 break;
3554 }
3555 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3556
3557 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no");
3558
3559 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3560 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3561 else
3562 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3563 snd_iprintf(buffer, "\n");
3564 }
3565
3566 }
3567
3568 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3569 {
3570 struct snd_info_entry *entry;
3571
3572 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3573 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3574 }
3575
3576 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3577 {
3578 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3579 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3580 }
3581
3582 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp)
3583 {
3584 unsigned long pb_bus, cb_bus;
3585
3586 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3587 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3588 if (hdsp->capture_dma_buf.area)
3589 snd_dma_free_pages(&hdsp->capture_dma_buf);
3590 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3591 return -ENOMEM;
3592 }
3593
3594 /* Align to bus-space 64K boundary */
3595
3596 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3597 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3598
3599 /* Tell the card where it is */
3600
3601 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3602 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3603
3604 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3605 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3606
3607 return 0;
3608 }
3609
3610 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3611 {
3612 unsigned int i;
3613
3614 /* ASSUMPTION: hdsp->lock is either held, or
3615 there is no need to hold it (e.g. during module
3616 initialization).
3617 */
3618
3619 /* set defaults:
3620
3621 SPDIF Input via Coax
3622 Master clock mode
3623 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3624 which implies 2 4096 sample, 32Kbyte periods).
3625 Enable line out.
3626 */
3627
3628 hdsp->control_register = HDSP_ClockModeMaster |
3629 HDSP_SPDIFInputCoaxial |
3630 hdsp_encode_latency(7) |
3631 HDSP_LineOut;
3632
3633
3634 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3635
3636 #ifdef SNDRV_BIG_ENDIAN
3637 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3638 #else
3639 hdsp->control2_register = 0;
3640 #endif
3641 if (hdsp->io_type == H9652)
3642 snd_hdsp_9652_enable_mixer (hdsp);
3643 else
3644 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3645
3646 hdsp_reset_hw_pointer(hdsp);
3647 hdsp_compute_period_size(hdsp);
3648
3649 /* silence everything */
3650
3651 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3652 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3653
3654 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3655 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3656 return -EIO;
3657 }
3658
3659 /* H9632 specific defaults */
3660 if (hdsp->io_type == H9632) {
3661 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3662 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3663 }
3664
3665 /* set a default rate so that the channel map is set up.
3666 */
3667
3668 hdsp_set_rate(hdsp, 48000, 1);
3669
3670 return 0;
3671 }
3672
3673 static void hdsp_midi_tasklet(unsigned long arg)
3674 {
3675 struct hdsp *hdsp = (struct hdsp *)arg;
3676
3677 if (hdsp->midi[0].pending)
3678 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3679 if (hdsp->midi[1].pending)
3680 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3681 }
3682
3683 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3684 {
3685 struct hdsp *hdsp = (struct hdsp *) dev_id;
3686 unsigned int status;
3687 int audio;
3688 int midi0;
3689 int midi1;
3690 unsigned int midi0status;
3691 unsigned int midi1status;
3692 int schedule = 0;
3693
3694 status = hdsp_read(hdsp, HDSP_statusRegister);
3695
3696 audio = status & HDSP_audioIRQPending;
3697 midi0 = status & HDSP_midi0IRQPending;
3698 midi1 = status & HDSP_midi1IRQPending;
3699
3700 if (!audio && !midi0 && !midi1)
3701 return IRQ_NONE;
3702
3703 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3704
3705 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3706 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3707
3708 if (audio) {
3709 if (hdsp->capture_substream)
3710 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3711
3712 if (hdsp->playback_substream)
3713 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3714 }
3715
3716 if (midi0 && midi0status) {
3717 if (hdsp->use_midi_tasklet) {
3718 /* we disable interrupts for this input until processing is done */
3719 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3720 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3721 hdsp->midi[0].pending = 1;
3722 schedule = 1;
3723 } else {
3724 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3725 }
3726 }
3727 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) {
3728 if (hdsp->use_midi_tasklet) {
3729 /* we disable interrupts for this input until processing is done */
3730 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3731 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3732 hdsp->midi[1].pending = 1;
3733 schedule = 1;
3734 } else {
3735 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3736 }
3737 }
3738 if (hdsp->use_midi_tasklet && schedule)
3739 tasklet_hi_schedule(&hdsp->midi_tasklet);
3740 return IRQ_HANDLED;
3741 }
3742
3743 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3744 {
3745 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3746 return hdsp_hw_pointer(hdsp);
3747 }
3748
3749 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3750 int stream,
3751 int channel)
3752
3753 {
3754 int mapped_channel;
3755
3756 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL);
3757
3758 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3759 return NULL;
3760
3761 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3762 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3763 else
3764 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3765 }
3766
3767 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3768 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3769 {
3770 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3771 char *channel_buf;
3772
3773 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3774
3775 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3776 snd_assert(channel_buf != NULL, return -EIO);
3777 if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3778 return -EFAULT;
3779 return count;
3780 }
3781
3782 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3783 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3784 {
3785 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3786 char *channel_buf;
3787
3788 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL);
3789
3790 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3791 snd_assert(channel_buf != NULL, return -EIO);
3792 if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3793 return -EFAULT;
3794 return count;
3795 }
3796
3797 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
3798 snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
3799 {
3800 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3801 char *channel_buf;
3802
3803 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3804 snd_assert(channel_buf != NULL, return -EIO);
3805 memset(channel_buf + pos * 4, 0, count * 4);
3806 return count;
3807 }
3808
3809 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3810 {
3811 struct snd_pcm_runtime *runtime = substream->runtime;
3812 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3813 struct snd_pcm_substream *other;
3814 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3815 other = hdsp->capture_substream;
3816 else
3817 other = hdsp->playback_substream;
3818 if (hdsp->running)
3819 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3820 else
3821 runtime->status->hw_ptr = 0;
3822 if (other) {
3823 struct snd_pcm_substream *s;
3824 struct snd_pcm_runtime *oruntime = other->runtime;
3825 snd_pcm_group_for_each_entry(s, substream) {
3826 if (s == other) {
3827 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3828 break;
3829 }
3830 }
3831 }
3832 return 0;
3833 }
3834
3835 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3836 struct snd_pcm_hw_params *params)
3837 {
3838 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3839 int err;
3840 pid_t this_pid;
3841 pid_t other_pid;
3842
3843 if (hdsp_check_for_iobox (hdsp))
3844 return -EIO;
3845
3846 if (hdsp_check_for_firmware(hdsp, 1))
3847 return -EIO;
3848
3849 spin_lock_irq(&hdsp->lock);
3850
3851 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
3852 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
3853 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
3854 this_pid = hdsp->playback_pid;
3855 other_pid = hdsp->capture_pid;
3856 } else {
3857 this_pid = hdsp->capture_pid;
3858 other_pid = hdsp->playback_pid;
3859 }
3860
3861 if ((other_pid > 0) && (this_pid != other_pid)) {
3862
3863 /* The other stream is open, and not by the same
3864 task as this one. Make sure that the parameters
3865 that matter are the same.
3866 */
3867
3868 if (params_rate(params) != hdsp->system_sample_rate) {
3869 spin_unlock_irq(&hdsp->lock);
3870 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3871 return -EBUSY;
3872 }
3873
3874 if (params_period_size(params) != hdsp->period_bytes / 4) {
3875 spin_unlock_irq(&hdsp->lock);
3876 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3877 return -EBUSY;
3878 }
3879
3880 /* We're fine. */
3881
3882 spin_unlock_irq(&hdsp->lock);
3883 return 0;
3884
3885 } else {
3886 spin_unlock_irq(&hdsp->lock);
3887 }
3888
3889 /* how to make sure that the rate matches an externally-set one ?
3890 */
3891
3892 spin_lock_irq(&hdsp->lock);
3893 if (! hdsp->clock_source_locked) {
3894 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
3895 spin_unlock_irq(&hdsp->lock);
3896 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
3897 return err;
3898 }
3899 }
3900 spin_unlock_irq(&hdsp->lock);
3901
3902 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
3903 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
3904 return err;
3905 }
3906
3907 return 0;
3908 }
3909
3910 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
3911 struct snd_pcm_channel_info *info)
3912 {
3913 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3914 int mapped_channel;
3915
3916 snd_assert(info->channel < hdsp->max_channels, return -EINVAL);
3917
3918 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
3919 return -EINVAL;
3920
3921 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
3922 info->first = 0;
3923 info->step = 32;
3924 return 0;
3925 }
3926
3927 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
3928 unsigned int cmd, void *arg)
3929 {
3930 switch (cmd) {
3931 case SNDRV_PCM_IOCTL1_RESET:
3932 return snd_hdsp_reset(substream);
3933 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
3934 return snd_hdsp_channel_info(substream, arg);
3935 default:
3936 break;
3937 }
3938
3939 return snd_pcm_lib_ioctl(substream, cmd, arg);
3940 }
3941
3942 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
3943 {
3944 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3945 struct snd_pcm_substream *other;
3946 int running;
3947
3948 if (hdsp_check_for_iobox (hdsp))
3949 return -EIO;
3950
3951 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
3952 return -EIO;
3953
3954 spin_lock(&hdsp->lock);
3955 running = hdsp->running;
3956 switch (cmd) {
3957 case SNDRV_PCM_TRIGGER_START:
3958 running |= 1 << substream->stream;
3959 break;
3960 case SNDRV_PCM_TRIGGER_STOP:
3961 running &= ~(1 << substream->stream);
3962 break;
3963 default:
3964 snd_BUG();
3965 spin_unlock(&hdsp->lock);
3966 return -EINVAL;
3967 }
3968 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3969 other = hdsp->capture_substream;
3970 else
3971 other = hdsp->playback_substream;
3972
3973 if (other) {
3974 struct snd_pcm_substream *s;
3975 snd_pcm_group_for_each_entry(s, substream) {
3976 if (s == other) {
3977 snd_pcm_trigger_done(s, substream);
3978 if (cmd == SNDRV_PCM_TRIGGER_START)
3979 running |= 1 << s->stream;
3980 else
3981 running &= ~(1 << s->stream);
3982 goto _ok;
3983 }
3984 }
3985 if (cmd == SNDRV_PCM_TRIGGER_START) {
3986 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
3987 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3988 hdsp_silence_playback(hdsp);
3989 } else {
3990 if (running &&
3991 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3992 hdsp_silence_playback(hdsp);
3993 }
3994 } else {
3995 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
3996 hdsp_silence_playback(hdsp);
3997 }
3998 _ok:
3999 snd_pcm_trigger_done(substream, substream);
4000 if (!hdsp->running && running)
4001 hdsp_start_audio(hdsp);
4002 else if (hdsp->running && !running)
4003 hdsp_stop_audio(hdsp);
4004 hdsp->running = running;
4005 spin_unlock(&hdsp->lock);
4006
4007 return 0;
4008 }
4009
4010 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4011 {
4012 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4013 int result = 0;
4014
4015 if (hdsp_check_for_iobox (hdsp))
4016 return -EIO;
4017
4018 if (hdsp_check_for_firmware(hdsp, 1))
4019 return -EIO;
4020
4021 spin_lock_irq(&hdsp->lock);
4022 if (!hdsp->running)
4023 hdsp_reset_hw_pointer(hdsp);
4024 spin_unlock_irq(&hdsp->lock);
4025 return result;
4026 }
4027
4028 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4029 {
4030 .info = (SNDRV_PCM_INFO_MMAP |
4031 SNDRV_PCM_INFO_MMAP_VALID |
4032 SNDRV_PCM_INFO_NONINTERLEAVED |
4033 SNDRV_PCM_INFO_SYNC_START |
4034 SNDRV_PCM_INFO_DOUBLE),
4035 #ifdef SNDRV_BIG_ENDIAN
4036 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4037 #else
4038 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4039 #endif
4040 .rates = (SNDRV_PCM_RATE_32000 |
4041 SNDRV_PCM_RATE_44100 |
4042 SNDRV_PCM_RATE_48000 |
4043 SNDRV_PCM_RATE_64000 |
4044 SNDRV_PCM_RATE_88200 |
4045 SNDRV_PCM_RATE_96000),
4046 .rate_min = 32000,
4047 .rate_max = 96000,
4048 .channels_min = 14,
4049 .channels_max = HDSP_MAX_CHANNELS,
4050 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4051 .period_bytes_min = (64 * 4) * 10,
4052 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4053 .periods_min = 2,
4054 .periods_max = 2,
4055 .fifo_size = 0
4056 };
4057
4058 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4059 {
4060 .info = (SNDRV_PCM_INFO_MMAP |
4061 SNDRV_PCM_INFO_MMAP_VALID |
4062 SNDRV_PCM_INFO_NONINTERLEAVED |
4063 SNDRV_PCM_INFO_SYNC_START),
4064 #ifdef SNDRV_BIG_ENDIAN
4065 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4066 #else
4067 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4068 #endif
4069 .rates = (SNDRV_PCM_RATE_32000 |
4070 SNDRV_PCM_RATE_44100 |
4071 SNDRV_PCM_RATE_48000 |
4072 SNDRV_PCM_RATE_64000 |
4073 SNDRV_PCM_RATE_88200 |
4074 SNDRV_PCM_RATE_96000),
4075 .rate_min = 32000,
4076 .rate_max = 96000,
4077 .channels_min = 14,
4078 .channels_max = HDSP_MAX_CHANNELS,
4079 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4080 .period_bytes_min = (64 * 4) * 10,
4081 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4082 .periods_min = 2,
4083 .periods_max = 2,
4084 .fifo_size = 0
4085 };
4086
4087 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4088
4089 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4090 .count = ARRAY_SIZE(hdsp_period_sizes),
4091 .list = hdsp_period_sizes,
4092 .mask = 0
4093 };
4094
4095 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4096
4097 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4098 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4099 .list = hdsp_9632_sample_rates,
4100 .mask = 0
4101 };
4102
4103 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4104 struct snd_pcm_hw_rule *rule)
4105 {
4106 struct hdsp *hdsp = rule->private;
4107 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4108 if (hdsp->io_type == H9632) {
4109 unsigned int list[3];
4110 list[0] = hdsp->qs_in_channels;
4111 list[1] = hdsp->ds_in_channels;
4112 list[2] = hdsp->ss_in_channels;
4113 return snd_interval_list(c, 3, list, 0);
4114 } else {
4115 unsigned int list[2];
4116 list[0] = hdsp->ds_in_channels;
4117 list[1] = hdsp->ss_in_channels;
4118 return snd_interval_list(c, 2, list, 0);
4119 }
4120 }
4121
4122 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4123 struct snd_pcm_hw_rule *rule)
4124 {
4125 unsigned int list[3];
4126 struct hdsp *hdsp = rule->private;
4127 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4128 if (hdsp->io_type == H9632) {
4129 list[0] = hdsp->qs_out_channels;
4130 list[1] = hdsp->ds_out_channels;
4131 list[2] = hdsp->ss_out_channels;
4132 return snd_interval_list(c, 3, list, 0);
4133 } else {
4134 list[0] = hdsp->ds_out_channels;
4135 list[1] = hdsp->ss_out_channels;
4136 }
4137 return snd_interval_list(c, 2, list, 0);
4138 }
4139
4140 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4141 struct snd_pcm_hw_rule *rule)
4142 {
4143 struct hdsp *hdsp = rule->private;
4144 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4145 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4146 if (r->min > 96000 && hdsp->io_type == H9632) {
4147 struct snd_interval t = {
4148 .min = hdsp->qs_in_channels,
4149 .max = hdsp->qs_in_channels,
4150 .integer = 1,
4151 };
4152 return snd_interval_refine(c, &t);
4153 } else if (r->min > 48000 && r->max <= 96000) {
4154 struct snd_interval t = {
4155 .min = hdsp->ds_in_channels,
4156 .max = hdsp->ds_in_channels,
4157 .integer = 1,
4158 };
4159 return snd_interval_refine(c, &t);
4160 } else if (r->max < 64000) {
4161 struct snd_interval t = {
4162 .min = hdsp->ss_in_channels,
4163 .max = hdsp->ss_in_channels,
4164 .integer = 1,
4165 };
4166 return snd_interval_refine(c, &t);
4167 }
4168 return 0;
4169 }
4170
4171 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4172 struct snd_pcm_hw_rule *rule)
4173 {
4174 struct hdsp *hdsp = rule->private;
4175 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4176 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4177 if (r->min > 96000 && hdsp->io_type == H9632) {
4178 struct snd_interval t = {
4179 .min = hdsp->qs_out_channels,
4180 .max = hdsp->qs_out_channels,
4181 .integer = 1,
4182 };
4183 return snd_interval_refine(c, &t);
4184 } else if (r->min > 48000 && r->max <= 96000) {
4185 struct snd_interval t = {
4186 .min = hdsp->ds_out_channels,
4187 .max = hdsp->ds_out_channels,
4188 .integer = 1,
4189 };
4190 return snd_interval_refine(c, &t);
4191 } else if (r->max < 64000) {
4192 struct snd_interval t = {
4193 .min = hdsp->ss_out_channels,
4194 .max = hdsp->ss_out_channels,
4195 .integer = 1,
4196 };
4197 return snd_interval_refine(c, &t);
4198 }
4199 return 0;
4200 }
4201
4202 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4203 struct snd_pcm_hw_rule *rule)
4204 {
4205 struct hdsp *hdsp = rule->private;
4206 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4207 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4208 if (c->min >= hdsp->ss_out_channels) {
4209 struct snd_interval t = {
4210 .min = 32000,
4211 .max = 48000,
4212 .integer = 1,
4213 };
4214 return snd_interval_refine(r, &t);
4215 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4216 struct snd_interval t = {
4217 .min = 128000,
4218 .max = 192000,
4219 .integer = 1,
4220 };
4221 return snd_interval_refine(r, &t);
4222 } else if (c->max <= hdsp->ds_out_channels) {
4223 struct snd_interval t = {
4224 .min = 64000,
4225 .max = 96000,
4226 .integer = 1,
4227 };
4228 return snd_interval_refine(r, &t);
4229 }
4230 return 0;
4231 }
4232
4233 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4234 struct snd_pcm_hw_rule *rule)
4235 {
4236 struct hdsp *hdsp = rule->private;
4237 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4238 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4239 if (c->min >= hdsp->ss_in_channels) {
4240 struct snd_interval t = {
4241 .min = 32000,
4242 .max = 48000,
4243 .integer = 1,
4244 };
4245 return snd_interval_refine(r, &t);
4246 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4247 struct snd_interval t = {
4248 .min = 128000,
4249 .max = 192000,
4250 .integer = 1,
4251 };
4252 return snd_interval_refine(r, &t);
4253 } else if (c->max <= hdsp->ds_in_channels) {
4254 struct snd_interval t = {
4255 .min = 64000,
4256 .max = 96000,
4257 .integer = 1,
4258 };
4259 return snd_interval_refine(r, &t);
4260 }
4261 return 0;
4262 }
4263
4264 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4265 {
4266 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4267 struct snd_pcm_runtime *runtime = substream->runtime;
4268
4269 if (hdsp_check_for_iobox (hdsp))
4270 return -EIO;
4271
4272 if (hdsp_check_for_firmware(hdsp, 1))
4273 return -EIO;
4274
4275 spin_lock_irq(&hdsp->lock);
4276
4277 snd_pcm_set_sync(substream);
4278
4279 runtime->hw = snd_hdsp_playback_subinfo;
4280 runtime->dma_area = hdsp->playback_buffer;
4281 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4282
4283 hdsp->playback_pid = current->pid;
4284 hdsp->playback_substream = substream;
4285
4286 spin_unlock_irq(&hdsp->lock);
4287
4288 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4289 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4290 if (hdsp->clock_source_locked) {
4291 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4292 } else if (hdsp->io_type == H9632) {
4293 runtime->hw.rate_max = 192000;
4294 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4295 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4296 }
4297 if (hdsp->io_type == H9632) {
4298 runtime->hw.channels_min = hdsp->qs_out_channels;
4299 runtime->hw.channels_max = hdsp->ss_out_channels;
4300 }
4301
4302 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4303 snd_hdsp_hw_rule_out_channels, hdsp,
4304 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4305 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4306 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4307 SNDRV_PCM_HW_PARAM_RATE, -1);
4308 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4309 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4310 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4311
4312 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4313 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4314 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4315 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4316 return 0;
4317 }
4318
4319 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4320 {
4321 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4322
4323 spin_lock_irq(&hdsp->lock);
4324
4325 hdsp->playback_pid = -1;
4326 hdsp->playback_substream = NULL;
4327
4328 spin_unlock_irq(&hdsp->lock);
4329
4330 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4331 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4332 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4333 return 0;
4334 }
4335
4336
4337 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4338 {
4339 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4340 struct snd_pcm_runtime *runtime = substream->runtime;
4341
4342 if (hdsp_check_for_iobox (hdsp))
4343 return -EIO;
4344
4345 if (hdsp_check_for_firmware(hdsp, 1))
4346 return -EIO;
4347
4348 spin_lock_irq(&hdsp->lock);
4349
4350 snd_pcm_set_sync(substream);
4351
4352 runtime->hw = snd_hdsp_capture_subinfo;
4353 runtime->dma_area = hdsp->capture_buffer;
4354 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4355
4356 hdsp->capture_pid = current->pid;
4357 hdsp->capture_substream = substream;
4358
4359 spin_unlock_irq(&hdsp->lock);
4360
4361 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4362 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4363 if (hdsp->io_type == H9632) {
4364 runtime->hw.channels_min = hdsp->qs_in_channels;
4365 runtime->hw.channels_max = hdsp->ss_in_channels;
4366 runtime->hw.rate_max = 192000;
4367 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4368 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4369 }
4370 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4371 snd_hdsp_hw_rule_in_channels, hdsp,
4372 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4373 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4374 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4375 SNDRV_PCM_HW_PARAM_RATE, -1);
4376 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4377 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4378 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4379 return 0;
4380 }
4381
4382 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4383 {
4384 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4385
4386 spin_lock_irq(&hdsp->lock);
4387
4388 hdsp->capture_pid = -1;
4389 hdsp->capture_substream = NULL;
4390
4391 spin_unlock_irq(&hdsp->lock);
4392 return 0;
4393 }
4394
4395 static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
4396 {
4397 /* we have nothing to initialize but the call is required */
4398 return 0;
4399 }
4400
4401
4402 /* helper functions for copying meter values */
4403 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4404 {
4405 u32 val = readl(src);
4406 return copy_to_user(dest, &val, 4);
4407 }
4408
4409 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4410 {
4411 u32 rms_low, rms_high;
4412 u64 rms;
4413 rms_low = readl(src_low);
4414 rms_high = readl(src_high);
4415 rms = ((u64)rms_high << 32) | rms_low;
4416 return copy_to_user(dest, &rms, 8);
4417 }
4418
4419 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4420 {
4421 u32 rms_low, rms_high;
4422 u64 rms;
4423 rms_low = readl(src_low) & 0xffffff00;
4424 rms_high = readl(src_high) & 0xffffff00;
4425 rms = ((u64)rms_high << 32) | rms_low;
4426 return copy_to_user(dest, &rms, 8);
4427 }
4428
4429 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4430 {
4431 int doublespeed = 0;
4432 int i, j, channels, ofs;
4433
4434 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4435 doublespeed = 1;
4436 channels = doublespeed ? 14 : 26;
4437 for (i = 0, j = 0; i < 26; ++i) {
4438 if (doublespeed && (i & 4))
4439 continue;
4440 ofs = HDSP_9652_peakBase - j * 4;
4441 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4442 return -EFAULT;
4443 ofs -= channels * 4;
4444 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4445 return -EFAULT;
4446 ofs -= channels * 4;
4447 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4448 return -EFAULT;
4449 ofs = HDSP_9652_rmsBase + j * 8;
4450 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4451 hdsp->iobase + ofs + 4))
4452 return -EFAULT;
4453 ofs += channels * 8;
4454 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4455 hdsp->iobase + ofs + 4))
4456 return -EFAULT;
4457 ofs += channels * 8;
4458 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4459 hdsp->iobase + ofs + 4))
4460 return -EFAULT;
4461 j++;
4462 }
4463 return 0;
4464 }
4465
4466 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4467 {
4468 int i, j;
4469 struct hdsp_9632_meters __iomem *m;
4470 int doublespeed = 0;
4471
4472 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4473 doublespeed = 1;
4474 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4475 for (i = 0, j = 0; i < 16; ++i, ++j) {
4476 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4477 return -EFAULT;
4478 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4479 return -EFAULT;
4480 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4481 return -EFAULT;
4482 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4483 &m->input_rms_high[j]))
4484 return -EFAULT;
4485 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4486 &m->playback_rms_high[j]))
4487 return -EFAULT;
4488 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4489 &m->output_rms_high[j]))
4490 return -EFAULT;
4491 if (doublespeed && i == 3) i += 4;
4492 }
4493 return 0;
4494 }
4495
4496 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4497 {
4498 int i;
4499
4500 for (i = 0; i < 26; i++) {
4501 if (copy_u32_le(&peak_rms->playback_peaks[i],
4502 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4503 return -EFAULT;
4504 if (copy_u32_le(&peak_rms->input_peaks[i],
4505 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4506 return -EFAULT;
4507 }
4508 for (i = 0; i < 28; i++) {
4509 if (copy_u32_le(&peak_rms->output_peaks[i],
4510 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4511 return -EFAULT;
4512 }
4513 for (i = 0; i < 26; ++i) {
4514 if (copy_u64_le(&peak_rms->playback_rms[i],
4515 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4516 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4517 return -EFAULT;
4518 if (copy_u64_le(&peak_rms->input_rms[i],
4519 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4520 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4521 return -EFAULT;
4522 }
4523 return 0;
4524 }
4525
4526 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4527 {
4528 struct hdsp *hdsp = (struct hdsp *)hw->private_data;
4529 void __user *argp = (void __user *)arg;
4530
4531 switch (cmd) {
4532 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4533 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4534
4535 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4536 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4537 return -EINVAL;
4538 }
4539
4540 switch (hdsp->io_type) {
4541 case H9652:
4542 return hdsp_9652_get_peak(hdsp, peak_rms);
4543 case H9632:
4544 return hdsp_9632_get_peak(hdsp, peak_rms);
4545 default:
4546 return hdsp_get_peak(hdsp, peak_rms);
4547 }
4548 }
4549 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4550 struct hdsp_config_info info;
4551 unsigned long flags;
4552 int i;
4553
4554 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4555 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n");
4556 return -EINVAL;
4557 }
4558 spin_lock_irqsave(&hdsp->lock, flags);
4559 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4560 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4561 if (hdsp->io_type != H9632)
4562 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4563 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4564 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i)
4565 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4566 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4567 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp);
4568 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp);
4569 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp);
4570 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp);
4571 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4572 info.system_sample_rate = hdsp->system_sample_rate;
4573 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4574 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4575 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4576 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4577 info.line_out = (unsigned char)hdsp_line_out(hdsp);
4578 if (hdsp->io_type == H9632) {
4579 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4580 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4581 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4582 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp);
4583
4584 }
4585 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4586 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp);
4587 spin_unlock_irqrestore(&hdsp->lock, flags);
4588 if (copy_to_user(argp, &info, sizeof(info)))
4589 return -EFAULT;
4590 break;
4591 }
4592 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4593 struct hdsp_9632_aeb h9632_aeb;
4594
4595 if (hdsp->io_type != H9632) return -EINVAL;
4596 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4597 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4598 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4599 return -EFAULT;
4600 break;
4601 }
4602 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4603 struct hdsp_version hdsp_version;
4604 int err;
4605
4606 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4607 if (hdsp->io_type == Undefined) {
4608 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4609 return err;
4610 }
4611 hdsp_version.io_type = hdsp->io_type;
4612 hdsp_version.firmware_rev = hdsp->firmware_rev;
4613 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4614 return -EFAULT;
4615 break;
4616 }
4617 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4618 struct hdsp_firmware __user *firmware;
4619 u32 __user *firmware_data;
4620 int err;
4621
4622 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4623 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4624 if (hdsp->io_type == Undefined) return -EINVAL;
4625
4626 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4627 return -EBUSY;
4628
4629 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
4630 firmware = (struct hdsp_firmware __user *)argp;
4631
4632 if (get_user(firmware_data, &firmware->firmware_data))
4633 return -EFAULT;
4634
4635 if (hdsp_check_for_iobox (hdsp))
4636 return -EIO;
4637
4638 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0)
4639 return -EFAULT;
4640
4641 hdsp->state |= HDSP_FirmwareCached;
4642
4643 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4644 return err;
4645
4646 if (!(hdsp->state & HDSP_InitializationComplete)) {
4647 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4648 return err;
4649
4650 snd_hdsp_initialize_channels(hdsp);
4651 snd_hdsp_initialize_midi_flush(hdsp);
4652
4653 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4654 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4655 return err;
4656 }
4657 }
4658 break;
4659 }
4660 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4661 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4662 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4663 return -EFAULT;
4664 break;
4665 }
4666 default:
4667 return -EINVAL;
4668 }
4669 return 0;
4670 }
4671
4672 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4673 .open = snd_hdsp_playback_open,
4674 .close = snd_hdsp_playback_release,
4675 .ioctl = snd_hdsp_ioctl,
4676 .hw_params = snd_hdsp_hw_params,
4677 .prepare = snd_hdsp_prepare,
4678 .trigger = snd_hdsp_trigger,
4679 .pointer = snd_hdsp_hw_pointer,
4680 .copy = snd_hdsp_playback_copy,
4681 .silence = snd_hdsp_hw_silence,
4682 };
4683
4684 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4685 .open = snd_hdsp_capture_open,
4686 .close = snd_hdsp_capture_release,
4687 .ioctl = snd_hdsp_ioctl,
4688 .hw_params = snd_hdsp_hw_params,
4689 .prepare = snd_hdsp_prepare,
4690 .trigger = snd_hdsp_trigger,
4691 .pointer = snd_hdsp_hw_pointer,
4692 .copy = snd_hdsp_capture_copy,
4693 };
4694
4695 <<<<<<< HEAD:sound/pci/rme9652/hdsp.c
4696 static int __devinit snd_hdsp_create_hwdep(struct snd_card *card,
4697 struct hdsp *hdsp)
4698 =======
4699 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4700 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/rme9652/hdsp.c
4701 {
4702 struct snd_hwdep *hw;
4703 int err;
4704
4705 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4706 return err;
4707
4708 hdsp->hwdep = hw;
4709 hw->private_data = hdsp;
4710 strcpy(hw->name, "HDSP hwdep interface");
4711
4712 hw->ops.open = snd_hdsp_hwdep_dummy_op;
4713 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4714 hw->ops.release = snd_hdsp_hwdep_dummy_op;
4715
4716 return 0;
4717 }
4718
4719 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4720 {
4721 struct snd_pcm *pcm;
4722 int err;
4723
4724 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4725 return err;
4726
4727 hdsp->pcm = pcm;
4728 pcm->private_data = hdsp;
4729 strcpy(pcm->name, hdsp->card_name);
4730
4731 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4732 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4733
4734 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4735
4736 return 0;
4737 }
4738
4739 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4740 {
4741 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4742 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4743 }
4744
4745 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4746 {
4747 int i;
4748
4749 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4750 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
4751 return -EIO;
4752 }
4753
4754 for (i = 0; i < hdsp->max_channels; ++i) {
4755 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4756 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4757 }
4758
4759 return 0;
4760 }
4761
4762 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4763 {
4764 int status, aebi_channels, aebo_channels;
4765
4766 switch (hdsp->io_type) {
4767 case Digiface:
4768 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4769 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4770 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4771 break;
4772
4773 case H9652:
4774 hdsp->card_name = "RME Hammerfall HDSP 9652";
4775 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4776 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4777 break;
4778
4779 case H9632:
4780 status = hdsp_read(hdsp, HDSP_statusRegister);
4781 /* HDSP_AEBx bits are low when AEB are connected */
4782 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4783 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4784 hdsp->card_name = "RME Hammerfall HDSP 9632";
4785 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4786 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4787 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4788 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4789 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4790 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4791 break;
4792
4793 case Multiface:
4794 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4795 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4796 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4797 break;
4798
4799 default:
4800 /* should never get here */
4801 break;
4802 }
4803 }
4804
4805 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
4806 {
4807 snd_hdsp_flush_midi_input (hdsp, 0);
4808 snd_hdsp_flush_midi_input (hdsp, 1);
4809 }
4810
4811 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
4812 {
4813 int err;
4814
4815 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
4816 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
4817 return err;
4818 }
4819
4820
4821 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
4822 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
4823 return err;
4824 }
4825
4826 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
4827 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
4828 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
4829 return err;
4830 }
4831 }
4832
4833 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
4834 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
4835 return err;
4836 }
4837
4838 snd_hdsp_proc_init(hdsp);
4839
4840 hdsp->system_sample_rate = -1;
4841 hdsp->playback_pid = -1;
4842 hdsp->capture_pid = -1;
4843 hdsp->capture_substream = NULL;
4844 hdsp->playback_substream = NULL;
4845
4846 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
4847 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
4848 return err;
4849 }
4850
4851 if (!(hdsp->state & HDSP_InitializationComplete)) {
4852 strcpy(card->shortname, "Hammerfall DSP");
4853 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
4854 hdsp->port, hdsp->irq);
4855
4856 if ((err = snd_card_register(card)) < 0) {
4857 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
4858 return err;
4859 }
4860 hdsp->state |= HDSP_InitializationComplete;
4861 }
4862
4863 return 0;
4864 }
4865
4866 #ifdef HDSP_FW_LOADER
4867 /* load firmware via hotplug fw loader */
4868 <<<<<<< HEAD:sound/pci/rme9652/hdsp.c
4869 static int __devinit hdsp_request_fw_loader(struct hdsp *hdsp)
4870 =======
4871 static int hdsp_request_fw_loader(struct hdsp *hdsp)
4872 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:sound/pci/rme9652/hdsp.c
4873 {
4874 const char *fwfile;
4875 const struct firmware *fw;
4876 int err;
4877
4878 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4879 return 0;
4880 if (hdsp->io_type == Undefined) {
4881 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4882 return err;
4883 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
4884 return 0;
4885 }
4886
4887 /* caution: max length of firmware filename is 30! */
4888 switch (hdsp->io_type) {
4889 case Multiface:
4890 if (hdsp->firmware_rev == 0xa)
4891 fwfile = "multiface_firmware.bin";
4892 else
4893 fwfile = "multiface_firmware_rev11.bin";
4894 break;
4895 case Digiface:
4896 if (hdsp->firmware_rev == 0xa)
4897 fwfile = "digiface_firmware.bin";
4898 else
4899 fwfile = "digiface_firmware_rev11.bin";
4900 break;
4901 default:
4902 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
4903 return -EINVAL;
4904 }
4905
4906 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
4907 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
4908 return -ENOENT;
4909 }
4910 if (fw->size < sizeof(hdsp->firmware_cache)) {
4911 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
4912 (int)fw->size, (int)sizeof(hdsp->firmware_cache));
4913 release_firmware(fw);
4914 return -EINVAL;
4915 }
4916
4917 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache));
4918
4919 release_firmware(fw);
4920
4921 hdsp->state |= HDSP_FirmwareCached;
4922
4923 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4924 return err;
4925
4926 if (!(hdsp->state & HDSP_InitializationComplete)) {
4927 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4928 return err;
4929
4930 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
4931 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
4932 return err;
4933 }
4934 snd_hdsp_initialize_channels(hdsp);
4935 snd_hdsp_initialize_midi_flush(hdsp);
4936 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4937 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4938 return err;
4939 }
4940 }
4941 return 0;
4942 }
4943 #endif
4944
4945 static int __devinit snd_hdsp_create(struct snd_card *card,
4946 struct hdsp *hdsp)
4947 {
4948 struct pci_dev *pci = hdsp->pci;
4949 int err;
4950 int is_9652 = 0;
4951 int is_9632 = 0;
4952
4953 hdsp->irq = -1;
4954 hdsp->state = 0;
4955 hdsp->midi[0].rmidi = NULL;
4956 hdsp->midi[1].rmidi = NULL;
4957 hdsp->midi[0].input = NULL;
4958 hdsp->midi[1].input = NULL;
4959 hdsp->midi[0].output = NULL;
4960 hdsp->midi[1].output = NULL;
4961 hdsp->midi[0].pending = 0;
4962 hdsp->midi[1].pending = 0;
4963 spin_lock_init(&hdsp->midi[0].lock);
4964 spin_lock_init(&hdsp->midi[1].lock);
4965 hdsp->iobase = NULL;
4966 hdsp->control_register = 0;
4967 hdsp->control2_register = 0;
4968 hdsp->io_type = Undefined;
4969 hdsp->max_channels = 26;
4970
4971 hdsp->card = card;
4972
4973 spin_lock_init(&hdsp->lock);
4974
4975 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
4976
4977 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
4978 hdsp->firmware_rev &= 0xff;
4979
4980 /* From Martin Bjoernsen :
4981 "It is important that the card's latency timer register in
4982 the PCI configuration space is set to a value much larger
4983 than 0 by the computer's BIOS or the driver.
4984 The windows driver always sets this 8 bit register [...]
4985 to its maximum 255 to avoid problems with some computers."
4986 */
4987 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
4988
4989 strcpy(card->driver, "H-DSP");
4990 strcpy(card->mixername, "Xilinx FPGA");
4991
4992 if (hdsp->firmware_rev < 0xa)
4993 return -ENODEV;
4994 else if (hdsp->firmware_rev < 0x64)
4995 hdsp->card_name = "RME Hammerfall DSP";
4996 else if (hdsp->firmware_rev < 0x96) {
4997 hdsp->card_name = "RME HDSP 9652";
4998 is_9652 = 1;
4999 } else {
5000 hdsp->card_name = "RME HDSP 9632";
5001 hdsp->max_channels = 16;
5002 is_9632 = 1;
5003 }
5004
5005 if ((err = pci_enable_device(pci)) < 0)
5006 return err;
5007
5008 pci_set_master(hdsp->pci);
5009
5010 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5011 return err;
5012 hdsp->port = pci_resource_start(pci, 0);
5013 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5014 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5015 return -EBUSY;
5016 }
5017
5018 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5019 "hdsp", hdsp)) {
5020 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5021 return -EBUSY;
5022 }
5023
5024 hdsp->irq = pci->irq;
5025 hdsp->precise_ptr = 0;
5026 hdsp->use_midi_tasklet = 1;
5027 hdsp->dds_value = 0;
5028
5029 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5030 return err;
5031
5032 if (!is_9652 && !is_9632) {
5033 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */
5034 ssleep(2);
5035
5036 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5037 #ifdef HDSP_FW_LOADER
5038 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5039 /* we don't fail as this can happen
5040 if userspace is not ready for
5041 firmware upload
5042 */
5043 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5044 else
5045 /* init is complete, we return */
5046 return 0;
5047 #endif
5048 /* no iobox connected, we defer initialization */
5049 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5050 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5051 return err;
5052 return 0;
5053 } else {
5054 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5055 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5056 hdsp->io_type = Multiface;
5057 else
5058 hdsp->io_type = Digiface;
5059 }
5060 }
5061
5062 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5063 return err;
5064
5065 if (is_9652)
5066 hdsp->io_type = H9652;
5067
5068 if (is_9632)
5069 hdsp->io_type = H9632;
5070
5071 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5072 return err;
5073
5074 snd_hdsp_initialize_channels(hdsp);
5075 snd_hdsp_initialize_midi_flush(hdsp);
5076
5077 hdsp->state |= HDSP_FirmwareLoaded;
5078
5079 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5080 return err;
5081
5082 return 0;
5083 }
5084
5085 static int snd_hdsp_free(struct hdsp *hdsp)
5086 {
5087 if (hdsp->port) {
5088 /* stop the audio, and cancel all interrupts */
5089 tasklet_kill(&hdsp->midi_tasklet);
5090 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5091 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5092 }
5093
5094 if (hdsp->irq >= 0)
5095 free_irq(hdsp->irq, (void *)hdsp);
5096
5097 snd_hdsp_free_buffers(hdsp);
5098
5099 if (hdsp->iobase)
5100 iounmap(hdsp->iobase);
5101
5102 if (hdsp->port)
5103 pci_release_regions(hdsp->pci);
5104
5105 pci_disable_device(hdsp->pci);
5106 return 0;
5107 }
5108
5109 static void snd_hdsp_card_free(struct snd_card *card)
5110 {
5111 struct hdsp *hdsp = (struct hdsp *) card->private_data;
5112
5113 if (hdsp)
5114 snd_hdsp_free(hdsp);
5115 }
5116
5117 static int __devinit snd_hdsp_probe(struct pci_dev *pci,
5118 const struct pci_device_id *pci_id)
5119 {
5120 static int dev;
5121 struct hdsp *hdsp;
5122 struct snd_card *card;
5123 int err;
5124
5125 if (dev >= SNDRV_CARDS)
5126 return -ENODEV;
5127 if (!enable[dev]) {
5128 dev++;
5129 return -ENOENT;
5130 }
5131
5132 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp))))
5133 return -ENOMEM;
5134
5135 hdsp = (struct hdsp *) card->private_data;
5136 card->private_free = snd_hdsp_card_free;
5137 hdsp->dev = dev;
5138 hdsp->pci = pci;
5139 snd_card_set_dev(card, &pci->dev);
5140
5141 if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5142 snd_card_free(card);
5143 return err;
5144 }
5145
5146 strcpy(card->shortname, "Hammerfall DSP");
5147 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5148 hdsp->port, hdsp->irq);
5149
5150 if ((err = snd_card_register(card)) < 0) {
5151 snd_card_free(card);
5152 return err;
5153 }
5154 pci_set_drvdata(pci, card);
5155 dev++;
5156 return 0;
5157 }
5158
5159 static void __devexit snd_hdsp_remove(struct pci_dev *pci)
5160 {
5161 snd_card_free(pci_get_drvdata(pci));
5162 pci_set_drvdata(pci, NULL);
5163 }
5164
5165 static struct pci_driver driver = {
5166 .name = "RME Hammerfall DSP",
5167 .id_table = snd_hdsp_ids,
5168 .probe = snd_hdsp_probe,
5169 .remove = __devexit_p(snd_hdsp_remove),
5170 };
5171
5172 static int __init alsa_card_hdsp_init(void)
5173 {
5174 return pci_register_driver(&driver);
5175 }
5176
5177 static void __exit alsa_card_hdsp_exit(void)
5178 {
5179 pci_unregister_driver(&driver);
5180 }
5181
5182 module_init(alsa_card_hdsp_init)
5183 module_exit(alsa_card_hdsp_exit)
WRT350N Kernel Patches