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Merge master.kernel.org:/pub/scm/linux/kernel/git/perex/alsa
[wrt350n-kernel.git] / drivers / scsi / sata_sil.c
blobd0a85073ebf7c7ecfc9872f5b9f3a94aa13e396a
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.0"
50
51 enum {
52 /*
53 * host flags
54 */
55 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
56 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
57 SIL_FLAG_MOD15WRITE = (1 << 30),
58
59 SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
60 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
61
62 /*
63 * Controller IDs
64 */
65 sil_3112 = 0,
66 sil_3112_no_sata_irq = 1,
67 sil_3512 = 2,
68 sil_3114 = 3,
69
70 /*
71 * Register offsets
72 */
73 SIL_SYSCFG = 0x48,
74
75 /*
76 * Register bits
77 */
78 /* SYSCFG */
79 SIL_MASK_IDE0_INT = (1 << 22),
80 SIL_MASK_IDE1_INT = (1 << 23),
81 SIL_MASK_IDE2_INT = (1 << 24),
82 SIL_MASK_IDE3_INT = (1 << 25),
83 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
84 SIL_MASK_4PORT = SIL_MASK_2PORT |
85 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
86
87 /* BMDMA/BMDMA2 */
88 SIL_INTR_STEERING = (1 << 1),
89
90 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
91 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
92 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
93 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
94 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
95 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
96 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
97 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
98 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
99 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
100
101 /* SIEN */
102 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
103
104 /*
105 * Others
106 */
107 SIL_QUIRK_MOD15WRITE = (1 << 0),
108 SIL_QUIRK_UDMA5MAX = (1 << 1),
109 };
110
111 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
112 static int sil_pci_device_resume(struct pci_dev *pdev);
113 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
114 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
115 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
116 static void sil_post_set_mode (struct ata_port *ap);
117 static irqreturn_t sil_interrupt(int irq, void *dev_instance,
118 struct pt_regs *regs);
119 static void sil_freeze(struct ata_port *ap);
120 static void sil_thaw(struct ata_port *ap);
121
122
123 static const struct pci_device_id sil_pci_tbl[] = {
124 { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
125 { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
126 { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
127 { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
128 { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
129 { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_no_sata_irq },
130 { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_no_sata_irq },
131 { } /* terminate list */
132 };
133
134
135 /* TODO firmware versions should be added - eric */
136 static const struct sil_drivelist {
137 const char * product;
138 unsigned int quirk;
139 } sil_blacklist [] = {
140 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
141 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
142 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
143 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
144 { "ST380013AS", SIL_QUIRK_MOD15WRITE },
145 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
146 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
147 { "ST3160023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST3120026AS", SIL_QUIRK_MOD15WRITE },
149 { "ST3200822AS", SIL_QUIRK_MOD15WRITE },
150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
156 { }
157 };
158
159 static struct pci_driver sil_pci_driver = {
160 .name = DRV_NAME,
161 .id_table = sil_pci_tbl,
162 .probe = sil_init_one,
163 .remove = ata_pci_remove_one,
164 .suspend = ata_pci_device_suspend,
165 .resume = sil_pci_device_resume,
166 };
167
168 static struct scsi_host_template sil_sht = {
169 .module = THIS_MODULE,
170 .name = DRV_NAME,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
177 .emulated = ATA_SHT_EMULATED,
178 .use_clustering = ATA_SHT_USE_CLUSTERING,
179 .proc_name = DRV_NAME,
180 .dma_boundary = ATA_DMA_BOUNDARY,
181 .slave_configure = ata_scsi_slave_config,
182 .slave_destroy = ata_scsi_slave_destroy,
183 .bios_param = ata_std_bios_param,
184 .suspend = ata_scsi_device_suspend,
185 .resume = ata_scsi_device_resume,
186 };
187
188 static const struct ata_port_operations sil_ops = {
189 .port_disable = ata_port_disable,
190 .dev_config = sil_dev_config,
191 .tf_load = ata_tf_load,
192 .tf_read = ata_tf_read,
193 .check_status = ata_check_status,
194 .exec_command = ata_exec_command,
195 .dev_select = ata_std_dev_select,
196 .post_set_mode = sil_post_set_mode,
197 .bmdma_setup = ata_bmdma_setup,
198 .bmdma_start = ata_bmdma_start,
199 .bmdma_stop = ata_bmdma_stop,
200 .bmdma_status = ata_bmdma_status,
201 .qc_prep = ata_qc_prep,
202 .qc_issue = ata_qc_issue_prot,
203 .data_xfer = ata_mmio_data_xfer,
204 .freeze = sil_freeze,
205 .thaw = sil_thaw,
206 .error_handler = ata_bmdma_error_handler,
207 .post_internal_cmd = ata_bmdma_post_internal_cmd,
208 .irq_handler = sil_interrupt,
209 .irq_clear = ata_bmdma_irq_clear,
210 .scr_read = sil_scr_read,
211 .scr_write = sil_scr_write,
212 .port_start = ata_port_start,
213 .port_stop = ata_port_stop,
214 .host_stop = ata_pci_host_stop,
215 };
216
217 static const struct ata_port_info sil_port_info[] = {
218 /* sil_3112 */
219 {
220 .sht = &sil_sht,
221 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE,
222 .pio_mask = 0x1f, /* pio0-4 */
223 .mwdma_mask = 0x07, /* mwdma0-2 */
224 .udma_mask = 0x3f, /* udma0-5 */
225 .port_ops = &sil_ops,
226 },
227 /* sil_3112_no_sata_irq */
228 {
229 .sht = &sil_sht,
230 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE |
231 SIL_FLAG_NO_SATA_IRQ,
232 .pio_mask = 0x1f, /* pio0-4 */
233 .mwdma_mask = 0x07, /* mwdma0-2 */
234 .udma_mask = 0x3f, /* udma0-5 */
235 .port_ops = &sil_ops,
236 },
237 /* sil_3512 */
238 {
239 .sht = &sil_sht,
240 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
241 .pio_mask = 0x1f, /* pio0-4 */
242 .mwdma_mask = 0x07, /* mwdma0-2 */
243 .udma_mask = 0x3f, /* udma0-5 */
244 .port_ops = &sil_ops,
245 },
246 /* sil_3114 */
247 {
248 .sht = &sil_sht,
249 .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
250 .pio_mask = 0x1f, /* pio0-4 */
251 .mwdma_mask = 0x07, /* mwdma0-2 */
252 .udma_mask = 0x3f, /* udma0-5 */
253 .port_ops = &sil_ops,
254 },
255 };
256
257 /* per-port register offsets */
258 /* TODO: we can probably calculate rather than use a table */
259 static const struct {
260 unsigned long tf; /* ATA taskfile register block */
261 unsigned long ctl; /* ATA control/altstatus register block */
262 unsigned long bmdma; /* DMA register block */
263 unsigned long bmdma2; /* DMA register block #2 */
264 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
265 unsigned long scr; /* SATA control register block */
266 unsigned long sien; /* SATA Interrupt Enable register */
267 unsigned long xfer_mode;/* data transfer mode register */
268 unsigned long sfis_cfg; /* SATA FIS reception config register */
269 } sil_port[] = {
270 /* port 0 ... */
271 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
272 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
273 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
274 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
275 /* ... port 3 */
276 };
277
278 MODULE_AUTHOR("Jeff Garzik");
279 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
280 MODULE_LICENSE("GPL");
281 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
282 MODULE_VERSION(DRV_VERSION);
283
284 static int slow_down = 0;
285 module_param(slow_down, int, 0444);
286 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
287
288
289 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
290 {
291 u8 cache_line = 0;
292 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
293 return cache_line;
294 }
295
296 static void sil_post_set_mode (struct ata_port *ap)
297 {
298 struct ata_host_set *host_set = ap->host_set;
299 struct ata_device *dev;
300 void __iomem *addr =
301 host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
302 u32 tmp, dev_mode[2];
303 unsigned int i;
304
305 for (i = 0; i < 2; i++) {
306 dev = &ap->device[i];
307 if (!ata_dev_enabled(dev))
308 dev_mode[i] = 0; /* PIO0/1/2 */
309 else if (dev->flags & ATA_DFLAG_PIO)
310 dev_mode[i] = 1; /* PIO3/4 */
311 else
312 dev_mode[i] = 3; /* UDMA */
313 /* value 2 indicates MDMA */
314 }
315
316 tmp = readl(addr);
317 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
318 tmp |= dev_mode[0];
319 tmp |= (dev_mode[1] << 4);
320 writel(tmp, addr);
321 readl(addr); /* flush */
322 }
323
324 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
325 {
326 unsigned long offset = ap->ioaddr.scr_addr;
327
328 switch (sc_reg) {
329 case SCR_STATUS:
330 return offset + 4;
331 case SCR_ERROR:
332 return offset + 8;
333 case SCR_CONTROL:
334 return offset;
335 default:
336 /* do nothing */
337 break;
338 }
339
340 return 0;
341 }
342
343 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
344 {
345 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
346 if (mmio)
347 return readl(mmio);
348 return 0xffffffffU;
349 }
350
351 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
352 {
353 void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
354 if (mmio)
355 writel(val, mmio);
356 }
357
358 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
359 {
360 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
361 u8 status;
362
363 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
364 u32 serror;
365
366 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
367 * controllers continue to assert IRQ as long as
368 * SError bits are pending. Clear SError immediately.
369 */
370 serror = sil_scr_read(ap, SCR_ERROR);
371 sil_scr_write(ap, SCR_ERROR, serror);
372
373 /* Trigger hotplug and accumulate SError only if the
374 * port isn't already frozen. Otherwise, PHY events
375 * during hardreset makes controllers with broken SIEN
376 * repeat probing needlessly.
377 */
378 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
379 ata_ehi_hotplugged(&ap->eh_info);
380 ap->eh_info.serror |= serror;
381 }
382
383 goto freeze;
384 }
385
386 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN))
387 goto freeze;
388
389 /* Check whether we are expecting interrupt in this state */
390 switch (ap->hsm_task_state) {
391 case HSM_ST_FIRST:
392 /* Some pre-ATAPI-4 devices assert INTRQ
393 * at this state when ready to receive CDB.
394 */
395
396 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
397 * The flag was turned on only for atapi devices.
398 * No need to check is_atapi_taskfile(&qc->tf) again.
399 */
400 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
401 goto err_hsm;
402 break;
403 case HSM_ST_LAST:
404 if (qc->tf.protocol == ATA_PROT_DMA ||
405 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
406 /* clear DMA-Start bit */
407 ap->ops->bmdma_stop(qc);
408
409 if (bmdma2 & SIL_DMA_ERROR) {
410 qc->err_mask |= AC_ERR_HOST_BUS;
411 ap->hsm_task_state = HSM_ST_ERR;
412 }
413 }
414 break;
415 case HSM_ST:
416 break;
417 default:
418 goto err_hsm;
419 }
420
421 /* check main status, clearing INTRQ */
422 status = ata_chk_status(ap);
423 if (unlikely(status & ATA_BUSY))
424 goto err_hsm;
425
426 /* ack bmdma irq events */
427 ata_bmdma_irq_clear(ap);
428
429 /* kick HSM in the ass */
430 ata_hsm_move(ap, qc, status, 0);
431
432 return;
433
434 err_hsm:
435 qc->err_mask |= AC_ERR_HSM;
436 freeze:
437 ata_port_freeze(ap);
438 }
439
440 static irqreturn_t sil_interrupt(int irq, void *dev_instance,
441 struct pt_regs *regs)
442 {
443 struct ata_host_set *host_set = dev_instance;
444 void __iomem *mmio_base = host_set->mmio_base;
445 int handled = 0;
446 int i;
447
448 spin_lock(&host_set->lock);
449
450 for (i = 0; i < host_set->n_ports; i++) {
451 struct ata_port *ap = host_set->ports[i];
452 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
453
454 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
455 continue;
456
457 /* turn off SATA_IRQ if not supported */
458 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
459 bmdma2 &= ~SIL_DMA_SATA_IRQ;
460
461 if (bmdma2 == 0xffffffff ||
462 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
463 continue;
464
465 sil_host_intr(ap, bmdma2);
466 handled = 1;
467 }
468
469 spin_unlock(&host_set->lock);
470
471 return IRQ_RETVAL(handled);
472 }
473
474 static void sil_freeze(struct ata_port *ap)
475 {
476 void __iomem *mmio_base = ap->host_set->mmio_base;
477 u32 tmp;
478
479 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
480 writel(0, mmio_base + sil_port[ap->port_no].sien);
481
482 /* plug IRQ */
483 tmp = readl(mmio_base + SIL_SYSCFG);
484 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
485 writel(tmp, mmio_base + SIL_SYSCFG);
486 readl(mmio_base + SIL_SYSCFG); /* flush */
487 }
488
489 static void sil_thaw(struct ata_port *ap)
490 {
491 void __iomem *mmio_base = ap->host_set->mmio_base;
492 u32 tmp;
493
494 /* clear IRQ */
495 ata_chk_status(ap);
496 ata_bmdma_irq_clear(ap);
497
498 /* turn on SATA IRQ if supported */
499 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
500 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
501
502 /* turn on IRQ */
503 tmp = readl(mmio_base + SIL_SYSCFG);
504 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
505 writel(tmp, mmio_base + SIL_SYSCFG);
506 }
507
508 /**
509 * sil_dev_config - Apply device/host-specific errata fixups
510 * @ap: Port containing device to be examined
511 * @dev: Device to be examined
512 *
513 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
514 * device is known to be present, this function is called.
515 * We apply two errata fixups which are specific to Silicon Image,
516 * a Seagate and a Maxtor fixup.
517 *
518 * For certain Seagate devices, we must limit the maximum sectors
519 * to under 8K.
520 *
521 * For certain Maxtor devices, we must not program the drive
522 * beyond udma5.
523 *
524 * Both fixups are unfairly pessimistic. As soon as I get more
525 * information on these errata, I will create a more exhaustive
526 * list, and apply the fixups to only the specific
527 * devices/hosts/firmwares that need it.
528 *
529 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
530 * The Maxtor quirk is in the blacklist, but I'm keeping the original
531 * pessimistic fix for the following reasons...
532 * - There seems to be less info on it, only one device gleaned off the
533 * Windows driver, maybe only one is affected. More info would be greatly
534 * appreciated.
535 * - But then again UDMA5 is hardly anything to complain about
536 */
537 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
538 {
539 unsigned int n, quirks = 0;
540 unsigned char model_num[41];
541
542 ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
543
544 for (n = 0; sil_blacklist[n].product; n++)
545 if (!strcmp(sil_blacklist[n].product, model_num)) {
546 quirks = sil_blacklist[n].quirk;
547 break;
548 }
549
550 /* limit requests to 15 sectors */
551 if (slow_down ||
552 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
553 (quirks & SIL_QUIRK_MOD15WRITE))) {
554 ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix "
555 "(mod15write workaround)\n");
556 dev->max_sectors = 15;
557 return;
558 }
559
560 /* limit to udma5 */
561 if (quirks & SIL_QUIRK_UDMA5MAX) {
562 ata_dev_printk(dev, KERN_INFO,
563 "applying Maxtor errata fix %s\n", model_num);
564 dev->udma_mask &= ATA_UDMA5;
565 return;
566 }
567 }
568
569 static void sil_init_controller(struct pci_dev *pdev,
570 int n_ports, unsigned long host_flags,
571 void __iomem *mmio_base)
572 {
573 u8 cls;
574 u32 tmp;
575 int i;
576
577 /* Initialize FIFO PCI bus arbitration */
578 cls = sil_get_device_cache_line(pdev);
579 if (cls) {
580 cls >>= 3;
581 cls++; /* cls = (line_size/8)+1 */
582 for (i = 0; i < n_ports; i++)
583 writew(cls << 8 | cls,
584 mmio_base + sil_port[i].fifo_cfg);
585 } else
586 dev_printk(KERN_WARNING, &pdev->dev,
587 "cache line size not set. Driver may not function\n");
588
589 /* Apply R_ERR on DMA activate FIS errata workaround */
590 if (host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
591 int cnt;
592
593 for (i = 0, cnt = 0; i < n_ports; i++) {
594 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
595 if ((tmp & 0x3) != 0x01)
596 continue;
597 if (!cnt)
598 dev_printk(KERN_INFO, &pdev->dev,
599 "Applying R_ERR on DMA activate "
600 "FIS errata fix\n");
601 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
602 cnt++;
603 }
604 }
605
606 if (n_ports == 4) {
607 /* flip the magic "make 4 ports work" bit */
608 tmp = readl(mmio_base + sil_port[2].bmdma);
609 if ((tmp & SIL_INTR_STEERING) == 0)
610 writel(tmp | SIL_INTR_STEERING,
611 mmio_base + sil_port[2].bmdma);
612 }
613 }
614
615 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
616 {
617 static int printed_version;
618 struct ata_probe_ent *probe_ent = NULL;
619 unsigned long base;
620 void __iomem *mmio_base;
621 int rc;
622 unsigned int i;
623 int pci_dev_busy = 0;
624
625 if (!printed_version++)
626 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
627
628 rc = pci_enable_device(pdev);
629 if (rc)
630 return rc;
631
632 rc = pci_request_regions(pdev, DRV_NAME);
633 if (rc) {
634 pci_dev_busy = 1;
635 goto err_out;
636 }
637
638 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
639 if (rc)
640 goto err_out_regions;
641 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
642 if (rc)
643 goto err_out_regions;
644
645 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
646 if (probe_ent == NULL) {
647 rc = -ENOMEM;
648 goto err_out_regions;
649 }
650
651 INIT_LIST_HEAD(&probe_ent->node);
652 probe_ent->dev = pci_dev_to_dev(pdev);
653 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
654 probe_ent->sht = sil_port_info[ent->driver_data].sht;
655 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
656 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
657 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
658 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
659 probe_ent->irq = pdev->irq;
660 probe_ent->irq_flags = IRQF_SHARED;
661 probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
662
663 mmio_base = pci_iomap(pdev, 5, 0);
664 if (mmio_base == NULL) {
665 rc = -ENOMEM;
666 goto err_out_free_ent;
667 }
668
669 probe_ent->mmio_base = mmio_base;
670
671 base = (unsigned long) mmio_base;
672
673 for (i = 0; i < probe_ent->n_ports; i++) {
674 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
675 probe_ent->port[i].altstatus_addr =
676 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
677 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
678 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
679 ata_std_ports(&probe_ent->port[i]);
680 }
681
682 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags,
683 mmio_base);
684
685 pci_set_master(pdev);
686
687 /* FIXME: check ata_device_add return value */
688 ata_device_add(probe_ent);
689 kfree(probe_ent);
690
691 return 0;
692
693 err_out_free_ent:
694 kfree(probe_ent);
695 err_out_regions:
696 pci_release_regions(pdev);
697 err_out:
698 if (!pci_dev_busy)
699 pci_disable_device(pdev);
700 return rc;
701 }
702
703 static int sil_pci_device_resume(struct pci_dev *pdev)
704 {
705 struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev);
706
707 ata_pci_device_do_resume(pdev);
708 sil_init_controller(pdev, host_set->n_ports, host_set->ports[0]->flags,
709 host_set->mmio_base);
710 ata_host_set_resume(host_set);
711
712 return 0;
713 }
714
715 static int __init sil_init(void)
716 {
717 return pci_module_init(&sil_pci_driver);
718 }
719
720 static void __exit sil_exit(void)
721 {
722 pci_unregister_driver(&sil_pci_driver);
723 }
724
725
726 module_init(sil_init);
727 module_exit(sil_exit);
WRT350N Kernel Patches