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x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / ide / pci / sis5513.c
blob2a461de22aa005099fa7e27bb53e5de3afebeb0b
1 /*
2 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
4 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29 /*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
47 #include <linux/types.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/delay.h>
51 #include <linux/timer.h>
52 #include <linux/mm.h>
53 #include <linux/ioport.h>
54 #include <linux/blkdev.h>
55 #include <linux/hdreg.h>
56
57 #include <linux/interrupt.h>
58 #include <linux/pci.h>
59 #include <linux/init.h>
60 #include <linux/ide.h>
61
62 #include <asm/irq.h>
63
64 #include "ide-timing.h"
65
66 /* registers layout and init values are chipset family dependant */
67
68 #define ATA_16 0x01
69 #define ATA_33 0x02
70 #define ATA_66 0x03
71 #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
72 #define ATA_100 0x05
73 #define ATA_133a 0x06 // SiS961b with 133 support
74 #define ATA_133 0x07 // SiS962/963
75
76 static u8 chipset_family;
77
78 /*
79 * Devices supported
80 */
81 static const struct {
82 const char *name;
83 u16 host_id;
84 u8 chipset_family;
85 u8 flags;
86 } SiSHostChipInfo[] = {
87 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
88 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
89 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
90 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
91 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
92 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
93 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
94 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
95
96 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
97 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
98
99 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
100 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
101 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
102 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
103 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
104
105 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
106 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
107 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
108 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
109 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
110 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
111
112 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
113 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
114 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
115 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
116 };
117
118 /* Cycle time bits and values vary across chip dma capabilities
119 These three arrays hold the register layout and the values to set.
120 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
121
122 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
123 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
124 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
125 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
126 {0,0,0,0,0,0,0}, /* no udma */
127 {0,0,0,0,0,0,0}, /* no udma */
128 {3,2,1,0,0,0,0}, /* ATA_33 */
129 {7,5,3,2,1,0,0}, /* ATA_66 */
130 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
131 {11,7,5,4,2,1,0}, /* ATA_100 */
132 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
133 {15,10,7,5,3,2,1}, /* ATA_133 */
134 };
135 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
136 See SiS962 data sheet for more detail */
137 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
138 {0,0,0,0,0,0,0}, /* no udma */
139 {0,0,0,0,0,0,0}, /* no udma */
140 {2,1,1,0,0,0,0},
141 {4,3,2,1,0,0,0},
142 {4,3,2,1,0,0,0},
143 {6,4,3,1,1,1,0},
144 {9,6,4,2,2,2,2},
145 {9,6,4,2,2,2,2},
146 };
147 /* Initialize time, Active time, Recovery time vary across
148 IDE clock settings. These 3 arrays hold the register value
149 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
150 static u8 ini_time_value[][8] = {
151 {0,0,0,0,0,0,0,0},
152 {0,0,0,0,0,0,0,0},
153 {2,1,0,0,0,1,0,0},
154 {4,3,1,1,1,3,1,1},
155 {4,3,1,1,1,3,1,1},
156 {6,4,2,2,2,4,2,2},
157 {9,6,3,3,3,6,3,3},
158 {9,6,3,3,3,6,3,3},
159 };
160 static u8 act_time_value[][8] = {
161 {0,0,0,0,0,0,0,0},
162 {0,0,0,0,0,0,0,0},
163 {9,9,9,2,2,7,2,2},
164 {19,19,19,5,4,14,5,4},
165 {19,19,19,5,4,14,5,4},
166 {28,28,28,7,6,21,7,6},
167 {38,38,38,10,9,28,10,9},
168 {38,38,38,10,9,28,10,9},
169 };
170 static u8 rco_time_value[][8] = {
171 {0,0,0,0,0,0,0,0},
172 {0,0,0,0,0,0,0,0},
173 {9,2,0,2,0,7,1,1},
174 {19,5,1,5,2,16,3,2},
175 {19,5,1,5,2,16,3,2},
176 {30,9,3,9,4,25,6,4},
177 {40,12,4,12,5,34,12,5},
178 {40,12,4,12,5,34,12,5},
179 };
180
181 /*
182 * Printing configuration
183 */
184 /* Used for chipset type printing at boot time */
185 static char* chipset_capability[] = {
186 "ATA", "ATA 16",
187 "ATA 33", "ATA 66",
188 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
189 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
190 };
191
192 /*
193 * Configuration functions
194 */
195
196 static u8 sis_ata133_get_base(ide_drive_t *drive)
197 {
198 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
199 u32 reg54 = 0;
200
201 pci_read_config_dword(dev, 0x54, &reg54);
202
203 return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
204 }
205
206 static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
207 {
208 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
209 u16 t1 = 0;
210 u8 drive_pci = 0x40 + drive->dn * 2;
211
212 const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
213 const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
214
215 pci_read_config_word(dev, drive_pci, &t1);
216
217 /* clear active/recovery timings */
218 t1 &= ~0x070f;
219 if (mode >= XFER_MW_DMA_0) {
220 if (chipset_family > ATA_16)
221 t1 &= ~0x8000; /* disable UDMA */
222 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
223 } else
224 t1 |= pio_timings[mode - XFER_PIO_0];
225
226 pci_write_config_word(dev, drive_pci, t1);
227 }
228
229 static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
230 {
231 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
232 u8 t1, drive_pci = 0x40 + drive->dn * 2;
233
234 /* timing bits: 7:4 active 3:0 recovery */
235 const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
236 const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
237
238 if (mode >= XFER_MW_DMA_0) {
239 u8 t2 = 0;
240
241 pci_read_config_byte(dev, drive_pci, &t2);
242 t2 &= ~0x80; /* disable UDMA */
243 pci_write_config_byte(dev, drive_pci, t2);
244
245 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
246 } else
247 t1 = pio_timings[mode - XFER_PIO_0];
248
249 pci_write_config_byte(dev, drive_pci + 1, t1);
250 }
251
252 static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
253 {
254 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
255 u32 t1 = 0;
256 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
257
258 pci_read_config_dword(dev, drive_pci, &t1);
259
260 t1 &= 0xc0c00fff;
261 clk = (t1 & 0x08) ? ATA_133 : ATA_100;
262 if (mode >= XFER_MW_DMA_0) {
263 t1 &= ~0x04; /* disable UDMA */
264 idx = mode - XFER_MW_DMA_0 + 5;
265 } else
266 idx = mode - XFER_PIO_0;
267 t1 |= ini_time_value[clk][idx] << 12;
268 t1 |= act_time_value[clk][idx] << 16;
269 t1 |= rco_time_value[clk][idx] << 24;
270
271 pci_write_config_dword(dev, drive_pci, t1);
272 }
273
274 static void sis_program_timings(ide_drive_t *drive, const u8 mode)
275 {
276 if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
277 sis_ata16_program_timings(drive, mode);
278 else if (chipset_family < ATA_133) /* ATA_100/133a */
279 sis_ata100_program_timings(drive, mode);
280 else /* ATA_133 */
281 sis_ata133_program_timings(drive, mode);
282 }
283
284 static void config_drive_art_rwp (ide_drive_t *drive)
285 {
286 ide_hwif_t *hwif = HWIF(drive);
287 struct pci_dev *dev = to_pci_dev(hwif->dev);
288 u8 reg4bh = 0;
289 u8 rw_prefetch = 0;
290
291 pci_read_config_byte(dev, 0x4b, &reg4bh);
292
293 if (drive->media == ide_disk)
294 rw_prefetch = 0x11 << drive->dn;
295
296 if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
297 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
298 }
299
300 static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
301 {
302 config_drive_art_rwp(drive);
303 sis_program_timings(drive, XFER_PIO_0 + pio);
304 }
305
306 static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
307 {
308 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
309 u32 regdw = 0;
310 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
311
312 pci_read_config_dword(dev, drive_pci, &regdw);
313
314 regdw |= 0x04;
315 regdw &= 0xfffff00f;
316 /* check if ATA133 enable */
317 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
318 idx = mode - XFER_UDMA_0;
319 regdw |= cycle_time_value[clk][idx] << 4;
320 regdw |= cvs_time_value[clk][idx] << 8;
321
322 pci_write_config_dword(dev, drive_pci, regdw);
323 }
324
325 static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
326 {
327 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
328 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
329
330 pci_read_config_byte(dev, drive_pci + 1, &reg);
331
332 /* force the UDMA bit on if we want to use UDMA */
333 reg |= 0x80;
334 /* clean reg cycle time bits */
335 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
336 /* set reg cycle time bits */
337 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
338
339 pci_write_config_byte(dev, drive_pci + 1, reg);
340 }
341
342 static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
343 {
344 if (chipset_family >= ATA_133) /* ATA_133 */
345 sis_ata133_program_udma_timings(drive, mode);
346 else /* ATA_33/66/100a/100/133a */
347 sis_ata33_program_udma_timings(drive, mode);
348 }
349
350 static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
351 {
352 if (speed >= XFER_UDMA_0)
353 sis_program_udma_timings(drive, speed);
354 else
355 sis_program_timings(drive, speed);
356 }
357
358 static u8 sis5513_ata133_udma_filter(ide_drive_t *drive)
359 {
360 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
361 u32 regdw = 0;
362 u8 drive_pci = sis_ata133_get_base(drive);
363
364 pci_read_config_dword(dev, drive_pci, &regdw);
365
366 /* if ATA133 disable, we should not set speed above UDMA5 */
367 return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
368 }
369
370 /* Chip detection and general config */
371 static unsigned int __devinit init_chipset_sis5513 (struct pci_dev *dev, const char *name)
372 {
373 struct pci_dev *host;
374 int i = 0;
375
376 chipset_family = 0;
377
378 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
379
380 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
381
382 if (!host)
383 continue;
384
385 chipset_family = SiSHostChipInfo[i].chipset_family;
386
387 /* Special case for SiS630 : 630S/ET is ATA_100a */
388 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
389 if (host->revision >= 0x30)
390 chipset_family = ATA_100a;
391 }
392 pci_dev_put(host);
393
394 printk(KERN_INFO "SIS5513: %s %s controller\n",
395 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
396 }
397
398 if (!chipset_family) { /* Belongs to pci-quirks */
399
400 u32 idemisc;
401 u16 trueid;
402
403 /* Disable ID masking and register remapping */
404 pci_read_config_dword(dev, 0x54, &idemisc);
405 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
406 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
407 pci_write_config_dword(dev, 0x54, idemisc);
408
409 if (trueid == 0x5518) {
410 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
411 chipset_family = ATA_133;
412
413 /* Check for 5513 compability mapping
414 * We must use this, else the port enabled code will fail,
415 * as it expects the enablebits at 0x4a.
416 */
417 if ((idemisc & 0x40000000) == 0) {
418 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
419 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
420 }
421 }
422 }
423
424 if (!chipset_family) { /* Belongs to pci-quirks */
425
426 struct pci_dev *lpc_bridge;
427 u16 trueid;
428 u8 prefctl;
429 u8 idecfg;
430
431 pci_read_config_byte(dev, 0x4a, &idecfg);
432 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
433 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
434 pci_write_config_byte(dev, 0x4a, idecfg);
435
436 if (trueid == 0x5517) { /* SiS 961/961B */
437
438 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
439 pci_read_config_byte(dev, 0x49, &prefctl);
440 pci_dev_put(lpc_bridge);
441
442 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
443 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
444 chipset_family = ATA_133a;
445 } else {
446 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
447 chipset_family = ATA_100;
448 }
449 }
450 }
451
452 if (!chipset_family)
453 return -1;
454
455 /* Make general config ops here
456 1/ tell IDE channels to operate in Compatibility mode only
457 2/ tell old chips to allow per drive IDE timings */
458
459 {
460 u8 reg;
461 u16 regw;
462
463 switch(chipset_family) {
464 case ATA_133:
465 /* SiS962 operation mode */
466 pci_read_config_word(dev, 0x50, &regw);
467 if (regw & 0x08)
468 pci_write_config_word(dev, 0x50, regw&0xfff7);
469 pci_read_config_word(dev, 0x52, &regw);
470 if (regw & 0x08)
471 pci_write_config_word(dev, 0x52, regw&0xfff7);
472 break;
473 case ATA_133a:
474 case ATA_100:
475 /* Fixup latency */
476 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
477 /* Set compatibility bit */
478 pci_read_config_byte(dev, 0x49, &reg);
479 if (!(reg & 0x01)) {
480 pci_write_config_byte(dev, 0x49, reg|0x01);
481 }
482 break;
483 case ATA_100a:
484 case ATA_66:
485 /* Fixup latency */
486 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
487
488 /* On ATA_66 chips the bit was elsewhere */
489 pci_read_config_byte(dev, 0x52, &reg);
490 if (!(reg & 0x04)) {
491 pci_write_config_byte(dev, 0x52, reg|0x04);
492 }
493 break;
494 case ATA_33:
495 /* On ATA_33 we didn't have a single bit to set */
496 pci_read_config_byte(dev, 0x09, &reg);
497 if ((reg & 0x0f) != 0x00) {
498 pci_write_config_byte(dev, 0x09, reg&0xf0);
499 }
500 case ATA_16:
501 /* force per drive recovery and active timings
502 needed on ATA_33 and below chips */
503 pci_read_config_byte(dev, 0x52, &reg);
504 if (!(reg & 0x08)) {
505 pci_write_config_byte(dev, 0x52, reg|0x08);
506 }
507 break;
508 }
509 }
510
511 return 0;
512 }
513
514 struct sis_laptop {
515 u16 device;
516 u16 subvendor;
517 u16 subdevice;
518 };
519
520 static const struct sis_laptop sis_laptop[] = {
521 /* devid, subvendor, subdev */
522 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
523 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
524 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
525 /* end marker */
526 { 0, }
527 };
528
529 static u8 __devinit ata66_sis5513(ide_hwif_t *hwif)
530 {
531 struct pci_dev *pdev = to_pci_dev(hwif->dev);
532 const struct sis_laptop *lap = &sis_laptop[0];
533 u8 ata66 = 0;
534
535 while (lap->device) {
536 if (lap->device == pdev->device &&
537 lap->subvendor == pdev->subsystem_vendor &&
538 lap->subdevice == pdev->subsystem_device)
539 return ATA_CBL_PATA40_SHORT;
540 lap++;
541 }
542
543 if (chipset_family >= ATA_133) {
544 u16 regw = 0;
545 u16 reg_addr = hwif->channel ? 0x52: 0x50;
546 pci_read_config_word(pdev, reg_addr, &regw);
547 ata66 = (regw & 0x8000) ? 0 : 1;
548 } else if (chipset_family >= ATA_66) {
549 u8 reg48h = 0;
550 u8 mask = hwif->channel ? 0x20 : 0x10;
551 pci_read_config_byte(pdev, 0x48, &reg48h);
552 ata66 = (reg48h & mask) ? 0 : 1;
553 }
554
555 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
556 }
557
558 static void __devinit init_hwif_sis5513 (ide_hwif_t *hwif)
559 {
560 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
561
562 hwif->set_pio_mode = &sis_set_pio_mode;
563 hwif->set_dma_mode = &sis_set_dma_mode;
564
565 if (chipset_family >= ATA_133)
566 hwif->udma_filter = sis5513_ata133_udma_filter;
567
568 if (hwif->dma_base == 0)
569 return;
570
571 hwif->ultra_mask = udma_rates[chipset_family];
572
573 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
574 hwif->cbl = ata66_sis5513(hwif);
575 }
576
577 static const struct ide_port_info sis5513_chipset __devinitdata = {
578 .name = "SIS5513",
579 .init_chipset = init_chipset_sis5513,
580 .init_hwif = init_hwif_sis5513,
581 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
582 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA |
583 IDE_HFLAG_BOOTABLE,
584 .pio_mask = ATA_PIO4,
585 .mwdma_mask = ATA_MWDMA2,
586 };
587
588 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
589 {
590 return ide_setup_pci_device(dev, &sis5513_chipset);
591 }
592
593 static const struct pci_device_id sis5513_pci_tbl[] = {
594 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
595 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
596 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
597 { 0, },
598 };
599 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
600
601 static struct pci_driver driver = {
602 .name = "SIS_IDE",
603 .id_table = sis5513_pci_tbl,
604 .probe = sis5513_init_one,
605 };
606
607 static int __init sis5513_ide_init(void)
608 {
609 return ide_pci_register_driver(&driver);
610 }
611
612 module_init(sis5513_ide_init);
613
614 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
615 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
616 MODULE_LICENSE("GPL");
617
618 /*
619 * TODO:
620 * - CLEANUP
621 * - Use drivers/ide/ide-timing.h !
622 * - More checks in the config registers (force values instead of
623 * relying on the BIOS setting them correctly).
624 * - Further optimisations ?
625 * . for example ATA66+ regs 0x48 & 0x4A
626 */
WRT350N Kernel Patches