drivers/net/netxen/netxen_nic_hw.h

   1 /*
   2  * Copyright (C) 2003 - 2006 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen,
  26  * 3965 Freedom Circle, Fourth floor,
  27  * Santa Clara, CA 95054
  28  *
  29  *
  30  * Structures, enums, and macros for the MAC
  31  *
  32  */
  33
  34 #ifndef __NETXEN_NIC_HW_H_
  35 #define __NETXEN_NIC_HW_H_
  36
  37 #include "netxen_nic_hdr.h"
  38
  39 /* Hardware memory size of 128 meg */
  40 #define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem * addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem * addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
  58                                                u64 __iomem * addr,
  59                                                int num_words)
  60 {
  61         int num;
  62         for (num = 0; num < num_words; num++) {
  63                 writeq(readq((void __iomem *)data_ptr), addr);
  64                 addr++;
  65                 data_ptr++;
  66         }
  67 }
  68
  69 static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
  70                                               u64 __iomem * addr, int num_words)
  71 {
  72         int num;
  73         for (num = 0; num < num_words; num++) {
  74                 writeq(readq((void __iomem *)addr), data_ptr);
  75                 addr++;
  76                 data_ptr++;
  77         }
  78
  79 }
  80
  81 struct netxen_adapter;
  82
  83 #define NETXEN_PCI_MAPSIZE_BYTES  (NETXEN_PCI_MAPSIZE << 20)
  84
  85 #define NETXEN_NIC_LOCKED_READ_REG(X, Y)        \
  86         addr = pci_base_offset(adapter, X);     \
  87         *(u32 *)Y = readl((void __iomem*) addr);
  88
  89 struct netxen_port;
  90 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
  91 void netxen_nic_flash_print(struct netxen_adapter *adapter);
  92 int netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off,
  93                            void *data, int len);
  94 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
  95                                  unsigned long off, int data);
  96 int netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off,
  97                           void *data, int len);
  98
  99 typedef u8 netxen_ethernet_macaddr_t[6];
 100
 101 /* Nibble or Byte mode for phy interface (GbE mode only) */
 102 typedef enum {
 103         NETXEN_NIU_10_100_MB = 0,
 104         NETXEN_NIU_1000_MB
 105 } netxen_niu_gbe_ifmode_t;
 106
 107 #define _netxen_crb_get_bit(var, bit)  ((var >> bit) & 0x1)
 108
 109 /*
 110  * NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
 111  *
 112  *      Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
 113  *      Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
 114  *      Bit 2 : enable_rx => 1:enable frame recv, 0:disable
 115  *      Bit 3 : rx_synced => R/O: recv enable synched to recv stream
 116  *      Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
 117  *      Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
 118  *      Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
 119  *      Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
 120  *      Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
 121  *      Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
 122  *      Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
 123  *      Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
 124  */
 125
 126 #define netxen_gb_enable_tx(config_word)        \
 127         ((config_word) |= 1 << 0)
 128 #define netxen_gb_enable_rx(config_word)        \
 129         ((config_word) |= 1 << 2)
 130 #define netxen_gb_tx_flowctl(config_word)       \
 131         ((config_word) |= 1 << 4)
 132 #define netxen_gb_rx_flowctl(config_word)       \
 133         ((config_word) |= 1 << 5)
 134 #define netxen_gb_tx_reset_pb(config_word)      \
 135         ((config_word) |= 1 << 16)
 136 #define netxen_gb_rx_reset_pb(config_word)      \
 137         ((config_word) |= 1 << 17)
 138 #define netxen_gb_tx_reset_mac(config_word)     \
 139         ((config_word) |= 1 << 18)
 140 #define netxen_gb_rx_reset_mac(config_word)     \
 141         ((config_word) |= 1 << 19)
 142 #define netxen_gb_soft_reset(config_word)       \
 143         ((config_word) |= 1 << 31)
 144
 145 #define netxen_gb_unset_tx_flowctl(config_word) \
 146         ((config_word) &= ~(1 << 4))
 147 #define netxen_gb_unset_rx_flowctl(config_word) \
 148         ((config_word) &= ~(1 << 5))
 149
 150 #define netxen_gb_get_tx_synced(config_word)    \
 151                 _netxen_crb_get_bit((config_word), 1)
 152 #define netxen_gb_get_rx_synced(config_word)    \
 153                 _netxen_crb_get_bit((config_word), 3)
 154 #define netxen_gb_get_tx_flowctl(config_word)   \
 155                 _netxen_crb_get_bit((config_word), 4)
 156 #define netxen_gb_get_rx_flowctl(config_word)   \
 157                 _netxen_crb_get_bit((config_word), 5)
 158 #define netxen_gb_get_soft_reset(config_word)   \
 159                 _netxen_crb_get_bit((config_word), 31)
 160
 161 /*
 162  * NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
 163  *
 164  *      Bit 0       : duplex => 1:full duplex mode, 0:half duplex
 165  *      Bit 1       : crc_enable => 1:append CRC to xmit frames, 0:dont append
 166  *      Bit 2       : padshort => 1:pad short frames and add CRC, 0:dont pad
 167  *      Bit 4       : checklength => 1:check framelen with actual,0:dont check
 168  *      Bit 5       : hugeframes => 1:allow oversize xmit frames, 0:dont allow
 169  *      Bits 8-9    : intfmode => 01:nibble (10/100), 10:byte (1000)
 170  *      Bits 12-15  : preamblelen => preamble field length in bytes, default 7
 171  */
 172
 173 #define netxen_gb_set_duplex(config_word)       \
 174                 ((config_word) |= 1 << 0)
 175 #define netxen_gb_set_crc_enable(config_word)   \
 176                 ((config_word) |= 1 << 1)
 177 #define netxen_gb_set_padshort(config_word)     \
 178                 ((config_word) |= 1 << 2)
 179 #define netxen_gb_set_checklength(config_word)  \
 180                 ((config_word) |= 1 << 4)
 181 #define netxen_gb_set_hugeframes(config_word)   \
 182                 ((config_word) |= 1 << 5)
 183 #define netxen_gb_set_preamblelen(config_word, val)     \
 184                 ((config_word) |= ((val) << 12) & 0xF000)
 185 #define netxen_gb_set_intfmode(config_word, val)                \
 186                 ((config_word) |= ((val) << 8) & 0x300)
 187
 188 #define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
 189
 190 #define netxen_gb_set_mii_mgmt_clockselect(config_word, val)    \
 191                 ((config_word) |= ((val) & 0x07))
 192 #define netxen_gb_mii_mgmt_reset(config_word)   \
 193                 ((config_word) |= 1 << 31)
 194 #define netxen_gb_mii_mgmt_unset(config_word)   \
 195                 ((config_word) &= ~(1 << 31))
 196
 197 /*
 198  * NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
 199  * Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
 200  * Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
 201  */
 202
 203 #define netxen_gb_mii_mgmt_set_read_cycle(config_word)  \
 204                 ((config_word) |= 1 << 0)
 205 #define netxen_gb_mii_mgmt_reg_addr(config_word, val)   \
 206                 ((config_word) |= ((val) & 0x1F))
 207 #define netxen_gb_mii_mgmt_phy_addr(config_word, val)   \
 208                 ((config_word) |= (((val) & 0x1F) << 8))
 209
 210 /*
 211  * NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
 212  * Read-only register.
 213  * Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
 214  * Bit 1 : scanning => 1:scan operation in progress, 0:idle
 215  * Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
 216  */
 217 #define netxen_get_gb_mii_mgmt_busy(config_word)        \
 218                 _netxen_crb_get_bit(config_word, 0)
 219 #define netxen_get_gb_mii_mgmt_scanning(config_word)    \
 220                 _netxen_crb_get_bit(config_word, 1)
 221 #define netxen_get_gb_mii_mgmt_notvalid(config_word)    \
 222                 _netxen_crb_get_bit(config_word, 2)
 223 /*
 224  * NIU XG Pause Ctl Register
 225  *
 226  *      Bit 0       : xg0_mask => 1:disable tx pause frames
 227  *      Bit 1       : xg0_request => 1:request single pause frame
 228  *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 229  *      Bit 3       : xg1_mask => 1:disable tx pause frames
 230  *      Bit 4       : xg1_request => 1:request single pause frame
 231  *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 232  */
 233
 234 #define netxen_xg_set_xg0_mask(config_word)    \
 235         ((config_word) |= 1 << 0)
 236 #define netxen_xg_set_xg1_mask(config_word)    \
 237         ((config_word) |= 1 << 3)
 238
 239 #define netxen_xg_get_xg0_mask(config_word)    \
 240         _netxen_crb_get_bit((config_word), 0)
 241 #define netxen_xg_get_xg1_mask(config_word)    \
 242         _netxen_crb_get_bit((config_word), 3)
 243
 244 #define netxen_xg_unset_xg0_mask(config_word)  \
 245         ((config_word) &= ~(1 << 0))
 246 #define netxen_xg_unset_xg1_mask(config_word)  \
 247         ((config_word) &= ~(1 << 3))
 248
 249 /*
 250  * NIU XG Pause Ctl Register
 251  *
 252  *      Bit 0       : xg0_mask => 1:disable tx pause frames
 253  *      Bit 1       : xg0_request => 1:request single pause frame
 254  *      Bit 2       : xg0_on_off => 1:request is pause on, 0:off
 255  *      Bit 3       : xg1_mask => 1:disable tx pause frames
 256  *      Bit 4       : xg1_request => 1:request single pause frame
 257  *      Bit 5       : xg1_on_off => 1:request is pause on, 0:off
 258  */
 259 #define netxen_gb_set_gb0_mask(config_word)    \
 260         ((config_word) |= 1 << 0)
 261 #define netxen_gb_set_gb1_mask(config_word)    \
 262         ((config_word) |= 1 << 2)
 263 #define netxen_gb_set_gb2_mask(config_word)    \
 264         ((config_word) |= 1 << 4)
 265 #define netxen_gb_set_gb3_mask(config_word)    \
 266         ((config_word) |= 1 << 6)
 267
 268 #define netxen_gb_get_gb0_mask(config_word)    \
 269         _netxen_crb_get_bit((config_word), 0)
 270 #define netxen_gb_get_gb1_mask(config_word)    \
 271         _netxen_crb_get_bit((config_word), 2)
 272 #define netxen_gb_get_gb2_mask(config_word)    \
 273         _netxen_crb_get_bit((config_word), 4)
 274 #define netxen_gb_get_gb3_mask(config_word)    \
 275         _netxen_crb_get_bit((config_word), 6)
 276
 277 #define netxen_gb_unset_gb0_mask(config_word)  \
 278         ((config_word) &= ~(1 << 0))
 279 #define netxen_gb_unset_gb1_mask(config_word)  \
 280         ((config_word) &= ~(1 << 2))
 281 #define netxen_gb_unset_gb2_mask(config_word)  \
 282         ((config_word) &= ~(1 << 4))
 283 #define netxen_gb_unset_gb3_mask(config_word)  \
 284         ((config_word) &= ~(1 << 6))
 285
 286
 287 /*
 288  * PHY-Specific MII control/status registers.
 289  */
 290 typedef enum {
 291         NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
 292         NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
 293         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
 294         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
 295         NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
 296         NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
 297         NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
 298         NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
 299         NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
 300         NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
 301         NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
 302         NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
 303         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
 304         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
 305         NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
 306         NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
 307         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
 308         NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
 309         NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
 310         NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
 311         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
 312         NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
 313 } netxen_niu_phy_register_t;
 314
 315 /*
 316  * PHY-Specific Status Register (reg 17).
 317  *
 318  * Bit 0      : jabber => 1:jabber detected, 0:not
 319  * Bit 1      : polarity => 1:polarity reversed, 0:normal
 320  * Bit 2      : recvpause => 1:receive pause enabled, 0:disabled
 321  * Bit 3      : xmitpause => 1:transmit pause enabled, 0:disabled
 322  * Bit 4      : energydetect => 1:sleep, 0:active
 323  * Bit 5      : downshift => 1:downshift, 0:no downshift
 324  * Bit 6      : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
 325  * Bits 7-9   : cablelen => not valid in 10Mb/s mode
 326  *                      0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
 327  * Bit 10     : link => 1:link up, 0:link down
 328  * Bit 11     : resolved => 1:speed and duplex resolved, 0:not yet
 329  * Bit 12     : pagercvd => 1:page received, 0:page not received
 330  * Bit 13     : duplex => 1:full duplex, 0:half duplex
 331  * Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
 332  */
 333
 334 #define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
 335 #define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
 336
 337 #define netxen_set_phy_speed(config_word, val)  \
 338                 ((config_word) |= ((val & 0x03) << 14))
 339 #define netxen_set_phy_duplex(config_word)      \
 340                 ((config_word) |= 1 << 13)
 341 #define netxen_clear_phy_duplex(config_word)    \
 342                 ((config_word) &= ~(1 << 13))
 343
 344 #define netxen_get_phy_jabber(config_word)      \
 345                 _netxen_crb_get_bit(config_word, 0)
 346 #define netxen_get_phy_polarity(config_word)    \
 347                 _netxen_crb_get_bit(config_word, 1)
 348 #define netxen_get_phy_recvpause(config_word)   \
 349                 _netxen_crb_get_bit(config_word, 2)
 350 #define netxen_get_phy_xmitpause(config_word)   \
 351                 _netxen_crb_get_bit(config_word, 3)
 352 #define netxen_get_phy_energydetect(config_word) \
 353                 _netxen_crb_get_bit(config_word, 4)
 354 #define netxen_get_phy_downshift(config_word)   \
 355                 _netxen_crb_get_bit(config_word, 5)
 356 #define netxen_get_phy_crossover(config_word)   \
 357                 _netxen_crb_get_bit(config_word, 6)
 358 #define netxen_get_phy_link(config_word)        \
 359                 _netxen_crb_get_bit(config_word, 10)
 360 #define netxen_get_phy_resolved(config_word)    \
 361                 _netxen_crb_get_bit(config_word, 11)
 362 #define netxen_get_phy_pagercvd(config_word)    \
 363                 _netxen_crb_get_bit(config_word, 12)
 364 #define netxen_get_phy_duplex(config_word)      \
 365                 _netxen_crb_get_bit(config_word, 13)
 366
 367 /*
 368  * Interrupt Register definition
 369  * This definition applies to registers 18 and 19 (int enable and int status).
 370  * Bit 0 : jabber
 371  * Bit 1 : polarity_changed
 372  * Bit 4 : energy_detect
 373  * Bit 5 : downshift
 374  * Bit 6 : mdi_xover_changed
 375  * Bit 7 : fifo_over_underflow
 376  * Bit 8 : false_carrier
 377  * Bit 9 : symbol_error
 378  * Bit 10: link_status_changed
 379  * Bit 11: autoneg_completed
 380  * Bit 12: page_received
 381  * Bit 13: duplex_changed
 382  * Bit 14: speed_changed
 383  * Bit 15: autoneg_error
 384  */
 385
 386 #define netxen_get_phy_int_jabber(config_word)  \
 387                 _netxen_crb_get_bit(config_word, 0)
 388 #define netxen_get_phy_int_polarity_changed(config_word)        \
 389                 _netxen_crb_get_bit(config_word, 1)
 390 #define netxen_get_phy_int_energy_detect(config_word)   \
 391                 _netxen_crb_get_bit(config_word, 4)
 392 #define netxen_get_phy_int_downshift(config_word)       \
 393                 _netxen_crb_get_bit(config_word, 5)
 394 #define netxen_get_phy_int_mdi_xover_changed(config_word)       \
 395                 _netxen_crb_get_bit(config_word, 6)
 396 #define netxen_get_phy_int_fifo_over_underflow(config_word)     \
 397                 _netxen_crb_get_bit(config_word, 7)
 398 #define netxen_get_phy_int_false_carrier(config_word)   \
 399                 _netxen_crb_get_bit(config_word, 8)
 400 #define netxen_get_phy_int_symbol_error(config_word)    \
 401                 _netxen_crb_get_bit(config_word, 9)
 402 #define netxen_get_phy_int_link_status_changed(config_word)     \
 403                 _netxen_crb_get_bit(config_word, 10)
 404 #define netxen_get_phy_int_autoneg_completed(config_word)       \
 405                 _netxen_crb_get_bit(config_word, 11)
 406 #define netxen_get_phy_int_page_received(config_word)   \
 407                 _netxen_crb_get_bit(config_word, 12)
 408 #define netxen_get_phy_int_duplex_changed(config_word)  \
 409                 _netxen_crb_get_bit(config_word, 13)
 410 #define netxen_get_phy_int_speed_changed(config_word)   \
 411                 _netxen_crb_get_bit(config_word, 14)
 412 #define netxen_get_phy_int_autoneg_error(config_word)   \
 413                 _netxen_crb_get_bit(config_word, 15)
 414
 415 #define netxen_set_phy_int_link_status_changed(config_word)     \
 416                 ((config_word) |= 1 << 10)
 417 #define netxen_set_phy_int_autoneg_completed(config_word)       \
 418                 ((config_word) |= 1 << 11)
 419 #define netxen_set_phy_int_speed_changed(config_word)   \
 420                 ((config_word) |= 1 << 14)
 421
 422 /*
 423  * NIU Mode Register.
 424  * Bit 0 : enable FibreChannel
 425  * Bit 1 : enable 10/100/1000 Ethernet
 426  * Bit 2 : enable 10Gb Ethernet
 427  */
 428
 429 #define netxen_get_niu_enable_ge(config_word)   \
 430                 _netxen_crb_get_bit(config_word, 1)
 431
 432 /* Promiscous mode options (GbE mode only) */
 433 typedef enum {
 434         NETXEN_NIU_PROMISC_MODE = 0,
 435         NETXEN_NIU_NON_PROMISC_MODE
 436 } netxen_niu_prom_mode_t;
 437
 438 /*
 439  * NIU GB Drop CRC Register
 440  *
 441  * Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
 442  * Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
 443  * Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
 444  * Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
 445  */
 446
 447 #define netxen_set_gb_drop_gb0(config_word)     \
 448                 ((config_word) |= 1 << 0)
 449 #define netxen_set_gb_drop_gb1(config_word)     \
 450                 ((config_word) |= 1 << 1)
 451 #define netxen_set_gb_drop_gb2(config_word)     \
 452                 ((config_word) |= 1 << 2)
 453 #define netxen_set_gb_drop_gb3(config_word)     \
 454                 ((config_word) |= 1 << 3)
 455
 456 #define netxen_clear_gb_drop_gb0(config_word)   \
 457                 ((config_word) &= ~(1 << 0))
 458 #define netxen_clear_gb_drop_gb1(config_word)   \
 459                 ((config_word) &= ~(1 << 1))
 460 #define netxen_clear_gb_drop_gb2(config_word)   \
 461                 ((config_word) &= ~(1 << 2))
 462 #define netxen_clear_gb_drop_gb3(config_word)   \
 463                 ((config_word) &= ~(1 << 3))
 464
 465 /*
 466  * NIU XG MAC Config Register
 467  *
 468  * Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
 469  * Bit 2 : rx_enable => 1:enable frame recv, 0:disable
 470  * Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
 471  * Bit 27: xaui_framer_reset
 472  * Bit 28: xaui_rx_reset
 473  * Bit 29: xaui_tx_reset
 474  * Bit 30: xg_ingress_afifo_reset
 475  * Bit 31: xg_egress_afifo_reset
 476  */
 477
 478 #define netxen_xg_soft_reset(config_word)       \
 479                 ((config_word) |= 1 << 4)
 480
 481 /*
 482  * MAC Control Register
 483  *
 484  * Bit 0-1   : id_pool0
 485  * Bit 2     : enable_xtnd0
 486  * Bit 4-5   : id_pool1
 487  * Bit 6     : enable_xtnd1
 488  * Bit 8-9   : id_pool2
 489  * Bit 10    : enable_xtnd2
 490  * Bit 12-13 : id_pool3
 491  * Bit 14    : enable_xtnd3
 492  * Bit 24-25 : mode_select
 493  * Bit 28-31 : enable_pool
 494  */
 495
 496 #define netxen_nic_mcr_set_id_pool0(config, val)        \
 497                 ((config) |= ((val) &0x03))
 498 #define netxen_nic_mcr_set_enable_xtnd0(config) \
 499                 ((config) |= 1 << 3)
 500 #define netxen_nic_mcr_set_id_pool1(config, val)        \
 501                 ((config) |= (((val) & 0x03) << 4))
 502 #define netxen_nic_mcr_set_enable_xtnd1(config) \
 503                 ((config) |= 1 << 6)
 504 #define netxen_nic_mcr_set_id_pool2(config, val)        \
 505                 ((config) |= (((val) & 0x03) << 8))
 506 #define netxen_nic_mcr_set_enable_xtnd2(config) \
 507                 ((config) |= 1 << 10)
 508 #define netxen_nic_mcr_set_id_pool3(config, val)        \
 509                 ((config) |= (((val) & 0x03) << 12))
 510 #define netxen_nic_mcr_set_enable_xtnd3(config) \
 511                 ((config) |= 1 << 14)
 512 #define netxen_nic_mcr_set_mode_select(config, val)     \
 513                 ((config) |= (((val) & 0x03) << 24))
 514 #define netxen_nic_mcr_set_enable_pool(config, val)     \
 515                 ((config) |= (((val) & 0x0f) << 28))
 516
 517 /* Set promiscuous mode for a GbE interface */
 518 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
 519                                     netxen_niu_prom_mode_t mode);
 520 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
 521                                        netxen_niu_prom_mode_t mode);
 522
 523 /* set the MAC address for a given MAC */
 524 int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
 525                            netxen_ethernet_macaddr_t addr);
 526
 527 /* XG version */
 528 int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
 529                               netxen_ethernet_macaddr_t addr);
 530
 531 /* Generic enable for GbE ports. Will detect the speed of the link. */
 532 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
 533
 534 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
 535
 536 /* Disable a GbE interface */
 537 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
 538
 539 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
 540
 541 #endif                          /* __NETXEN_NIC_HW_H_ */