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x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / net / pci-skeleton.c
blobed402e00e730e1c0c2eadfa1ac13a5cfe3cb9aa9
1 /*
2
3 drivers/net/pci-skeleton.c
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6
7 Original code came from 8139too.c, which in turns was based
8 originally on Donald Becker's rtl8139.c driver, versions 1.11
9 and older. This driver was originally based on rtl8139.c
10 version 1.07. Header of rtl8139.c version 1.11:
11
12 -----<snip>-----
13
14 Written 1997-2000 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41
42 -----------------------------------------------------------------------------
43
44 Theory of Operation
45
46 I. Board Compatibility
47
48 This device driver is designed for the RealTek RTL8139 series, the RealTek
49 Fast Ethernet controllers for PCI and CardBus. This chip is used on many
50 low-end boards, sometimes with its markings changed.
51
52
53 II. Board-specific settings
54
55 PCI bus devices are configured by the system at boot time, so no jumpers
56 need to be set on the board. The system BIOS will assign the
57 PCI INTA signal to a (preferably otherwise unused) system IRQ line.
58
59 III. Driver operation
60
61 IIIa. Rx Ring buffers
62
63 The receive unit uses a single linear ring buffer rather than the more
64 common (and more efficient) descriptor-based architecture. Incoming frames
65 are sequentially stored into the Rx region, and the host copies them into
66 skbuffs.
67
68 Comment: While it is theoretically possible to process many frames in place,
69 any delay in Rx processing would cause us to drop frames. More importantly,
70 the Linux protocol stack is not designed to operate in this manner.
71
72 IIIb. Tx operation
73
74 The RTL8139 uses a fixed set of four Tx descriptors in register space.
75 In a stunningly bad design choice, Tx frames must be 32 bit aligned. Linux
76 aligns the IP header on word boundaries, and 14 byte ethernet header means
77 that almost all frames will need to be copied to an alignment buffer.
78
79 IVb. References
80
81 http://www.realtek.com.tw/cn/cn.html
82 http://www.scyld.com/expert/NWay.html
83
84 IVc. Errata
85
86 */
87
88 #include <linux/module.h>
89 #include <linux/kernel.h>
90 #include <linux/pci.h>
91 #include <linux/init.h>
92 #include <linux/ioport.h>
93 #include <linux/netdevice.h>
94 #include <linux/etherdevice.h>
95 #include <linux/delay.h>
96 #include <linux/ethtool.h>
97 #include <linux/mii.h>
98 #include <linux/crc32.h>
99 #include <asm/io.h>
100
101 #define NETDRV_VERSION "1.0.1"
102 #define MODNAME "netdrv"
103 #define NETDRV_DRIVER_LOAD_MSG "MyVendor Fast Ethernet driver " NETDRV_VERSION " loaded"
104 #define PFX MODNAME ": "
105
106 static char version[] __devinitdata =
107 KERN_INFO NETDRV_DRIVER_LOAD_MSG "\n"
108 KERN_INFO " Support available from http://foo.com/bar/baz.html\n";
109
110 /* define to 1 to enable PIO instead of MMIO */
111 #undef USE_IO_OPS
112
113 /* define to 1 to enable copious debugging info */
114 #undef NETDRV_DEBUG
115
116 /* define to 1 to disable lightweight runtime debugging checks */
117 #undef NETDRV_NDEBUG
118
119
120 #ifdef NETDRV_DEBUG
121 /* note: prints function name for you */
122 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
123 #else
124 # define DPRINTK(fmt, args...)
125 #endif
126
127 #ifdef NETDRV_NDEBUG
128 # define assert(expr) do {} while (0)
129 #else
130 # define assert(expr) \
131 if(!(expr)) { \
132 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
133 #expr,__FILE__,__FUNCTION__,__LINE__); \
134 }
135 #endif
136
137
138 /* A few user-configurable values. */
139 /* media options */
140 static int media[] = {-1, -1, -1, -1, -1, -1, -1, -1};
141
142 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
143 static int max_interrupt_work = 20;
144
145 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
146 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
147 static int multicast_filter_limit = 32;
148
149 /* Size of the in-memory receive ring. */
150 #define RX_BUF_LEN_IDX 2 /* 0==8K, 1==16K, 2==32K, 3==64K */
151 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
152 #define RX_BUF_PAD 16
153 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
154 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
155
156 /* Number of Tx descriptor registers. */
157 #define NUM_TX_DESC 4
158
159 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
160 #define MAX_ETH_FRAME_SIZE 1536
161
162 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
163 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
164 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
165
166 /* PCI Tuning Parameters
167 Threshold is bytes transferred to chip before transmission starts. */
168 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
169
170 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
171 #define RX_FIFO_THRESH 6 /* Rx buffer level before first PCI xfer. */
172 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
173 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
174
175
176 /* Operational parameters that usually are not changed. */
177 /* Time in jiffies before concluding the transmitter is hung. */
178 #define TX_TIMEOUT (6*HZ)
179
180
181 enum {
182 HAS_CHIP_XCVR = 0x020000,
183 HAS_LNK_CHNG = 0x040000,
184 };
185
186 #define NETDRV_MIN_IO_SIZE 0x80
187 #define RTL8139B_IO_SIZE 256
188
189 #define NETDRV_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
190
191 typedef enum {
192 RTL8139 = 0,
193 NETDRV_CB,
194 SMC1211TX,
195 /*MPX5030,*/
196 DELTA8139,
197 ADDTRON8139,
198 } board_t;
199
200
201 /* indexed by board_t, above */
202 static struct {
203 const char *name;
204 } board_info[] __devinitdata = {
205 { "RealTek RTL8139 Fast Ethernet" },
206 { "RealTek RTL8139B PCI/CardBus" },
207 { "SMC1211TX EZCard 10/100 (RealTek RTL8139)" },
208 /* { MPX5030, "Accton MPX5030 (RealTek RTL8139)" },*/
209 { "Delta Electronics 8139 10/100BaseTX" },
210 { "Addtron Technolgy 8139 10/100BaseTX" },
211 };
212
213
214 static struct pci_device_id netdrv_pci_tbl[] = {
215 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
216 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, NETDRV_CB },
217 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
218 /* {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
219 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
220 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
221 {0,}
222 };
223 MODULE_DEVICE_TABLE (pci, netdrv_pci_tbl);
224
225
226 /* The rest of these values should never change. */
227
228 /* Symbolic offsets to registers. */
229 enum NETDRV_registers {
230 MAC0 = 0, /* Ethernet hardware address. */
231 MAR0 = 8, /* Multicast filter. */
232 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
233 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
234 RxBuf = 0x30,
235 RxEarlyCnt = 0x34,
236 RxEarlyStatus = 0x36,
237 ChipCmd = 0x37,
238 RxBufPtr = 0x38,
239 RxBufAddr = 0x3A,
240 IntrMask = 0x3C,
241 IntrStatus = 0x3E,
242 TxConfig = 0x40,
243 ChipVersion = 0x43,
244 RxConfig = 0x44,
245 Timer = 0x48, /* A general-purpose counter. */
246 RxMissed = 0x4C, /* 24 bits valid, write clears. */
247 Cfg9346 = 0x50,
248 Config0 = 0x51,
249 Config1 = 0x52,
250 FlashReg = 0x54,
251 MediaStatus = 0x58,
252 Config3 = 0x59,
253 Config4 = 0x5A, /* absent on RTL-8139A */
254 HltClk = 0x5B,
255 MultiIntr = 0x5C,
256 TxSummary = 0x60,
257 BasicModeCtrl = 0x62,
258 BasicModeStatus = 0x64,
259 NWayAdvert = 0x66,
260 NWayLPAR = 0x68,
261 NWayExpansion = 0x6A,
262 /* Undocumented registers, but required for proper operation. */
263 FIFOTMS = 0x70, /* FIFO Control and test. */
264 CSCR = 0x74, /* Chip Status and Configuration Register. */
265 PARA78 = 0x78,
266 PARA7c = 0x7c, /* Magic transceiver parameter register. */
267 Config5 = 0xD8, /* absent on RTL-8139A */
268 };
269
270 enum ClearBitMasks {
271 MultiIntrClear = 0xF000,
272 ChipCmdClear = 0xE2,
273 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
274 };
275
276 enum ChipCmdBits {
277 CmdReset = 0x10,
278 CmdRxEnb = 0x08,
279 CmdTxEnb = 0x04,
280 RxBufEmpty = 0x01,
281 };
282
283 /* Interrupt register bits, using my own meaningful names. */
284 enum IntrStatusBits {
285 PCIErr = 0x8000,
286 PCSTimeout = 0x4000,
287 RxFIFOOver = 0x40,
288 RxUnderrun = 0x20,
289 RxOverflow = 0x10,
290 TxErr = 0x08,
291 TxOK = 0x04,
292 RxErr = 0x02,
293 RxOK = 0x01,
294 };
295 enum TxStatusBits {
296 TxHostOwns = 0x2000,
297 TxUnderrun = 0x4000,
298 TxStatOK = 0x8000,
299 TxOutOfWindow = 0x20000000,
300 TxAborted = 0x40000000,
301 TxCarrierLost = 0x80000000,
302 };
303 enum RxStatusBits {
304 RxMulticast = 0x8000,
305 RxPhysical = 0x4000,
306 RxBroadcast = 0x2000,
307 RxBadSymbol = 0x0020,
308 RxRunt = 0x0010,
309 RxTooLong = 0x0008,
310 RxCRCErr = 0x0004,
311 RxBadAlign = 0x0002,
312 RxStatusOK = 0x0001,
313 };
314
315 /* Bits in RxConfig. */
316 enum rx_mode_bits {
317 AcceptErr = 0x20,
318 AcceptRunt = 0x10,
319 AcceptBroadcast = 0x08,
320 AcceptMulticast = 0x04,
321 AcceptMyPhys = 0x02,
322 AcceptAllPhys = 0x01,
323 };
324
325 /* Bits in TxConfig. */
326 enum tx_config_bits {
327 TxIFG1 = (1 << 25), /* Interframe Gap Time */
328 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
329 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
330 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
331 TxClearAbt = (1 << 0), /* Clear abort (WO) */
332 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
333
334 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
335 };
336
337 /* Bits in Config1 */
338 enum Config1Bits {
339 Cfg1_PM_Enable = 0x01,
340 Cfg1_VPD_Enable = 0x02,
341 Cfg1_PIO = 0x04,
342 Cfg1_MMIO = 0x08,
343 Cfg1_LWAKE = 0x10,
344 Cfg1_Driver_Load = 0x20,
345 Cfg1_LED0 = 0x40,
346 Cfg1_LED1 = 0x80,
347 };
348
349 enum RxConfigBits {
350 /* Early Rx threshold, none or X/16 */
351 RxCfgEarlyRxNone = 0,
352 RxCfgEarlyRxShift = 24,
353
354 /* rx fifo threshold */
355 RxCfgFIFOShift = 13,
356 RxCfgFIFONone = (7 << RxCfgFIFOShift),
357
358 /* Max DMA burst */
359 RxCfgDMAShift = 8,
360 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
361
362 /* rx ring buffer length */
363 RxCfgRcv8K = 0,
364 RxCfgRcv16K = (1 << 11),
365 RxCfgRcv32K = (1 << 12),
366 RxCfgRcv64K = (1 << 11) | (1 << 12),
367
368 /* Disable packet wrap at end of Rx buffer */
369 RxNoWrap = (1 << 7),
370 };
371
372
373 /* Twister tuning parameters from RealTek.
374 Completely undocumented, but required to tune bad links. */
375 enum CSCRBits {
376 CSCR_LinkOKBit = 0x0400,
377 CSCR_LinkChangeBit = 0x0800,
378 CSCR_LinkStatusBits = 0x0f000,
379 CSCR_LinkDownOffCmd = 0x003c0,
380 CSCR_LinkDownCmd = 0x0f3c0,
381 };
382
383
384 enum Cfg9346Bits {
385 Cfg9346_Lock = 0x00,
386 Cfg9346_Unlock = 0xC0,
387 };
388
389
390 #define PARA78_default 0x78fa8388
391 #define PARA7c_default 0xcb38de43 /* param[0][3] */
392 #define PARA7c_xxx 0xcb38de43
393 static const unsigned long param[4][4] = {
394 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
395 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
396 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
397 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
398 };
399
400 struct ring_info {
401 struct sk_buff *skb;
402 dma_addr_t mapping;
403 };
404
405
406 typedef enum {
407 CH_8139 = 0,
408 CH_8139_K,
409 CH_8139A,
410 CH_8139B,
411 CH_8130,
412 CH_8139C,
413 } chip_t;
414
415
416 /* directly indexed by chip_t, above */
417 static const struct {
418 const char *name;
419 u8 version; /* from RTL8139C docs */
420 u32 RxConfigMask; /* should clear the bits supported by this chip */
421 } rtl_chip_info[] = {
422 { "RTL-8139",
423 0x40,
424 0xf0fe0040, /* XXX copied from RTL8139A, verify */
425 },
426
427 { "RTL-8139 rev K",
428 0x60,
429 0xf0fe0040,
430 },
431
432 { "RTL-8139A",
433 0x70,
434 0xf0fe0040,
435 },
436
437 { "RTL-8139B",
438 0x78,
439 0xf0fc0040
440 },
441
442 { "RTL-8130",
443 0x7C,
444 0xf0fe0040, /* XXX copied from RTL8139A, verify */
445 },
446
447 { "RTL-8139C",
448 0x74,
449 0xf0fc0040, /* XXX copied from RTL8139B, verify */
450 },
451
452 };
453
454
455 struct netdrv_private {
456 board_t board;
457 void *mmio_addr;
458 int drv_flags;
459 struct pci_dev *pci_dev;
460 struct timer_list timer; /* Media selection timer. */
461 unsigned char *rx_ring;
462 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
463 unsigned int tx_flag;
464 atomic_t cur_tx;
465 atomic_t dirty_tx;
466 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
467 struct ring_info tx_info[NUM_TX_DESC];
468 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
469 unsigned char *tx_bufs; /* Tx bounce buffer region. */
470 dma_addr_t rx_ring_dma;
471 dma_addr_t tx_bufs_dma;
472 char phys[4]; /* MII device addresses. */
473 char twistie, twist_row, twist_col; /* Twister tune state. */
474 unsigned int full_duplex:1; /* Full-duplex operation requested. */
475 unsigned int duplex_lock:1;
476 unsigned int default_port:4; /* Last dev->if_port value. */
477 unsigned int media2:4; /* Secondary monitored media port. */
478 unsigned int medialock:1; /* Don't sense media type. */
479 unsigned int mediasense:1; /* Media sensing in progress. */
480 spinlock_t lock;
481 chip_t chipset;
482 };
483
484 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
485 MODULE_DESCRIPTION ("Skeleton for a PCI Fast Ethernet driver");
486 MODULE_LICENSE("GPL");
487 module_param(multicast_filter_limit, int, 0);
488 module_param(max_interrupt_work, int, 0);
489 module_param_array(media, int, NULL, 0);
490 MODULE_PARM_DESC (multicast_filter_limit, "pci-skeleton maximum number of filtered multicast addresses");
491 MODULE_PARM_DESC (max_interrupt_work, "pci-skeleton maximum events handled per interrupt");
492 MODULE_PARM_DESC (media, "pci-skeleton: Bits 0-3: media type, bit 17: full duplex");
493
494 static int read_eeprom (void *ioaddr, int location, int addr_len);
495 static int netdrv_open (struct net_device *dev);
496 static int mdio_read (struct net_device *dev, int phy_id, int location);
497 static void mdio_write (struct net_device *dev, int phy_id, int location,
498 int val);
499 static void netdrv_timer (unsigned long data);
500 static void netdrv_tx_timeout (struct net_device *dev);
501 static void netdrv_init_ring (struct net_device *dev);
502 static int netdrv_start_xmit (struct sk_buff *skb,
503 struct net_device *dev);
504 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance);
505 static int netdrv_close (struct net_device *dev);
506 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
507 static void netdrv_set_rx_mode (struct net_device *dev);
508 static void netdrv_hw_start (struct net_device *dev);
509
510
511 #ifdef USE_IO_OPS
512
513 #define NETDRV_R8(reg) inb (((unsigned long)ioaddr) + (reg))
514 #define NETDRV_R16(reg) inw (((unsigned long)ioaddr) + (reg))
515 #define NETDRV_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
516 #define NETDRV_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
517 #define NETDRV_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
518 #define NETDRV_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
519 #define NETDRV_W8_F NETDRV_W8
520 #define NETDRV_W16_F NETDRV_W16
521 #define NETDRV_W32_F NETDRV_W32
522 #undef readb
523 #undef readw
524 #undef readl
525 #undef writeb
526 #undef writew
527 #undef writel
528 #define readb(addr) inb((unsigned long)(addr))
529 #define readw(addr) inw((unsigned long)(addr))
530 #define readl(addr) inl((unsigned long)(addr))
531 #define writeb(val,addr) outb((val),(unsigned long)(addr))
532 #define writew(val,addr) outw((val),(unsigned long)(addr))
533 #define writel(val,addr) outl((val),(unsigned long)(addr))
534
535 #else
536
537 /* write MMIO register, with flush */
538 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
539 #define NETDRV_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
540 #define NETDRV_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
541 #define NETDRV_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
542
543
544 #if MMIO_FLUSH_AUDIT_COMPLETE
545
546 /* write MMIO register */
547 #define NETDRV_W8(reg, val8) writeb ((val8), ioaddr + (reg))
548 #define NETDRV_W16(reg, val16) writew ((val16), ioaddr + (reg))
549 #define NETDRV_W32(reg, val32) writel ((val32), ioaddr + (reg))
550
551 #else
552
553 /* write MMIO register, then flush */
554 #define NETDRV_W8 NETDRV_W8_F
555 #define NETDRV_W16 NETDRV_W16_F
556 #define NETDRV_W32 NETDRV_W32_F
557
558 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
559
560 /* read MMIO register */
561 #define NETDRV_R8(reg) readb (ioaddr + (reg))
562 #define NETDRV_R16(reg) readw (ioaddr + (reg))
563 #define NETDRV_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
564
565 #endif /* USE_IO_OPS */
566
567
568 static const u16 netdrv_intr_mask =
569 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
570 TxErr | TxOK | RxErr | RxOK;
571
572 static const unsigned int netdrv_rx_config =
573 RxCfgEarlyRxNone | RxCfgRcv32K | RxNoWrap |
574 (RX_FIFO_THRESH << RxCfgFIFOShift) |
575 (RX_DMA_BURST << RxCfgDMAShift);
576
577
578 static int __devinit netdrv_init_board (struct pci_dev *pdev,
579 struct net_device **dev_out,
580 void **ioaddr_out)
581 {
582 void *ioaddr = NULL;
583 struct net_device *dev;
584 struct netdrv_private *tp;
585 int rc, i;
586 u32 pio_start, pio_end, pio_flags, pio_len;
587 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
588 u32 tmp;
589
590 DPRINTK ("ENTER\n");
591
592 assert (pdev != NULL);
593 assert (ioaddr_out != NULL);
594
595 *ioaddr_out = NULL;
596 *dev_out = NULL;
597
598 /* dev zeroed in alloc_etherdev */
599 dev = alloc_etherdev (sizeof (*tp));
600 if (dev == NULL) {
601 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
602 DPRINTK ("EXIT, returning -ENOMEM\n");
603 return -ENOMEM;
604 }
605 SET_NETDEV_DEV(dev, &pdev->dev);
606 tp = dev->priv;
607
608 /* enable device (incl. PCI PM wakeup), and bus-mastering */
609 rc = pci_enable_device (pdev);
610 if (rc)
611 goto err_out;
612
613 pio_start = pci_resource_start (pdev, 0);
614 pio_end = pci_resource_end (pdev, 0);
615 pio_flags = pci_resource_flags (pdev, 0);
616 pio_len = pci_resource_len (pdev, 0);
617
618 mmio_start = pci_resource_start (pdev, 1);
619 mmio_end = pci_resource_end (pdev, 1);
620 mmio_flags = pci_resource_flags (pdev, 1);
621 mmio_len = pci_resource_len (pdev, 1);
622
623 /* set this immediately, we need to know before
624 * we talk to the chip directly */
625 DPRINTK("PIO region size == 0x%02X\n", pio_len);
626 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
627
628 /* make sure PCI base addr 0 is PIO */
629 if (!(pio_flags & IORESOURCE_IO)) {
630 dev_err(&pdev->dev, "region #0 not a PIO resource, aborting\n");
631 rc = -ENODEV;
632 goto err_out;
633 }
634
635 /* make sure PCI base addr 1 is MMIO */
636 if (!(mmio_flags & IORESOURCE_MEM)) {
637 dev_err(&pdev->dev, "region #1 not an MMIO resource, aborting\n");
638 rc = -ENODEV;
639 goto err_out;
640 }
641
642 /* check for weird/broken PCI region reporting */
643 if ((pio_len < NETDRV_MIN_IO_SIZE) ||
644 (mmio_len < NETDRV_MIN_IO_SIZE)) {
645 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
646 rc = -ENODEV;
647 goto err_out;
648 }
649
650 rc = pci_request_regions (pdev, MODNAME);
651 if (rc)
652 goto err_out;
653
654 pci_set_master (pdev);
655
656 #ifdef USE_IO_OPS
657 ioaddr = (void *) pio_start;
658 #else
659 /* ioremap MMIO region */
660 ioaddr = ioremap (mmio_start, mmio_len);
661 if (ioaddr == NULL) {
662 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
663 rc = -EIO;
664 goto err_out_free_res;
665 }
666 #endif /* USE_IO_OPS */
667
668 /* Soft reset the chip. */
669 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
670
671 /* Check that the chip has finished the reset. */
672 for (i = 1000; i > 0; i--)
673 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
674 break;
675 else
676 udelay (10);
677
678 /* Bring the chip out of low-power mode. */
679 /* <insert device-specific code here> */
680
681 #ifndef USE_IO_OPS
682 /* sanity checks -- ensure PIO and MMIO registers agree */
683 assert (inb (pio_start+Config0) == readb (ioaddr+Config0));
684 assert (inb (pio_start+Config1) == readb (ioaddr+Config1));
685 assert (inb (pio_start+TxConfig) == readb (ioaddr+TxConfig));
686 assert (inb (pio_start+RxConfig) == readb (ioaddr+RxConfig));
687 #endif /* !USE_IO_OPS */
688
689 /* identify chip attached to board */
690 tmp = NETDRV_R8 (ChipVersion);
691 for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--)
692 if (tmp == rtl_chip_info[i].version) {
693 tp->chipset = i;
694 goto match;
695 }
696
697 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
698 dev_printk (KERN_DEBUG, &pdev->dev,
699 "unknown chip version, assuming RTL-8139\n");
700 dev_printk (KERN_DEBUG, &pdev->dev, "TxConfig = 0x%lx\n",
701 NETDRV_R32 (TxConfig));
702 tp->chipset = 0;
703
704 match:
705 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
706 tmp,
707 tp->chipset,
708 rtl_chip_info[tp->chipset].name);
709
710 rc = register_netdev (dev);
711 if (rc)
712 goto err_out_unmap;
713
714 DPRINTK ("EXIT, returning 0\n");
715 *ioaddr_out = ioaddr;
716 *dev_out = dev;
717 return 0;
718
719 err_out_unmap:
720 #ifndef USE_IO_OPS
721 iounmap(ioaddr);
722 err_out_free_res:
723 #endif
724 pci_release_regions (pdev);
725 err_out:
726 free_netdev (dev);
727 DPRINTK ("EXIT, returning %d\n", rc);
728 return rc;
729 }
730
731
732 static int __devinit netdrv_init_one (struct pci_dev *pdev,
733 const struct pci_device_id *ent)
734 {
735 struct net_device *dev = NULL;
736 struct netdrv_private *tp;
737 int i, addr_len, option;
738 void *ioaddr = NULL;
739 static int board_idx = -1;
740 DECLARE_MAC_BUF(mac);
741
742 /* when built into the kernel, we only print version if device is found */
743 #ifndef MODULE
744 static int printed_version;
745 if (!printed_version++)
746 printk(version);
747 #endif
748
749 DPRINTK ("ENTER\n");
750
751 assert (pdev != NULL);
752 assert (ent != NULL);
753
754 board_idx++;
755
756 i = netdrv_init_board (pdev, &dev, &ioaddr);
757 if (i < 0) {
758 DPRINTK ("EXIT, returning %d\n", i);
759 return i;
760 }
761
762 tp = dev->priv;
763
764 assert (ioaddr != NULL);
765 assert (dev != NULL);
766 assert (tp != NULL);
767
768 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
769 for (i = 0; i < 3; i++)
770 ((u16 *) (dev->dev_addr))[i] =
771 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
772
773 /* The Rtl8139-specific entries in the device structure. */
774 dev->open = netdrv_open;
775 dev->hard_start_xmit = netdrv_start_xmit;
776 dev->stop = netdrv_close;
777 dev->set_multicast_list = netdrv_set_rx_mode;
778 dev->do_ioctl = netdrv_ioctl;
779 dev->tx_timeout = netdrv_tx_timeout;
780 dev->watchdog_timeo = TX_TIMEOUT;
781
782 dev->irq = pdev->irq;
783 dev->base_addr = (unsigned long) ioaddr;
784
785 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
786 tp = dev->priv;
787
788 /* note: tp->chipset set in netdrv_init_board */
789 tp->drv_flags = PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
790 PCI_COMMAND_MASTER | NETDRV_CAPS;
791 tp->pci_dev = pdev;
792 tp->board = ent->driver_data;
793 tp->mmio_addr = ioaddr;
794 spin_lock_init(&tp->lock);
795
796 pci_set_drvdata(pdev, dev);
797
798 tp->phys[0] = 32;
799
800 printk (KERN_INFO "%s: %s at 0x%lx, %sIRQ %d\n",
801 dev->name,
802 board_info[ent->driver_data].name,
803 dev->base_addr,
804 print_mac(mac, dev->dev_addr),
805 dev->irq);
806
807 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
808 dev->name, rtl_chip_info[tp->chipset].name);
809
810 /* Put the chip into low-power mode. */
811 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
812
813 /* The lower four bits are the media type. */
814 option = (board_idx > 7) ? 0 : media[board_idx];
815 if (option > 0) {
816 tp->full_duplex = (option & 0x200) ? 1 : 0;
817 tp->default_port = option & 15;
818 if (tp->default_port)
819 tp->medialock = 1;
820 }
821
822 if (tp->full_duplex) {
823 printk (KERN_INFO
824 "%s: Media type forced to Full Duplex.\n",
825 dev->name);
826 mdio_write (dev, tp->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
827 tp->duplex_lock = 1;
828 }
829
830 DPRINTK ("EXIT - returning 0\n");
831 return 0;
832 }
833
834
835 static void __devexit netdrv_remove_one (struct pci_dev *pdev)
836 {
837 struct net_device *dev = pci_get_drvdata (pdev);
838 struct netdrv_private *np;
839
840 DPRINTK ("ENTER\n");
841
842 assert (dev != NULL);
843
844 np = dev->priv;
845 assert (np != NULL);
846
847 unregister_netdev (dev);
848
849 #ifndef USE_IO_OPS
850 iounmap (np->mmio_addr);
851 #endif /* !USE_IO_OPS */
852
853 pci_release_regions (pdev);
854
855 free_netdev (dev);
856
857 pci_set_drvdata (pdev, NULL);
858
859 pci_disable_device (pdev);
860
861 DPRINTK ("EXIT\n");
862 }
863
864
865 /* Serial EEPROM section. */
866
867 /* EEPROM_Ctrl bits. */
868 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
869 #define EE_CS 0x08 /* EEPROM chip select. */
870 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
871 #define EE_WRITE_0 0x00
872 #define EE_WRITE_1 0x02
873 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
874 #define EE_ENB (0x80 | EE_CS)
875
876 /* Delay between EEPROM clock transitions.
877 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
878 */
879
880 #define eeprom_delay() readl(ee_addr)
881
882 /* The EEPROM commands include the alway-set leading bit. */
883 #define EE_WRITE_CMD (5)
884 #define EE_READ_CMD (6)
885 #define EE_ERASE_CMD (7)
886
887 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
888 {
889 int i;
890 unsigned retval = 0;
891 void *ee_addr = ioaddr + Cfg9346;
892 int read_cmd = location | (EE_READ_CMD << addr_len);
893
894 DPRINTK ("ENTER\n");
895
896 writeb (EE_ENB & ~EE_CS, ee_addr);
897 writeb (EE_ENB, ee_addr);
898 eeprom_delay ();
899
900 /* Shift the read command bits out. */
901 for (i = 4 + addr_len; i >= 0; i--) {
902 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
903 writeb (EE_ENB | dataval, ee_addr);
904 eeprom_delay ();
905 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
906 eeprom_delay ();
907 }
908 writeb (EE_ENB, ee_addr);
909 eeprom_delay ();
910
911 for (i = 16; i > 0; i--) {
912 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
913 eeprom_delay ();
914 retval =
915 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
916 0);
917 writeb (EE_ENB, ee_addr);
918 eeprom_delay ();
919 }
920
921 /* Terminate the EEPROM access. */
922 writeb (~EE_CS, ee_addr);
923 eeprom_delay ();
924
925 DPRINTK ("EXIT - returning %d\n", retval);
926 return retval;
927 }
928
929 /* MII serial management: mostly bogus for now. */
930 /* Read and write the MII management registers using software-generated
931 serial MDIO protocol.
932 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
933 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
934 "overclocking" issues. */
935 #define MDIO_DIR 0x80
936 #define MDIO_DATA_OUT 0x04
937 #define MDIO_DATA_IN 0x02
938 #define MDIO_CLK 0x01
939 #define MDIO_WRITE0 (MDIO_DIR)
940 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
941
942 #define mdio_delay() readb(mdio_addr)
943
944
945 static char mii_2_8139_map[8] = {
946 BasicModeCtrl,
947 BasicModeStatus,
948 0,
949 0,
950 NWayAdvert,
951 NWayLPAR,
952 NWayExpansion,
953 0
954 };
955
956
957 /* Syncronize the MII management interface by shifting 32 one bits out. */
958 static void mdio_sync (void *mdio_addr)
959 {
960 int i;
961
962 DPRINTK ("ENTER\n");
963
964 for (i = 32; i >= 0; i--) {
965 writeb (MDIO_WRITE1, mdio_addr);
966 mdio_delay ();
967 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
968 mdio_delay ();
969 }
970
971 DPRINTK ("EXIT\n");
972 }
973
974
975 static int mdio_read (struct net_device *dev, int phy_id, int location)
976 {
977 struct netdrv_private *tp = dev->priv;
978 void *mdio_addr = tp->mmio_addr + Config4;
979 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
980 int retval = 0;
981 int i;
982
983 DPRINTK ("ENTER\n");
984
985 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
986 DPRINTK ("EXIT after directly using 8139 internal regs\n");
987 return location < 8 && mii_2_8139_map[location] ?
988 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
989 }
990 mdio_sync (mdio_addr);
991 /* Shift the read command bits out. */
992 for (i = 15; i >= 0; i--) {
993 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
994
995 writeb (MDIO_DIR | dataval, mdio_addr);
996 mdio_delay ();
997 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
998 mdio_delay ();
999 }
1000
1001 /* Read the two transition, 16 data, and wire-idle bits. */
1002 for (i = 19; i > 0; i--) {
1003 writeb (0, mdio_addr);
1004 mdio_delay ();
1005 retval =
1006 (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1
1007 : 0);
1008 writeb (MDIO_CLK, mdio_addr);
1009 mdio_delay ();
1010 }
1011
1012 DPRINTK ("EXIT, returning %d\n", (retval >> 1) & 0xffff);
1013 return (retval >> 1) & 0xffff;
1014 }
1015
1016
1017 static void mdio_write (struct net_device *dev, int phy_id, int location,
1018 int value)
1019 {
1020 struct netdrv_private *tp = dev->priv;
1021 void *mdio_addr = tp->mmio_addr + Config4;
1022 int mii_cmd =
1023 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1024 int i;
1025
1026 DPRINTK ("ENTER\n");
1027
1028 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1029 if (location < 8 && mii_2_8139_map[location]) {
1030 writew (value,
1031 tp->mmio_addr + mii_2_8139_map[location]);
1032 readw (tp->mmio_addr + mii_2_8139_map[location]);
1033 }
1034 DPRINTK ("EXIT after directly using 8139 internal regs\n");
1035 return;
1036 }
1037 mdio_sync (mdio_addr);
1038
1039 /* Shift the command bits out. */
1040 for (i = 31; i >= 0; i--) {
1041 int dataval =
1042 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1043 writeb (dataval, mdio_addr);
1044 mdio_delay ();
1045 writeb (dataval | MDIO_CLK, mdio_addr);
1046 mdio_delay ();
1047 }
1048
1049 /* Clear out extra bits. */
1050 for (i = 2; i > 0; i--) {
1051 writeb (0, mdio_addr);
1052 mdio_delay ();
1053 writeb (MDIO_CLK, mdio_addr);
1054 mdio_delay ();
1055 }
1056
1057 DPRINTK ("EXIT\n");
1058 }
1059
1060
1061 static int netdrv_open (struct net_device *dev)
1062 {
1063 struct netdrv_private *tp = dev->priv;
1064 int retval;
1065 #ifdef NETDRV_DEBUG
1066 void *ioaddr = tp->mmio_addr;
1067 #endif
1068
1069 DPRINTK ("ENTER\n");
1070
1071 retval = request_irq (dev->irq, netdrv_interrupt, IRQF_SHARED, dev->name, dev);
1072 if (retval) {
1073 DPRINTK ("EXIT, returning %d\n", retval);
1074 return retval;
1075 }
1076
1077 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1078 &tp->tx_bufs_dma);
1079 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1080 &tp->rx_ring_dma);
1081 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1082 free_irq(dev->irq, dev);
1083
1084 if (tp->tx_bufs)
1085 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1086 tp->tx_bufs, tp->tx_bufs_dma);
1087 if (tp->rx_ring)
1088 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1089 tp->rx_ring, tp->rx_ring_dma);
1090
1091 DPRINTK ("EXIT, returning -ENOMEM\n");
1092 return -ENOMEM;
1093
1094 }
1095
1096 tp->full_duplex = tp->duplex_lock;
1097 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1098
1099 netdrv_init_ring (dev);
1100 netdrv_hw_start (dev);
1101
1102 DPRINTK ("%s: netdrv_open() ioaddr %#lx IRQ %d"
1103 " GP Pins %2.2x %s-duplex.\n",
1104 dev->name, pci_resource_start (tp->pci_dev, 1),
1105 dev->irq, NETDRV_R8 (MediaStatus),
1106 tp->full_duplex ? "full" : "half");
1107
1108 /* Set the timer to switch to check for link beat and perhaps switch
1109 to an alternate media type. */
1110 init_timer (&tp->timer);
1111 tp->timer.expires = jiffies + 3 * HZ;
1112 tp->timer.data = (unsigned long) dev;
1113 tp->timer.function = &netdrv_timer;
1114 add_timer (&tp->timer);
1115
1116 DPRINTK ("EXIT, returning 0\n");
1117 return 0;
1118 }
1119
1120
1121 /* Start the hardware at open or resume. */
1122 static void netdrv_hw_start (struct net_device *dev)
1123 {
1124 struct netdrv_private *tp = dev->priv;
1125 void *ioaddr = tp->mmio_addr;
1126 u32 i;
1127
1128 DPRINTK ("ENTER\n");
1129
1130 /* Soft reset the chip. */
1131 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) | CmdReset);
1132 udelay (100);
1133
1134 /* Check that the chip has finished the reset. */
1135 for (i = 1000; i > 0; i--)
1136 if ((NETDRV_R8 (ChipCmd) & CmdReset) == 0)
1137 break;
1138
1139 /* Restore our idea of the MAC address. */
1140 NETDRV_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1141 NETDRV_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1142
1143 /* Must enable Tx/Rx before setting transfer thresholds! */
1144 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1145 CmdRxEnb | CmdTxEnb);
1146
1147 i = netdrv_rx_config |
1148 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1149 NETDRV_W32_F (RxConfig, i);
1150
1151 /* Check this value: the documentation for IFG contradicts ifself. */
1152 NETDRV_W32 (TxConfig, (TX_DMA_BURST << TxDMAShift));
1153
1154 /* unlock Config[01234] and BMCR register writes */
1155 NETDRV_W8_F (Cfg9346, Cfg9346_Unlock);
1156 udelay (10);
1157
1158 tp->cur_rx = 0;
1159
1160 /* Lock Config[01234] and BMCR register writes */
1161 NETDRV_W8_F (Cfg9346, Cfg9346_Lock);
1162 udelay (10);
1163
1164 /* init Rx ring buffer DMA address */
1165 NETDRV_W32_F (RxBuf, tp->rx_ring_dma);
1166
1167 /* init Tx buffer DMA addresses */
1168 for (i = 0; i < NUM_TX_DESC; i++)
1169 NETDRV_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1170
1171 NETDRV_W32_F (RxMissed, 0);
1172
1173 netdrv_set_rx_mode (dev);
1174
1175 /* no early-rx interrupts */
1176 NETDRV_W16 (MultiIntr, NETDRV_R16 (MultiIntr) & MultiIntrClear);
1177
1178 /* make sure RxTx has started */
1179 NETDRV_W8_F (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear) |
1180 CmdRxEnb | CmdTxEnb);
1181
1182 /* Enable all known interrupts by setting the interrupt mask. */
1183 NETDRV_W16_F (IntrMask, netdrv_intr_mask);
1184
1185 netif_start_queue (dev);
1186
1187 DPRINTK ("EXIT\n");
1188 }
1189
1190
1191 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1192 static void netdrv_init_ring (struct net_device *dev)
1193 {
1194 struct netdrv_private *tp = dev->priv;
1195 int i;
1196
1197 DPRINTK ("ENTER\n");
1198
1199 tp->cur_rx = 0;
1200 atomic_set (&tp->cur_tx, 0);
1201 atomic_set (&tp->dirty_tx, 0);
1202
1203 for (i = 0; i < NUM_TX_DESC; i++) {
1204 tp->tx_info[i].skb = NULL;
1205 tp->tx_info[i].mapping = 0;
1206 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1207 }
1208
1209 DPRINTK ("EXIT\n");
1210 }
1211
1212
1213 static void netdrv_timer (unsigned long data)
1214 {
1215 struct net_device *dev = (struct net_device *) data;
1216 struct netdrv_private *tp = dev->priv;
1217 void *ioaddr = tp->mmio_addr;
1218 int next_tick = 60 * HZ;
1219 int mii_lpa;
1220
1221 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1222
1223 if (!tp->duplex_lock && mii_lpa != 0xffff) {
1224 int duplex = (mii_lpa & LPA_100FULL)
1225 || (mii_lpa & 0x01C0) == 0x0040;
1226 if (tp->full_duplex != duplex) {
1227 tp->full_duplex = duplex;
1228 printk (KERN_INFO
1229 "%s: Setting %s-duplex based on MII #%d link"
1230 " partner ability of %4.4x.\n", dev->name,
1231 tp->full_duplex ? "full" : "half",
1232 tp->phys[0], mii_lpa);
1233 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1234 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1235 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1236 }
1237 }
1238
1239 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1240 dev->name, NETDRV_R16 (NWayLPAR));
1241 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x"
1242 " RxStatus %4.4x.\n", dev->name,
1243 NETDRV_R16 (IntrMask),
1244 NETDRV_R16 (IntrStatus),
1245 NETDRV_R32 (RxEarlyStatus));
1246 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1247 dev->name, NETDRV_R8 (Config0),
1248 NETDRV_R8 (Config1));
1249
1250 tp->timer.expires = jiffies + next_tick;
1251 add_timer (&tp->timer);
1252 }
1253
1254
1255 static void netdrv_tx_clear (struct netdrv_private *tp)
1256 {
1257 int i;
1258
1259 atomic_set (&tp->cur_tx, 0);
1260 atomic_set (&tp->dirty_tx, 0);
1261
1262 /* Dump the unsent Tx packets. */
1263 for (i = 0; i < NUM_TX_DESC; i++) {
1264 struct ring_info *rp = &tp->tx_info[i];
1265 if (rp->mapping != 0) {
1266 pci_unmap_single (tp->pci_dev, rp->mapping,
1267 rp->skb->len, PCI_DMA_TODEVICE);
1268 rp->mapping = 0;
1269 }
1270 if (rp->skb) {
1271 dev_kfree_skb (rp->skb);
1272 rp->skb = NULL;
1273 dev->stats.tx_dropped++;
1274 }
1275 }
1276 }
1277
1278
1279 static void netdrv_tx_timeout (struct net_device *dev)
1280 {
1281 struct netdrv_private *tp = dev->priv;
1282 void *ioaddr = tp->mmio_addr;
1283 int i;
1284 u8 tmp8;
1285 unsigned long flags;
1286
1287 DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
1288 "media %2.2x.\n", dev->name,
1289 NETDRV_R8 (ChipCmd),
1290 NETDRV_R16 (IntrStatus),
1291 NETDRV_R8 (MediaStatus));
1292
1293 /* disable Tx ASAP, if not already */
1294 tmp8 = NETDRV_R8 (ChipCmd);
1295 if (tmp8 & CmdTxEnb)
1296 NETDRV_W8 (ChipCmd, tmp8 & ~CmdTxEnb);
1297
1298 /* Disable interrupts by clearing the interrupt mask. */
1299 NETDRV_W16 (IntrMask, 0x0000);
1300
1301 /* Emit info to figure out what went wrong. */
1302 printk (KERN_DEBUG "%s: Tx queue start entry %d dirty entry %d.\n",
1303 dev->name, atomic_read (&tp->cur_tx),
1304 atomic_read (&tp->dirty_tx));
1305 for (i = 0; i < NUM_TX_DESC; i++)
1306 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1307 dev->name, i, NETDRV_R32 (TxStatus0 + (i * 4)),
1308 i == atomic_read (&tp->dirty_tx) % NUM_TX_DESC ?
1309 " (queue head)" : "");
1310
1311 /* Stop a shared interrupt from scavenging while we are. */
1312 spin_lock_irqsave (&tp->lock, flags);
1313
1314 netdrv_tx_clear (tp);
1315
1316 spin_unlock_irqrestore (&tp->lock, flags);
1317
1318 /* ...and finally, reset everything */
1319 netdrv_hw_start (dev);
1320
1321 netif_wake_queue (dev);
1322 }
1323
1324
1325
1326 static int netdrv_start_xmit (struct sk_buff *skb, struct net_device *dev)
1327 {
1328 struct netdrv_private *tp = dev->priv;
1329 void *ioaddr = tp->mmio_addr;
1330 int entry;
1331
1332 /* Calculate the next Tx descriptor entry. */
1333 entry = atomic_read (&tp->cur_tx) % NUM_TX_DESC;
1334
1335 assert (tp->tx_info[entry].skb == NULL);
1336 assert (tp->tx_info[entry].mapping == 0);
1337
1338 tp->tx_info[entry].skb = skb;
1339 /* tp->tx_info[entry].mapping = 0; */
1340 skb_copy_from_linear_data(skb, tp->tx_buf[entry], skb->len);
1341
1342 /* Note: the chip doesn't have auto-pad! */
1343 NETDRV_W32 (TxStatus0 + (entry * sizeof(u32)),
1344 tp->tx_flag | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1345
1346 dev->trans_start = jiffies;
1347 atomic_inc (&tp->cur_tx);
1348 if ((atomic_read (&tp->cur_tx) - atomic_read (&tp->dirty_tx)) >= NUM_TX_DESC)
1349 netif_stop_queue (dev);
1350
1351 DPRINTK ("%s: Queued Tx packet at %p size %u to slot %d.\n",
1352 dev->name, skb->data, skb->len, entry);
1353
1354 return 0;
1355 }
1356
1357
1358 static void netdrv_tx_interrupt (struct net_device *dev,
1359 struct netdrv_private *tp,
1360 void *ioaddr)
1361 {
1362 int cur_tx, dirty_tx, tx_left;
1363
1364 assert (dev != NULL);
1365 assert (tp != NULL);
1366 assert (ioaddr != NULL);
1367
1368 dirty_tx = atomic_read (&tp->dirty_tx);
1369
1370 cur_tx = atomic_read (&tp->cur_tx);
1371 tx_left = cur_tx - dirty_tx;
1372 while (tx_left > 0) {
1373 int entry = dirty_tx % NUM_TX_DESC;
1374 int txstatus;
1375
1376 txstatus = NETDRV_R32 (TxStatus0 + (entry * sizeof (u32)));
1377
1378 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1379 break; /* It still hasn't been Txed */
1380
1381 /* Note: TxCarrierLost is always asserted at 100mbps. */
1382 if (txstatus & (TxOutOfWindow | TxAborted)) {
1383 /* There was an major error, log it. */
1384 DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
1385 dev->name, txstatus);
1386 dev->stats.tx_errors++;
1387 if (txstatus & TxAborted) {
1388 dev->stats.tx_aborted_errors++;
1389 NETDRV_W32 (TxConfig, TxClearAbt | (TX_DMA_BURST << TxDMAShift));
1390 }
1391 if (txstatus & TxCarrierLost)
1392 dev->stats.tx_carrier_errors++;
1393 if (txstatus & TxOutOfWindow)
1394 dev->stats.tx_window_errors++;
1395 } else {
1396 if (txstatus & TxUnderrun) {
1397 /* Add 64 to the Tx FIFO threshold. */
1398 if (tp->tx_flag < 0x00300000)
1399 tp->tx_flag += 0x00020000;
1400 dev->stats.tx_fifo_errors++;
1401 }
1402 dev->stats.collisions += (txstatus >> 24) & 15;
1403 dev->stats.tx_bytes += txstatus & 0x7ff;
1404 dev->stats.tx_packets++;
1405 }
1406
1407 /* Free the original skb. */
1408 if (tp->tx_info[entry].mapping != 0) {
1409 pci_unmap_single(tp->pci_dev,
1410 tp->tx_info[entry].mapping,
1411 tp->tx_info[entry].skb->len,
1412 PCI_DMA_TODEVICE);
1413 tp->tx_info[entry].mapping = 0;
1414 }
1415 dev_kfree_skb_irq (tp->tx_info[entry].skb);
1416 tp->tx_info[entry].skb = NULL;
1417 dirty_tx++;
1418 if (dirty_tx < 0) { /* handle signed int overflow */
1419 atomic_sub (cur_tx, &tp->cur_tx); /* XXX racy? */
1420 dirty_tx = cur_tx - tx_left + 1;
1421 }
1422 if (netif_queue_stopped (dev))
1423 netif_wake_queue (dev);
1424
1425 cur_tx = atomic_read (&tp->cur_tx);
1426 tx_left = cur_tx - dirty_tx;
1427
1428 }
1429
1430 #ifndef NETDRV_NDEBUG
1431 if (atomic_read (&tp->cur_tx) - dirty_tx > NUM_TX_DESC) {
1432 printk (KERN_ERR
1433 "%s: Out-of-sync dirty pointer, %d vs. %d.\n",
1434 dev->name, dirty_tx, atomic_read (&tp->cur_tx));
1435 dirty_tx += NUM_TX_DESC;
1436 }
1437 #endif /* NETDRV_NDEBUG */
1438
1439 atomic_set (&tp->dirty_tx, dirty_tx);
1440 }
1441
1442
1443 /* TODO: clean this up! Rx reset need not be this intensive */
1444 static void netdrv_rx_err (u32 rx_status, struct net_device *dev,
1445 struct netdrv_private *tp, void *ioaddr)
1446 {
1447 u8 tmp8;
1448 int tmp_work = 1000;
1449
1450 DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
1451 dev->name, rx_status);
1452 if (rx_status & RxTooLong) {
1453 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1454 dev->name, rx_status);
1455 /* A.C.: The chip hangs here. */
1456 }
1457 dev->stats.rx_errors++;
1458 if (rx_status & (RxBadSymbol | RxBadAlign))
1459 dev->stats.rx_frame_errors++;
1460 if (rx_status & (RxRunt | RxTooLong))
1461 dev->stats.rx_length_errors++;
1462 if (rx_status & RxCRCErr)
1463 dev->stats.rx_crc_errors++;
1464 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1465 tp->cur_rx = 0;
1466
1467 /* disable receive */
1468 tmp8 = NETDRV_R8 (ChipCmd) & ChipCmdClear;
1469 NETDRV_W8_F (ChipCmd, tmp8 | CmdTxEnb);
1470
1471 /* A.C.: Reset the multicast list. */
1472 netdrv_set_rx_mode (dev);
1473
1474 /* XXX potentially temporary hack to
1475 * restart hung receiver */
1476 while (--tmp_work > 0) {
1477 tmp8 = NETDRV_R8 (ChipCmd);
1478 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1479 break;
1480 NETDRV_W8_F (ChipCmd,
1481 (tmp8 & ChipCmdClear) | CmdRxEnb | CmdTxEnb);
1482 }
1483
1484 /* G.S.: Re-enable receiver */
1485 /* XXX temporary hack to work around receiver hang */
1486 netdrv_set_rx_mode (dev);
1487
1488 if (tmp_work <= 0)
1489 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1490 }
1491
1492
1493 /* The data sheet doesn't describe the Rx ring at all, so I'm guessing at the
1494 field alignments and semantics. */
1495 static void netdrv_rx_interrupt (struct net_device *dev,
1496 struct netdrv_private *tp, void *ioaddr)
1497 {
1498 unsigned char *rx_ring;
1499 u16 cur_rx;
1500
1501 assert (dev != NULL);
1502 assert (tp != NULL);
1503 assert (ioaddr != NULL);
1504
1505 rx_ring = tp->rx_ring;
1506 cur_rx = tp->cur_rx;
1507
1508 DPRINTK ("%s: In netdrv_rx(), current %4.4x BufAddr %4.4x,"
1509 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1510 NETDRV_R16 (RxBufAddr),
1511 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1512
1513 while ((NETDRV_R8 (ChipCmd) & RxBufEmpty) == 0) {
1514 int ring_offset = cur_rx % RX_BUF_LEN;
1515 u32 rx_status;
1516 unsigned int rx_size;
1517 unsigned int pkt_size;
1518 struct sk_buff *skb;
1519
1520 /* read size+status of next frame from DMA ring buffer */
1521 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1522 rx_size = rx_status >> 16;
1523 pkt_size = rx_size - 4;
1524
1525 DPRINTK ("%s: netdrv_rx() status %4.4x, size %4.4x,"
1526 " cur %4.4x.\n", dev->name, rx_status,
1527 rx_size, cur_rx);
1528 #if NETDRV_DEBUG > 2
1529 {
1530 int i;
1531 DPRINTK ("%s: Frame contents ", dev->name);
1532 for (i = 0; i < 70; i++)
1533 printk (" %2.2x",
1534 rx_ring[ring_offset + i]);
1535 printk (".\n");
1536 }
1537 #endif
1538
1539 /* If Rx err or invalid rx_size/rx_status received
1540 * (which happens if we get lost in the ring),
1541 * Rx process gets reset, so we abort any further
1542 * Rx processing.
1543 */
1544 if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
1545 (!(rx_status & RxStatusOK))) {
1546 netdrv_rx_err (rx_status, dev, tp, ioaddr);
1547 return;
1548 }
1549
1550 /* Malloc up new buffer, compatible with net-2e. */
1551 /* Omit the four octet CRC from the length. */
1552
1553 /* TODO: consider allocating skb's outside of
1554 * interrupt context, both to speed interrupt processing,
1555 * and also to reduce the chances of having to
1556 * drop packets here under memory pressure.
1557 */
1558
1559 skb = dev_alloc_skb (pkt_size + 2);
1560 if (skb) {
1561 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
1562
1563 skb_copy_to_linear_data (skb, &rx_ring[ring_offset + 4], pkt_size);
1564 skb_put (skb, pkt_size);
1565
1566 skb->protocol = eth_type_trans (skb, dev);
1567 netif_rx (skb);
1568 dev->last_rx = jiffies;
1569 dev->stats.rx_bytes += pkt_size;
1570 dev->stats.rx_packets++;
1571 } else {
1572 printk (KERN_WARNING
1573 "%s: Memory squeeze, dropping packet.\n",
1574 dev->name);
1575 dev->stats.rx_dropped++;
1576 }
1577
1578 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
1579 NETDRV_W16_F (RxBufPtr, cur_rx - 16);
1580 }
1581
1582 DPRINTK ("%s: Done netdrv_rx(), current %4.4x BufAddr %4.4x,"
1583 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
1584 NETDRV_R16 (RxBufAddr),
1585 NETDRV_R16 (RxBufPtr), NETDRV_R8 (ChipCmd));
1586
1587 tp->cur_rx = cur_rx;
1588 }
1589
1590
1591 static void netdrv_weird_interrupt (struct net_device *dev,
1592 struct netdrv_private *tp,
1593 void *ioaddr,
1594 int status, int link_changed)
1595 {
1596 printk (KERN_DEBUG "%s: Abnormal interrupt, status %8.8x.\n",
1597 dev->name, status);
1598
1599 assert (dev != NULL);
1600 assert (tp != NULL);
1601 assert (ioaddr != NULL);
1602
1603 /* Update the error count. */
1604 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1605 NETDRV_W32 (RxMissed, 0);
1606
1607 if ((status & RxUnderrun) && link_changed &&
1608 (tp->drv_flags & HAS_LNK_CHNG)) {
1609 /* Really link-change on new chips. */
1610 int lpar = NETDRV_R16 (NWayLPAR);
1611 int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040
1612 || tp->duplex_lock;
1613 if (tp->full_duplex != duplex) {
1614 tp->full_duplex = duplex;
1615 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1616 NETDRV_W8 (Config1, tp->full_duplex ? 0x60 : 0x20);
1617 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1618 }
1619 status &= ~RxUnderrun;
1620 }
1621
1622 /* XXX along with netdrv_rx_err, are we double-counting errors? */
1623 if (status &
1624 (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
1625 dev->stats.rx_errors++;
1626
1627 if (status & (PCSTimeout))
1628 dev->stats.rx_length_errors++;
1629 if (status & (RxUnderrun | RxFIFOOver))
1630 dev->stats.rx_fifo_errors++;
1631 if (status & RxOverflow) {
1632 dev->stats.rx_over_errors++;
1633 tp->cur_rx = NETDRV_R16 (RxBufAddr) % RX_BUF_LEN;
1634 NETDRV_W16_F (RxBufPtr, tp->cur_rx - 16);
1635 }
1636 if (status & PCIErr) {
1637 u16 pci_cmd_status;
1638 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
1639
1640 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
1641 dev->name, pci_cmd_status);
1642 }
1643 }
1644
1645
1646 /* The interrupt handler does all of the Rx thread work and cleans up
1647 after the Tx thread. */
1648 static irqreturn_t netdrv_interrupt (int irq, void *dev_instance)
1649 {
1650 struct net_device *dev = (struct net_device *) dev_instance;
1651 struct netdrv_private *tp = dev->priv;
1652 int boguscnt = max_interrupt_work;
1653 void *ioaddr = tp->mmio_addr;
1654 int status = 0, link_changed = 0; /* avoid bogus "uninit" warning */
1655 int handled = 0;
1656
1657 spin_lock (&tp->lock);
1658
1659 do {
1660 status = NETDRV_R16 (IntrStatus);
1661
1662 /* h/w no longer present (hotplug?) or major error, bail */
1663 if (status == 0xFFFF)
1664 break;
1665
1666 handled = 1;
1667 /* Acknowledge all of the current interrupt sources ASAP */
1668 NETDRV_W16_F (IntrStatus, status);
1669
1670 DPRINTK ("%s: interrupt status=%#4.4x new intstat=%#4.4x.\n",
1671 dev->name, status,
1672 NETDRV_R16 (IntrStatus));
1673
1674 if ((status &
1675 (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1676 RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
1677 break;
1678
1679 /* Check uncommon events with one test. */
1680 if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
1681 RxFIFOOver | TxErr | RxErr))
1682 netdrv_weird_interrupt (dev, tp, ioaddr,
1683 status, link_changed);
1684
1685 if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) /* Rx interrupt */
1686 netdrv_rx_interrupt (dev, tp, ioaddr);
1687
1688 if (status & (TxOK | TxErr))
1689 netdrv_tx_interrupt (dev, tp, ioaddr);
1690
1691 boguscnt--;
1692 } while (boguscnt > 0);
1693
1694 if (boguscnt <= 0) {
1695 printk (KERN_WARNING
1696 "%s: Too much work at interrupt, "
1697 "IntrStatus=0x%4.4x.\n", dev->name,
1698 status);
1699
1700 /* Clear all interrupt sources. */
1701 NETDRV_W16 (IntrStatus, 0xffff);
1702 }
1703
1704 spin_unlock (&tp->lock);
1705
1706 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
1707 dev->name, NETDRV_R16 (IntrStatus));
1708 return IRQ_RETVAL(handled);
1709 }
1710
1711
1712 static int netdrv_close (struct net_device *dev)
1713 {
1714 struct netdrv_private *tp = dev->priv;
1715 void *ioaddr = tp->mmio_addr;
1716 unsigned long flags;
1717
1718 DPRINTK ("ENTER\n");
1719
1720 netif_stop_queue (dev);
1721
1722 DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
1723 dev->name, NETDRV_R16 (IntrStatus));
1724
1725 del_timer_sync (&tp->timer);
1726
1727 spin_lock_irqsave (&tp->lock, flags);
1728
1729 /* Stop the chip's Tx and Rx DMA processes. */
1730 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1731
1732 /* Disable interrupts by clearing the interrupt mask. */
1733 NETDRV_W16 (IntrMask, 0x0000);
1734
1735 /* Update the error counts. */
1736 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1737 NETDRV_W32 (RxMissed, 0);
1738
1739 spin_unlock_irqrestore (&tp->lock, flags);
1740
1741 synchronize_irq ();
1742 free_irq (dev->irq, dev);
1743
1744 netdrv_tx_clear (tp);
1745
1746 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1747 tp->rx_ring, tp->rx_ring_dma);
1748 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1749 tp->tx_bufs, tp->tx_bufs_dma);
1750 tp->rx_ring = NULL;
1751 tp->tx_bufs = NULL;
1752
1753 /* Green! Put the chip in low-power mode. */
1754 NETDRV_W8 (Cfg9346, Cfg9346_Unlock);
1755 NETDRV_W8 (Config1, 0x03);
1756 NETDRV_W8 (Cfg9346, Cfg9346_Lock);
1757
1758 DPRINTK ("EXIT\n");
1759 return 0;
1760 }
1761
1762
1763 static int netdrv_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1764 {
1765 struct netdrv_private *tp = dev->priv;
1766 struct mii_ioctl_data *data = if_mii(rq);
1767 unsigned long flags;
1768 int rc = 0;
1769
1770 DPRINTK ("ENTER\n");
1771
1772 switch (cmd) {
1773 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1774 data->phy_id = tp->phys[0] & 0x3f;
1775 /* Fall Through */
1776
1777 case SIOCGMIIREG: /* Read MII PHY register. */
1778 spin_lock_irqsave (&tp->lock, flags);
1779 data->val_out = mdio_read (dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1780 spin_unlock_irqrestore (&tp->lock, flags);
1781 break;
1782
1783 case SIOCSMIIREG: /* Write MII PHY register. */
1784 if (!capable (CAP_NET_ADMIN)) {
1785 rc = -EPERM;
1786 break;
1787 }
1788
1789 spin_lock_irqsave (&tp->lock, flags);
1790 mdio_write (dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1791 spin_unlock_irqrestore (&tp->lock, flags);
1792 break;
1793
1794 default:
1795 rc = -EOPNOTSUPP;
1796 break;
1797 }
1798
1799 DPRINTK ("EXIT, returning %d\n", rc);
1800 return rc;
1801 }
1802
1803 /* Set or clear the multicast filter for this adaptor.
1804 This routine is not state sensitive and need not be SMP locked. */
1805
1806 static void netdrv_set_rx_mode (struct net_device *dev)
1807 {
1808 struct netdrv_private *tp = dev->priv;
1809 void *ioaddr = tp->mmio_addr;
1810 u32 mc_filter[2]; /* Multicast hash filter */
1811 int i, rx_mode;
1812 u32 tmp;
1813
1814 DPRINTK ("ENTER\n");
1815
1816 DPRINTK ("%s: netdrv_set_rx_mode(%4.4x) done -- Rx config %8.8x.\n",
1817 dev->name, dev->flags, NETDRV_R32 (RxConfig));
1818
1819 /* Note: do not reorder, GCC is clever about common statements. */
1820 if (dev->flags & IFF_PROMISC) {
1821 rx_mode =
1822 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
1823 AcceptAllPhys;
1824 mc_filter[1] = mc_filter[0] = 0xffffffff;
1825 } else if ((dev->mc_count > multicast_filter_limit)
1826 || (dev->flags & IFF_ALLMULTI)) {
1827 /* Too many to filter perfectly -- accept all multicasts. */
1828 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1829 mc_filter[1] = mc_filter[0] = 0xffffffff;
1830 } else {
1831 struct dev_mc_list *mclist;
1832 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1833 mc_filter[1] = mc_filter[0] = 0;
1834 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1835 i++, mclist = mclist->next) {
1836 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1837
1838 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1839 }
1840 }
1841
1842 /* if called from irq handler, lock already acquired */
1843 if (!in_irq ())
1844 spin_lock_irq (&tp->lock);
1845
1846 /* We can safely update without stopping the chip. */
1847 tmp = netdrv_rx_config | rx_mode |
1848 (NETDRV_R32 (RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1849 NETDRV_W32_F (RxConfig, tmp);
1850 NETDRV_W32_F (MAR0 + 0, mc_filter[0]);
1851 NETDRV_W32_F (MAR0 + 4, mc_filter[1]);
1852
1853 if (!in_irq ())
1854 spin_unlock_irq (&tp->lock);
1855
1856 DPRINTK ("EXIT\n");
1857 }
1858
1859
1860 #ifdef CONFIG_PM
1861
1862 static int netdrv_suspend (struct pci_dev *pdev, pm_message_t state)
1863 {
1864 struct net_device *dev = pci_get_drvdata (pdev);
1865 struct netdrv_private *tp = dev->priv;
1866 void *ioaddr = tp->mmio_addr;
1867 unsigned long flags;
1868
1869 if (!netif_running(dev))
1870 return 0;
1871 netif_device_detach (dev);
1872
1873 spin_lock_irqsave (&tp->lock, flags);
1874
1875 /* Disable interrupts, stop Tx and Rx. */
1876 NETDRV_W16 (IntrMask, 0x0000);
1877 NETDRV_W8 (ChipCmd, (NETDRV_R8 (ChipCmd) & ChipCmdClear));
1878
1879 /* Update the error counts. */
1880 dev->stats.rx_missed_errors += NETDRV_R32 (RxMissed);
1881 NETDRV_W32 (RxMissed, 0);
1882
1883 spin_unlock_irqrestore (&tp->lock, flags);
1884
1885 pci_save_state (pdev);
1886 pci_set_power_state (pdev, PCI_D3hot);
1887
1888 return 0;
1889 }
1890
1891
1892 static int netdrv_resume (struct pci_dev *pdev)
1893 {
1894 struct net_device *dev = pci_get_drvdata (pdev);
1895 struct netdrv_private *tp = dev->priv;
1896
1897 if (!netif_running(dev))
1898 return 0;
1899 pci_set_power_state (pdev, PCI_D0);
1900 pci_restore_state (pdev);
1901 netif_device_attach (dev);
1902 netdrv_hw_start (dev);
1903
1904 return 0;
1905 }
1906
1907 #endif /* CONFIG_PM */
1908
1909
1910 static struct pci_driver netdrv_pci_driver = {
1911 .name = MODNAME,
1912 .id_table = netdrv_pci_tbl,
1913 .probe = netdrv_init_one,
1914 .remove = __devexit_p(netdrv_remove_one),
1915 #ifdef CONFIG_PM
1916 .suspend = netdrv_suspend,
1917 .resume = netdrv_resume,
1918 #endif /* CONFIG_PM */
1919 };
1920
1921
1922 static int __init netdrv_init_module (void)
1923 {
1924 /* when a module, this is printed whether or not devices are found in probe */
1925 #ifdef MODULE
1926 printk(version);
1927 #endif
1928 return pci_register_driver(&netdrv_pci_driver);
1929 }
1930
1931
1932 static void __exit netdrv_cleanup_module (void)
1933 {
1934 pci_unregister_driver (&netdrv_pci_driver);
1935 }
1936
1937
1938 module_init(netdrv_init_module);
1939 module_exit(netdrv_cleanup_module);
WRT350N Kernel Patches