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x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / net / tehuti.c
blob17585e5eed5379c2299f85f92a3956768850161e
1 /*
2 * Tehuti Networks(R) Network Driver
3 * ethtool interface implementation
4 * Copyright (C) 2007 Tehuti Networks Ltd. All rights reserved
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 /*
13 * RX HW/SW interaction overview
14 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
15 * There are 2 types of RX communication channels betwean driver and NIC.
16 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
17 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
18 * info about buffer's location, size and ID. An ID field is used to identify a
19 * buffer when it's returned with data via RXD Fifo (see below)
20 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
21 * filled by HW and is readen by SW. Each descriptor holds status and ID.
22 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
23 * via dma moves it into host memory, builds new RXD descriptor with same ID,
24 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
25 *
26 * Current NIC configuration (registers + firmware) makes NIC use 2 RXF Fifos.
27 * One holds 1.5K packets and another - 26K packets. Depending on incoming
28 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
29 * filled with data, HW builds new RXD descriptor for it and push it into single
30 * RXD Fifo.
31 *
32 * RX SW Data Structures
33 * ~~~~~~~~~~~~~~~~~~~~~
34 * skb db - used to keep track of all skbs owned by SW and their dma addresses.
35 * For RX case, ownership lasts from allocating new empty skb for RXF until
36 * accepting full skb from RXD and passing it to OS. Each RXF Fifo has its own
37 * skb db. Implemented as array with bitmask.
38 * fifo - keeps info about fifo's size and location, relevant HW registers,
39 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
40 * Implemented as simple struct.
41 *
42 * RX SW Execution Flow
43 * ~~~~~~~~~~~~~~~~~~~~
44 * Upon initialization (ifconfig up) driver creates RX fifos and initializes
45 * relevant registers. At the end of init phase, driver enables interrupts.
46 * NIC sees that there is no RXF buffers and raises
47 * RD_INTR interrupt, isr fills skbs and Rx begins.
48 * Driver has two receive operation modes:
49 * NAPI - interrupt-driven mixed with polling
50 * interrupt-driven only
51 *
52 * Interrupt-driven only flow is following. When buffer is ready, HW raises
53 * interrupt and isr is called. isr collects all available packets
54 * (bdx_rx_receive), refills skbs (bdx_rx_alloc_skbs) and exit.
55
56 * Rx buffer allocation note
57 * ~~~~~~~~~~~~~~~~~~~~~~~~~
58 * Driver cares to feed such amount of RxF descriptors that respective amount of
59 * RxD descriptors can not fill entire RxD fifo. The main reason is lack of
60 * overflow check in Bordeaux for RxD fifo free/used size.
61 * FIXME: this is NOT fully implemented, more work should be done
62 *
63 */
64
65 #include "tehuti.h"
66 #include "tehuti_fw.h"
67
68 static struct pci_device_id __devinitdata bdx_pci_tbl[] = {
69 {0x1FC9, 0x3009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
70 {0x1FC9, 0x3010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 {0x1FC9, 0x3014, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
72 {0}
73 };
74
75 MODULE_DEVICE_TABLE(pci, bdx_pci_tbl);
76
77 /* Definitions needed by ISR or NAPI functions */
78 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f);
79 static void bdx_tx_cleanup(struct bdx_priv *priv);
80 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget);
81
82 /* Definitions needed by FW loading */
83 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size);
84
85 /* Definitions needed by hw_start */
86 static int bdx_tx_init(struct bdx_priv *priv);
87 static int bdx_rx_init(struct bdx_priv *priv);
88
89 /* Definitions needed by bdx_close */
90 static void bdx_rx_free(struct bdx_priv *priv);
91 static void bdx_tx_free(struct bdx_priv *priv);
92
93 /* Definitions needed by bdx_probe */
94 static void bdx_ethtool_ops(struct net_device *netdev);
95
96 /*************************************************************************
97 * Print Info *
98 *************************************************************************/
99
100 static void print_hw_id(struct pci_dev *pdev)
101 {
102 struct pci_nic *nic = pci_get_drvdata(pdev);
103 u16 pci_link_status = 0;
104 u16 pci_ctrl = 0;
105
106 pci_read_config_word(pdev, PCI_LINK_STATUS_REG, &pci_link_status);
107 pci_read_config_word(pdev, PCI_DEV_CTRL_REG, &pci_ctrl);
108
109 printk(KERN_INFO "tehuti: %s%s\n", BDX_NIC_NAME,
110 nic->port_num == 1 ? "" : ", 2-Port");
111 printk(KERN_INFO
112 "tehuti: srom 0x%x fpga %d build %u lane# %d"
113 " max_pl 0x%x mrrs 0x%x\n",
114 readl(nic->regs + SROM_VER), readl(nic->regs + FPGA_VER) & 0xFFF,
115 readl(nic->regs + FPGA_SEED),
116 GET_LINK_STATUS_LANES(pci_link_status),
117 GET_DEV_CTRL_MAXPL(pci_ctrl), GET_DEV_CTRL_MRRS(pci_ctrl));
118 }
119
120 static void print_fw_id(struct pci_nic *nic)
121 {
122 printk(KERN_INFO "tehuti: fw 0x%x\n", readl(nic->regs + FW_VER));
123 }
124
125 static void print_eth_id(struct net_device *ndev)
126 {
127 printk(KERN_INFO "%s: %s, Port %c\n", ndev->name, BDX_NIC_NAME,
128 (ndev->if_port == 0) ? 'A' : 'B');
129
130 }
131
132 /*************************************************************************
133 * Code *
134 *************************************************************************/
135
136 #define bdx_enable_interrupts(priv) \
137 do { WRITE_REG(priv, regIMR, IR_RUN); } while (0)
138 #define bdx_disable_interrupts(priv) \
139 do { WRITE_REG(priv, regIMR, 0); } while (0)
140
141 /* bdx_fifo_init
142 * create TX/RX descriptor fifo for host-NIC communication.
143 * 1K extra space is allocated at the end of the fifo to simplify
144 * processing of descriptors that wraps around fifo's end
145 * @priv - NIC private structure
146 * @f - fifo to initialize
147 * @fsz_type - fifo size type: 0-4KB, 1-8KB, 2-16KB, 3-32KB
148 * @reg_XXX - offsets of registers relative to base address
149 *
150 * Returns 0 on success, negative value on failure
151 *
152 */
153 static int
154 bdx_fifo_init(struct bdx_priv *priv, struct fifo *f, int fsz_type,
155 u16 reg_CFG0, u16 reg_CFG1, u16 reg_RPTR, u16 reg_WPTR)
156 {
157 u16 memsz = FIFO_SIZE * (1 << fsz_type);
158
159 memset(f, 0, sizeof(struct fifo));
160 /* pci_alloc_consistent gives us 4k-aligned memory */
161 f->va = pci_alloc_consistent(priv->pdev,
162 memsz + FIFO_EXTRA_SPACE, &f->da);
163 if (!f->va) {
164 ERR("pci_alloc_consistent failed\n");
165 RET(-ENOMEM);
166 }
167 f->reg_CFG0 = reg_CFG0;
168 f->reg_CFG1 = reg_CFG1;
169 f->reg_RPTR = reg_RPTR;
170 f->reg_WPTR = reg_WPTR;
171 f->rptr = 0;
172 f->wptr = 0;
173 f->memsz = memsz;
174 f->size_mask = memsz - 1;
175 WRITE_REG(priv, reg_CFG0, (u32) ((f->da & TX_RX_CFG0_BASE) | fsz_type));
176 WRITE_REG(priv, reg_CFG1, H32_64(f->da));
177
178 RET(0);
179 }
180
181 /* bdx_fifo_free - free all resources used by fifo
182 * @priv - NIC private structure
183 * @f - fifo to release
184 */
185 static void bdx_fifo_free(struct bdx_priv *priv, struct fifo *f)
186 {
187 ENTER;
188 if (f->va) {
189 pci_free_consistent(priv->pdev,
190 f->memsz + FIFO_EXTRA_SPACE, f->va, f->da);
191 f->va = NULL;
192 }
193 RET();
194 }
195
196 /*
197 * bdx_link_changed - notifies OS about hw link state.
198 * @bdx_priv - hw adapter structure
199 */
200 static void bdx_link_changed(struct bdx_priv *priv)
201 {
202 u32 link = READ_REG(priv, regMAC_LNK_STAT) & MAC_LINK_STAT;
203
204 if (!link) {
205 if (netif_carrier_ok(priv->ndev)) {
206 netif_stop_queue(priv->ndev);
207 netif_carrier_off(priv->ndev);
208 ERR("%s: Link Down\n", priv->ndev->name);
209 }
210 } else {
211 if (!netif_carrier_ok(priv->ndev)) {
212 netif_wake_queue(priv->ndev);
213 netif_carrier_on(priv->ndev);
214 ERR("%s: Link Up\n", priv->ndev->name);
215 }
216 }
217 }
218
219 static void bdx_isr_extra(struct bdx_priv *priv, u32 isr)
220 {
221 if (isr & IR_RX_FREE_0) {
222 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
223 DBG("RX_FREE_0\n");
224 }
225
226 if (isr & IR_LNKCHG0)
227 bdx_link_changed(priv);
228
229 if (isr & IR_PCIE_LINK)
230 ERR("%s: PCI-E Link Fault\n", priv->ndev->name);
231
232 if (isr & IR_PCIE_TOUT)
233 ERR("%s: PCI-E Time Out\n", priv->ndev->name);
234
235 }
236
237 /* bdx_isr - Interrupt Service Routine for Bordeaux NIC
238 * @irq - interrupt number
239 * @ndev - network device
240 * @regs - CPU registers
241 *
242 * Return IRQ_NONE if it was not our interrupt, IRQ_HANDLED - otherwise
243 *
244 * It reads ISR register to know interrupt reasons, and proceed them one by one.
245 * Reasons of interest are:
246 * RX_DESC - new packet has arrived and RXD fifo holds its descriptor
247 * RX_FREE - number of free Rx buffers in RXF fifo gets low
248 * TX_FREE - packet was transmited and RXF fifo holds its descriptor
249 */
250
251 static irqreturn_t bdx_isr_napi(int irq, void *dev)
252 {
253 struct net_device *ndev = dev;
254 struct bdx_priv *priv = ndev->priv;
255 u32 isr;
256
257 ENTER;
258 isr = (READ_REG(priv, regISR) & IR_RUN);
259 if (unlikely(!isr)) {
260 bdx_enable_interrupts(priv);
261 return IRQ_NONE; /* Not our interrupt */
262 }
263
264 if (isr & IR_EXTRA)
265 bdx_isr_extra(priv, isr);
266
267 if (isr & (IR_RX_DESC_0 | IR_TX_FREE_0)) {
268 if (likely(netif_rx_schedule_prep(ndev, &priv->napi))) {
269 __netif_rx_schedule(ndev, &priv->napi);
270 RET(IRQ_HANDLED);
271 } else {
272 /* NOTE: we get here if intr has slipped into window
273 * between these lines in bdx_poll:
274 * bdx_enable_interrupts(priv);
275 * return 0;
276 * currently intrs are disabled (since we read ISR),
277 * and we have failed to register next poll.
278 * so we read the regs to trigger chip
279 * and allow further interupts. */
280 READ_REG(priv, regTXF_WPTR_0);
281 READ_REG(priv, regRXD_WPTR_0);
282 }
283 }
284
285 bdx_enable_interrupts(priv);
286 RET(IRQ_HANDLED);
287 }
288
289 static int bdx_poll(struct napi_struct *napi, int budget)
290 {
291 struct bdx_priv *priv = container_of(napi, struct bdx_priv, napi);
292 struct net_device *dev = priv->ndev;
293 int work_done;
294
295 ENTER;
296 bdx_tx_cleanup(priv);
297 work_done = bdx_rx_receive(priv, &priv->rxd_fifo0, budget);
298 if ((work_done < budget) ||
299 (priv->napi_stop++ >= 30)) {
300 DBG("rx poll is done. backing to isr-driven\n");
301
302 /* from time to time we exit to let NAPI layer release
303 * device lock and allow waiting tasks (eg rmmod) to advance) */
304 priv->napi_stop = 0;
305
306 netif_rx_complete(dev, napi);
307 bdx_enable_interrupts(priv);
308 }
309 return work_done;
310 }
311
312 /* bdx_fw_load - loads firmware to NIC
313 * @priv - NIC private structure
314 * Firmware is loaded via TXD fifo, so it must be initialized first.
315 * Firware must be loaded once per NIC not per PCI device provided by NIC (NIC
316 * can have few of them). So all drivers use semaphore register to choose one
317 * that will actually load FW to NIC.
318 */
319
320 static int bdx_fw_load(struct bdx_priv *priv)
321 {
322 int master, i;
323
324 ENTER;
325 master = READ_REG(priv, regINIT_SEMAPHORE);
326 if (!READ_REG(priv, regINIT_STATUS) && master) {
327 bdx_tx_push_desc_safe(priv, s_firmLoad, sizeof(s_firmLoad));
328 mdelay(100);
329 }
330 for (i = 0; i < 200; i++) {
331 if (READ_REG(priv, regINIT_STATUS))
332 break;
333 mdelay(2);
334 }
335 if (master)
336 WRITE_REG(priv, regINIT_SEMAPHORE, 1);
337
338 if (i == 200) {
339 ERR("%s: firmware loading failed\n", priv->ndev->name);
340 DBG("VPC = 0x%x VIC = 0x%x INIT_STATUS = 0x%x i=%d\n",
341 READ_REG(priv, regVPC),
342 READ_REG(priv, regVIC), READ_REG(priv, regINIT_STATUS), i);
343 RET(-EIO);
344 } else {
345 DBG("%s: firmware loading success\n", priv->ndev->name);
346 RET(0);
347 }
348 }
349
350 static void bdx_restore_mac(struct net_device *ndev, struct bdx_priv *priv)
351 {
352 u32 val;
353
354 ENTER;
355 DBG("mac0=%x mac1=%x mac2=%x\n",
356 READ_REG(priv, regUNC_MAC0_A),
357 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
358
359 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]);
360 WRITE_REG(priv, regUNC_MAC2_A, val);
361 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]);
362 WRITE_REG(priv, regUNC_MAC1_A, val);
363 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]);
364 WRITE_REG(priv, regUNC_MAC0_A, val);
365
366 DBG("mac0=%x mac1=%x mac2=%x\n",
367 READ_REG(priv, regUNC_MAC0_A),
368 READ_REG(priv, regUNC_MAC1_A), READ_REG(priv, regUNC_MAC2_A));
369 RET();
370 }
371
372 /* bdx_hw_start - inits registers and starts HW's Rx and Tx engines
373 * @priv - NIC private structure
374 */
375 static int bdx_hw_start(struct bdx_priv *priv)
376 {
377 int rc = -EIO;
378 struct net_device *ndev = priv->ndev;
379
380 ENTER;
381 bdx_link_changed(priv);
382
383 /* 10G overall max length (vlan, eth&ip header, ip payload, crc) */
384 WRITE_REG(priv, regFRM_LENGTH, 0X3FE0);
385 WRITE_REG(priv, regPAUSE_QUANT, 0x96);
386 WRITE_REG(priv, regRX_FIFO_SECTION, 0x800010);
387 WRITE_REG(priv, regTX_FIFO_SECTION, 0xE00010);
388 WRITE_REG(priv, regRX_FULLNESS, 0);
389 WRITE_REG(priv, regTX_FULLNESS, 0);
390 WRITE_REG(priv, regCTRLST,
391 regCTRLST_BASE | regCTRLST_RX_ENA | regCTRLST_TX_ENA);
392
393 WRITE_REG(priv, regVGLB, 0);
394 WRITE_REG(priv, regMAX_FRAME_A,
395 priv->rxf_fifo0.m.pktsz & MAX_FRAME_AB_VAL);
396
397 DBG("RDINTCM=%08x\n", priv->rdintcm); /*NOTE: test script uses this */
398 WRITE_REG(priv, regRDINTCM0, priv->rdintcm);
399 WRITE_REG(priv, regRDINTCM2, 0); /*cpu_to_le32(rcm.val)); */
400
401 DBG("TDINTCM=%08x\n", priv->tdintcm); /*NOTE: test script uses this */
402 WRITE_REG(priv, regTDINTCM0, priv->tdintcm); /* old val = 0x300064 */
403
404 /* Enable timer interrupt once in 2 secs. */
405 /*WRITE_REG(priv, regGTMR0, ((GTMR_SEC * 2) & GTMR_DATA)); */
406 bdx_restore_mac(priv->ndev, priv);
407
408 WRITE_REG(priv, regGMAC_RXF_A, GMAC_RX_FILTER_OSEN |
409 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB);
410
411 #define BDX_IRQ_TYPE ((priv->nic->irq_type == IRQ_MSI)?0:IRQF_SHARED)
412 if ((rc = request_irq(priv->pdev->irq, &bdx_isr_napi, BDX_IRQ_TYPE,
413 ndev->name, ndev)))
414 goto err_irq;
415 bdx_enable_interrupts(priv);
416
417 RET(0);
418
419 err_irq:
420 RET(rc);
421 }
422
423 static void bdx_hw_stop(struct bdx_priv *priv)
424 {
425 ENTER;
426 bdx_disable_interrupts(priv);
427 free_irq(priv->pdev->irq, priv->ndev);
428
429 netif_carrier_off(priv->ndev);
430 netif_stop_queue(priv->ndev);
431
432 RET();
433 }
434
435 static int bdx_hw_reset_direct(void __iomem *regs)
436 {
437 u32 val, i;
438 ENTER;
439
440 /* reset sequences: read, write 1, read, write 0 */
441 val = readl(regs + regCLKPLL);
442 writel((val | CLKPLL_SFTRST) + 0x8, regs + regCLKPLL);
443 udelay(50);
444 val = readl(regs + regCLKPLL);
445 writel(val & ~CLKPLL_SFTRST, regs + regCLKPLL);
446
447 /* check that the PLLs are locked and reset ended */
448 for (i = 0; i < 70; i++, mdelay(10))
449 if ((readl(regs + regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
450 /* do any PCI-E read transaction */
451 readl(regs + regRXD_CFG0_0);
452 return 0;
453 }
454 ERR("tehuti: HW reset failed\n");
455 return 1; /* failure */
456 }
457
458 static int bdx_hw_reset(struct bdx_priv *priv)
459 {
460 u32 val, i;
461 ENTER;
462
463 if (priv->port == 0) {
464 /* reset sequences: read, write 1, read, write 0 */
465 val = READ_REG(priv, regCLKPLL);
466 WRITE_REG(priv, regCLKPLL, (val | CLKPLL_SFTRST) + 0x8);
467 udelay(50);
468 val = READ_REG(priv, regCLKPLL);
469 WRITE_REG(priv, regCLKPLL, val & ~CLKPLL_SFTRST);
470 }
471 /* check that the PLLs are locked and reset ended */
472 for (i = 0; i < 70; i++, mdelay(10))
473 if ((READ_REG(priv, regCLKPLL) & CLKPLL_LKD) == CLKPLL_LKD) {
474 /* do any PCI-E read transaction */
475 READ_REG(priv, regRXD_CFG0_0);
476 return 0;
477 }
478 ERR("tehuti: HW reset failed\n");
479 return 1; /* failure */
480 }
481
482 static int bdx_sw_reset(struct bdx_priv *priv)
483 {
484 int i;
485
486 ENTER;
487 /* 1. load MAC (obsolete) */
488 /* 2. disable Rx (and Tx) */
489 WRITE_REG(priv, regGMAC_RXF_A, 0);
490 mdelay(100);
491 /* 3. disable port */
492 WRITE_REG(priv, regDIS_PORT, 1);
493 /* 4. disable queue */
494 WRITE_REG(priv, regDIS_QU, 1);
495 /* 5. wait until hw is disabled */
496 for (i = 0; i < 50; i++) {
497 if (READ_REG(priv, regRST_PORT) & 1)
498 break;
499 mdelay(10);
500 }
501 if (i == 50)
502 ERR("%s: SW reset timeout. continuing anyway\n",
503 priv->ndev->name);
504
505 /* 6. disable intrs */
506 WRITE_REG(priv, regRDINTCM0, 0);
507 WRITE_REG(priv, regTDINTCM0, 0);
508 WRITE_REG(priv, regIMR, 0);
509 READ_REG(priv, regISR);
510
511 /* 7. reset queue */
512 WRITE_REG(priv, regRST_QU, 1);
513 /* 8. reset port */
514 WRITE_REG(priv, regRST_PORT, 1);
515 /* 9. zero all read and write pointers */
516 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
517 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
518 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
519 WRITE_REG(priv, i, 0);
520 /* 10. unseet port disable */
521 WRITE_REG(priv, regDIS_PORT, 0);
522 /* 11. unset queue disable */
523 WRITE_REG(priv, regDIS_QU, 0);
524 /* 12. unset queue reset */
525 WRITE_REG(priv, regRST_QU, 0);
526 /* 13. unset port reset */
527 WRITE_REG(priv, regRST_PORT, 0);
528 /* 14. enable Rx */
529 /* skiped. will be done later */
530 /* 15. save MAC (obsolete) */
531 for (i = regTXD_WPTR_0; i <= regTXF_RPTR_3; i += 0x10)
532 DBG("%x = %x\n", i, READ_REG(priv, i) & TXF_WPTR_WR_PTR);
533
534 RET(0);
535 }
536
537 /* bdx_reset - performs right type of reset depending on hw type */
538 static int bdx_reset(struct bdx_priv *priv)
539 {
540 ENTER;
541 RET((priv->pdev->device == 0x3009)
542 ? bdx_hw_reset(priv)
543 : bdx_sw_reset(priv));
544 }
545
546 /**
547 * bdx_close - Disables a network interface
548 * @netdev: network interface device structure
549 *
550 * Returns 0, this is not allowed to fail
551 *
552 * The close entry point is called when an interface is de-activated
553 * by the OS. The hardware is still under the drivers control, but
554 * needs to be disabled. A global MAC reset is issued to stop the
555 * hardware, and all transmit and receive resources are freed.
556 **/
557 static int bdx_close(struct net_device *ndev)
558 {
559 struct bdx_priv *priv = NULL;
560
561 ENTER;
562 priv = ndev->priv;
563
564 napi_disable(&priv->napi);
565
566 bdx_reset(priv);
567 bdx_hw_stop(priv);
568 bdx_rx_free(priv);
569 bdx_tx_free(priv);
570 RET(0);
571 }
572
573 /**
574 * bdx_open - Called when a network interface is made active
575 * @netdev: network interface device structure
576 *
577 * Returns 0 on success, negative value on failure
578 *
579 * The open entry point is called when a network interface is made
580 * active by the system (IFF_UP). At this point all resources needed
581 * for transmit and receive operations are allocated, the interrupt
582 * handler is registered with the OS, the watchdog timer is started,
583 * and the stack is notified that the interface is ready.
584 **/
585 static int bdx_open(struct net_device *ndev)
586 {
587 struct bdx_priv *priv;
588 int rc;
589
590 ENTER;
591 priv = ndev->priv;
592 bdx_reset(priv);
593 if (netif_running(ndev))
594 netif_stop_queue(priv->ndev);
595
596 if ((rc = bdx_tx_init(priv)))
597 goto err;
598
599 if ((rc = bdx_rx_init(priv)))
600 goto err;
601
602 if ((rc = bdx_fw_load(priv)))
603 goto err;
604
605 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
606
607 if ((rc = bdx_hw_start(priv)))
608 goto err;
609
610 napi_enable(&priv->napi);
611
612 print_fw_id(priv->nic);
613
614 RET(0);
615
616 err:
617 bdx_close(ndev);
618 RET(rc);
619 }
620
621 static void __init bdx_firmware_endianess(void)
622 {
623 int i;
624 for (i = 0; i < ARRAY_SIZE(s_firmLoad); i++)
625 s_firmLoad[i] = CPU_CHIP_SWAP32(s_firmLoad[i]);
626 }
627
628 static int bdx_ioctl_priv(struct net_device *ndev, struct ifreq *ifr, int cmd)
629 {
630 struct bdx_priv *priv = ndev->priv;
631 u32 data[3];
632 int error;
633
634 ENTER;
635
636 DBG("jiffies=%ld cmd=%d\n", jiffies, cmd);
637 if (cmd != SIOCDEVPRIVATE) {
638 error = copy_from_user(data, ifr->ifr_data, sizeof(data));
639 if (error) {
640 ERR("cant copy from user\n");
641 RET(error);
642 }
643 DBG("%d 0x%x 0x%x\n", data[0], data[1], data[2]);
644 }
645
646 switch (data[0]) {
647
648 case BDX_OP_READ:
649 data[2] = READ_REG(priv, data[1]);
650 DBG("read_reg(0x%x)=0x%x (dec %d)\n", data[1], data[2],
651 data[2]);
652 error = copy_to_user(ifr->ifr_data, data, sizeof(data));
653 if (error)
654 RET(error);
655 break;
656
657 case BDX_OP_WRITE:
658 WRITE_REG(priv, data[1], data[2]);
659 DBG("write_reg(0x%x, 0x%x)\n", data[1], data[2]);
660 break;
661
662 default:
663 RET(-EOPNOTSUPP);
664 }
665 return 0;
666 }
667
668 static int bdx_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd)
669 {
670 ENTER;
671 if (cmd >= SIOCDEVPRIVATE && cmd <= (SIOCDEVPRIVATE + 15))
672 RET(bdx_ioctl_priv(ndev, ifr, cmd));
673 else
674 RET(-EOPNOTSUPP);
675 }
676
677 /*
678 * __bdx_vlan_rx_vid - private helper for adding/killing VLAN vid
679 * by passing VLAN filter table to hardware
680 * @ndev network device
681 * @vid VLAN vid
682 * @op add or kill operation
683 */
684 static void __bdx_vlan_rx_vid(struct net_device *ndev, uint16_t vid, int enable)
685 {
686 struct bdx_priv *priv = ndev->priv;
687 u32 reg, bit, val;
688
689 ENTER;
690 DBG2("vid=%d value=%d\n", (int)vid, enable);
691 if (unlikely(vid >= 4096)) {
692 ERR("tehuti: invalid VID: %u (> 4096)\n", vid);
693 RET();
694 }
695 reg = regVLAN_0 + (vid / 32) * 4;
696 bit = 1 << vid % 32;
697 val = READ_REG(priv, reg);
698 DBG2("reg=%x, val=%x, bit=%d\n", reg, val, bit);
699 if (enable)
700 val |= bit;
701 else
702 val &= ~bit;
703 DBG2("new val %x\n", val);
704 WRITE_REG(priv, reg, val);
705 RET();
706 }
707
708 /*
709 * bdx_vlan_rx_add_vid - kernel hook for adding VLAN vid to hw filtering table
710 * @ndev network device
711 * @vid VLAN vid to add
712 */
713 static void bdx_vlan_rx_add_vid(struct net_device *ndev, uint16_t vid)
714 {
715 __bdx_vlan_rx_vid(ndev, vid, 1);
716 }
717
718 /*
719 * bdx_vlan_rx_kill_vid - kernel hook for killing VLAN vid in hw filtering table
720 * @ndev network device
721 * @vid VLAN vid to kill
722 */
723 static void bdx_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
724 {
725 __bdx_vlan_rx_vid(ndev, vid, 0);
726 }
727
728 /*
729 * bdx_vlan_rx_register - kernel hook for adding VLAN group
730 * @ndev network device
731 * @grp VLAN group
732 */
733 static void
734 bdx_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
735 {
736 struct bdx_priv *priv = ndev->priv;
737
738 ENTER;
739 DBG("device='%s', group='%p'\n", ndev->name, grp);
740 priv->vlgrp = grp;
741 RET();
742 }
743
744 /**
745 * bdx_change_mtu - Change the Maximum Transfer Unit
746 * @netdev: network interface device structure
747 * @new_mtu: new value for maximum frame size
748 *
749 * Returns 0 on success, negative on failure
750 */
751 static int bdx_change_mtu(struct net_device *ndev, int new_mtu)
752 {
753 ENTER;
754
755 if (new_mtu == ndev->mtu)
756 RET(0);
757
758 /* enforce minimum frame size */
759 if (new_mtu < ETH_ZLEN) {
760 ERR("%s: %s mtu %d is less then minimal %d\n",
761 BDX_DRV_NAME, ndev->name, new_mtu, ETH_ZLEN);
762 RET(-EINVAL);
763 }
764
765 ndev->mtu = new_mtu;
766 if (netif_running(ndev)) {
767 bdx_close(ndev);
768 bdx_open(ndev);
769 }
770 RET(0);
771 }
772
773 static void bdx_setmulti(struct net_device *ndev)
774 {
775 struct bdx_priv *priv = ndev->priv;
776
777 u32 rxf_val =
778 GMAC_RX_FILTER_AM | GMAC_RX_FILTER_AB | GMAC_RX_FILTER_OSEN;
779 int i;
780
781 ENTER;
782 /* IMF - imperfect (hash) rx multicat filter */
783 /* PMF - perfect rx multicat filter */
784
785 /* FIXME: RXE(OFF) */
786 if (ndev->flags & IFF_PROMISC) {
787 rxf_val |= GMAC_RX_FILTER_PRM;
788 } else if (ndev->flags & IFF_ALLMULTI) {
789 /* set IMF to accept all multicast frmaes */
790 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
791 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, ~0);
792 } else if (ndev->mc_count) {
793 u8 hash;
794 struct dev_mc_list *mclist;
795 u32 reg, val;
796
797 /* set IMF to deny all multicast frames */
798 for (i = 0; i < MAC_MCST_HASH_NUM; i++)
799 WRITE_REG(priv, regRX_MCST_HASH0 + i * 4, 0);
800 /* set PMF to deny all multicast frames */
801 for (i = 0; i < MAC_MCST_NUM; i++) {
802 WRITE_REG(priv, regRX_MAC_MCST0 + i * 8, 0);
803 WRITE_REG(priv, regRX_MAC_MCST1 + i * 8, 0);
804 }
805
806 /* use PMF to accept first MAC_MCST_NUM (15) addresses */
807 /* TBD: sort addreses and write them in ascending order
808 * into RX_MAC_MCST regs. we skip this phase now and accept ALL
809 * multicast frames throu IMF */
810 mclist = ndev->mc_list;
811
812 /* accept the rest of addresses throu IMF */
813 for (; mclist; mclist = mclist->next) {
814 hash = 0;
815 for (i = 0; i < ETH_ALEN; i++)
816 hash ^= mclist->dmi_addr[i];
817 reg = regRX_MCST_HASH0 + ((hash >> 5) << 2);
818 val = READ_REG(priv, reg);
819 val |= (1 << (hash % 32));
820 WRITE_REG(priv, reg, val);
821 }
822
823 } else {
824 DBG("only own mac %d\n", ndev->mc_count);
825 rxf_val |= GMAC_RX_FILTER_AB;
826 }
827 WRITE_REG(priv, regGMAC_RXF_A, rxf_val);
828 /* enable RX */
829 /* FIXME: RXE(ON) */
830 RET();
831 }
832
833 static int bdx_set_mac(struct net_device *ndev, void *p)
834 {
835 struct bdx_priv *priv = ndev->priv;
836 struct sockaddr *addr = p;
837
838 ENTER;
839 /*
840 if (netif_running(dev))
841 return -EBUSY
842 */
843 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
844 bdx_restore_mac(ndev, priv);
845 RET(0);
846 }
847
848 static int bdx_read_mac(struct bdx_priv *priv)
849 {
850 u16 macAddress[3], i;
851 ENTER;
852
853 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
854 macAddress[2] = READ_REG(priv, regUNC_MAC0_A);
855 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
856 macAddress[1] = READ_REG(priv, regUNC_MAC1_A);
857 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
858 macAddress[0] = READ_REG(priv, regUNC_MAC2_A);
859 for (i = 0; i < 3; i++) {
860 priv->ndev->dev_addr[i * 2 + 1] = macAddress[i];
861 priv->ndev->dev_addr[i * 2] = macAddress[i] >> 8;
862 }
863 RET(0);
864 }
865
866 static u64 bdx_read_l2stat(struct bdx_priv *priv, int reg)
867 {
868 u64 val;
869
870 val = READ_REG(priv, reg);
871 val |= ((u64) READ_REG(priv, reg + 8)) << 32;
872 return val;
873 }
874
875 /*Do the statistics-update work*/
876 static void bdx_update_stats(struct bdx_priv *priv)
877 {
878 struct bdx_stats *stats = &priv->hw_stats;
879 u64 *stats_vector = (u64 *) stats;
880 int i;
881 int addr;
882
883 /*Fill HW structure */
884 addr = 0x7200;
885 /*First 12 statistics - 0x7200 - 0x72B0 */
886 for (i = 0; i < 12; i++) {
887 stats_vector[i] = bdx_read_l2stat(priv, addr);
888 addr += 0x10;
889 }
890 BDX_ASSERT(addr != 0x72C0);
891 /* 0x72C0-0x72E0 RSRV */
892 addr = 0x72F0;
893 for (; i < 16; i++) {
894 stats_vector[i] = bdx_read_l2stat(priv, addr);
895 addr += 0x10;
896 }
897 BDX_ASSERT(addr != 0x7330);
898 /* 0x7330-0x7360 RSRV */
899 addr = 0x7370;
900 for (; i < 19; i++) {
901 stats_vector[i] = bdx_read_l2stat(priv, addr);
902 addr += 0x10;
903 }
904 BDX_ASSERT(addr != 0x73A0);
905 /* 0x73A0-0x73B0 RSRV */
906 addr = 0x73C0;
907 for (; i < 23; i++) {
908 stats_vector[i] = bdx_read_l2stat(priv, addr);
909 addr += 0x10;
910 }
911 BDX_ASSERT(addr != 0x7400);
912 BDX_ASSERT((sizeof(struct bdx_stats) / sizeof(u64)) != i);
913 }
914
915 static struct net_device_stats *bdx_get_stats(struct net_device *ndev)
916 {
917 struct bdx_priv *priv = ndev->priv;
918 struct net_device_stats *net_stat = &priv->net_stats;
919 return net_stat;
920 }
921
922 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
923 u16 rxd_vlan);
924 static void print_rxfd(struct rxf_desc *rxfd);
925
926 /*************************************************************************
927 * Rx DB *
928 *************************************************************************/
929
930 static void bdx_rxdb_destroy(struct rxdb *db)
931 {
932 if (db)
933 vfree(db);
934 }
935
936 static struct rxdb *bdx_rxdb_create(int nelem)
937 {
938 struct rxdb *db;
939 int i;
940
941 db = vmalloc(sizeof(struct rxdb)
942 + (nelem * sizeof(int))
943 + (nelem * sizeof(struct rx_map)));
944 if (likely(db != NULL)) {
945 db->stack = (int *)(db + 1);
946 db->elems = (void *)(db->stack + nelem);
947 db->nelem = nelem;
948 db->top = nelem;
949 for (i = 0; i < nelem; i++)
950 db->stack[i] = nelem - i - 1; /* to make first allocs
951 close to db struct*/
952 }
953
954 return db;
955 }
956
957 static inline int bdx_rxdb_alloc_elem(struct rxdb *db)
958 {
959 BDX_ASSERT(db->top <= 0);
960 return db->stack[--(db->top)];
961 }
962
963 static inline void *bdx_rxdb_addr_elem(struct rxdb *db, int n)
964 {
965 BDX_ASSERT((n < 0) || (n >= db->nelem));
966 return db->elems + n;
967 }
968
969 static inline int bdx_rxdb_available(struct rxdb *db)
970 {
971 return db->top;
972 }
973
974 static inline void bdx_rxdb_free_elem(struct rxdb *db, int n)
975 {
976 BDX_ASSERT((n >= db->nelem) || (n < 0));
977 db->stack[(db->top)++] = n;
978 }
979
980 /*************************************************************************
981 * Rx Init *
982 *************************************************************************/
983
984 /* bdx_rx_init - initialize RX all related HW and SW resources
985 * @priv - NIC private structure
986 *
987 * Returns 0 on success, negative value on failure
988 *
989 * It creates rxf and rxd fifos, update relevant HW registers, preallocate
990 * skb for rx. It assumes that Rx is desabled in HW
991 * funcs are grouped for better cache usage
992 *
993 * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be
994 * filled and packets will be dropped by nic without getting into host or
995 * cousing interrupt. Anyway, in that condition, host has no chance to proccess
996 * all packets, but dropping in nic is cheaper, since it takes 0 cpu cycles
997 */
998
999 /* TBD: ensure proper packet size */
1000
1001 static int bdx_rx_init(struct bdx_priv *priv)
1002 {
1003 ENTER;
1004
1005 if (bdx_fifo_init(priv, &priv->rxd_fifo0.m, priv->rxd_size,
1006 regRXD_CFG0_0, regRXD_CFG1_0,
1007 regRXD_RPTR_0, regRXD_WPTR_0))
1008 goto err_mem;
1009 if (bdx_fifo_init(priv, &priv->rxf_fifo0.m, priv->rxf_size,
1010 regRXF_CFG0_0, regRXF_CFG1_0,
1011 regRXF_RPTR_0, regRXF_WPTR_0))
1012 goto err_mem;
1013 if (!
1014 (priv->rxdb =
1015 bdx_rxdb_create(priv->rxf_fifo0.m.memsz /
1016 sizeof(struct rxf_desc))))
1017 goto err_mem;
1018
1019 priv->rxf_fifo0.m.pktsz = priv->ndev->mtu + VLAN_ETH_HLEN;
1020 return 0;
1021
1022 err_mem:
1023 ERR("%s: %s: Rx init failed\n", BDX_DRV_NAME, priv->ndev->name);
1024 return -ENOMEM;
1025 }
1026
1027 /* bdx_rx_free_skbs - frees and unmaps all skbs allocated for the fifo
1028 * @priv - NIC private structure
1029 * @f - RXF fifo
1030 */
1031 static void bdx_rx_free_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1032 {
1033 struct rx_map *dm;
1034 struct rxdb *db = priv->rxdb;
1035 u16 i;
1036
1037 ENTER;
1038 DBG("total=%d free=%d busy=%d\n", db->nelem, bdx_rxdb_available(db),
1039 db->nelem - bdx_rxdb_available(db));
1040 while (bdx_rxdb_available(db) > 0) {
1041 i = bdx_rxdb_alloc_elem(db);
1042 dm = bdx_rxdb_addr_elem(db, i);
1043 dm->dma = 0;
1044 }
1045 for (i = 0; i < db->nelem; i++) {
1046 dm = bdx_rxdb_addr_elem(db, i);
1047 if (dm->dma) {
1048 pci_unmap_single(priv->pdev,
1049 dm->dma, f->m.pktsz,
1050 PCI_DMA_FROMDEVICE);
1051 dev_kfree_skb(dm->skb);
1052 }
1053 }
1054 }
1055
1056 /* bdx_rx_free - release all Rx resources
1057 * @priv - NIC private structure
1058 * It assumes that Rx is desabled in HW
1059 */
1060 static void bdx_rx_free(struct bdx_priv *priv)
1061 {
1062 ENTER;
1063 if (priv->rxdb) {
1064 bdx_rx_free_skbs(priv, &priv->rxf_fifo0);
1065 bdx_rxdb_destroy(priv->rxdb);
1066 priv->rxdb = NULL;
1067 }
1068 bdx_fifo_free(priv, &priv->rxf_fifo0.m);
1069 bdx_fifo_free(priv, &priv->rxd_fifo0.m);
1070
1071 RET();
1072 }
1073
1074 /*************************************************************************
1075 * Rx Engine *
1076 *************************************************************************/
1077
1078 /* bdx_rx_alloc_skbs - fill rxf fifo with new skbs
1079 * @priv - nic's private structure
1080 * @f - RXF fifo that needs skbs
1081 * It allocates skbs, build rxf descs and push it (rxf descr) into rxf fifo.
1082 * skb's virtual and physical addresses are stored in skb db.
1083 * To calculate free space, func uses cached values of RPTR and WPTR
1084 * When needed, it also updates RPTR and WPTR.
1085 */
1086
1087 /* TBD: do not update WPTR if no desc were written */
1088
1089 static void bdx_rx_alloc_skbs(struct bdx_priv *priv, struct rxf_fifo *f)
1090 {
1091 struct sk_buff *skb;
1092 struct rxf_desc *rxfd;
1093 struct rx_map *dm;
1094 int dno, delta, idx;
1095 struct rxdb *db = priv->rxdb;
1096
1097 ENTER;
1098 dno = bdx_rxdb_available(db) - 1;
1099 while (dno > 0) {
1100 if (!(skb = dev_alloc_skb(f->m.pktsz + NET_IP_ALIGN))) {
1101 ERR("NO MEM: dev_alloc_skb failed\n");
1102 break;
1103 }
1104 skb->dev = priv->ndev;
1105 skb_reserve(skb, NET_IP_ALIGN);
1106
1107 idx = bdx_rxdb_alloc_elem(db);
1108 dm = bdx_rxdb_addr_elem(db, idx);
1109 dm->dma = pci_map_single(priv->pdev,
1110 skb->data, f->m.pktsz,
1111 PCI_DMA_FROMDEVICE);
1112 dm->skb = skb;
1113 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1114 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1115 rxfd->va_lo = idx;
1116 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1117 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1118 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1119 print_rxfd(rxfd);
1120
1121 f->m.wptr += sizeof(struct rxf_desc);
1122 delta = f->m.wptr - f->m.memsz;
1123 if (unlikely(delta >= 0)) {
1124 f->m.wptr = delta;
1125 if (delta > 0) {
1126 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1127 DBG("wrapped descriptor\n");
1128 }
1129 }
1130 dno--;
1131 }
1132 /*TBD: to do - delayed rxf wptr like in txd */
1133 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1134 RET();
1135 }
1136
1137 static inline void
1138 NETIF_RX_MUX(struct bdx_priv *priv, u32 rxd_val1, u16 rxd_vlan,
1139 struct sk_buff *skb)
1140 {
1141 ENTER;
1142 DBG("rxdd->flags.bits.vtag=%d vlgrp=%p\n", GET_RXD_VTAG(rxd_val1),
1143 priv->vlgrp);
1144 if (priv->vlgrp && GET_RXD_VTAG(rxd_val1)) {
1145 DBG("%s: vlan rcv vlan '%x' vtag '%x', device name '%s'\n",
1146 priv->ndev->name,
1147 GET_RXD_VLAN_ID(rxd_vlan),
1148 GET_RXD_VTAG(rxd_val1),
1149 vlan_group_get_device(priv->vlgrp,
1150 GET_RXD_VLAN_ID(rxd_vlan))->name);
1151 /* NAPI variant of receive functions */
1152 vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1153 GET_RXD_VLAN_ID(rxd_vlan));
1154 } else {
1155 netif_receive_skb(skb);
1156 }
1157 }
1158
1159 static void bdx_recycle_skb(struct bdx_priv *priv, struct rxd_desc *rxdd)
1160 {
1161 struct rxf_desc *rxfd;
1162 struct rx_map *dm;
1163 struct rxf_fifo *f;
1164 struct rxdb *db;
1165 struct sk_buff *skb;
1166 int delta;
1167
1168 ENTER;
1169 DBG("priv=%p rxdd=%p\n", priv, rxdd);
1170 f = &priv->rxf_fifo0;
1171 db = priv->rxdb;
1172 DBG("db=%p f=%p\n", db, f);
1173 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1174 DBG("dm=%p\n", dm);
1175 skb = dm->skb;
1176 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr);
1177 rxfd->info = CPU_CHIP_SWAP32(0x10003); /* INFO=1 BC=3 */
1178 rxfd->va_lo = rxdd->va_lo;
1179 rxfd->pa_lo = CPU_CHIP_SWAP32(L32_64(dm->dma));
1180 rxfd->pa_hi = CPU_CHIP_SWAP32(H32_64(dm->dma));
1181 rxfd->len = CPU_CHIP_SWAP32(f->m.pktsz);
1182 print_rxfd(rxfd);
1183
1184 f->m.wptr += sizeof(struct rxf_desc);
1185 delta = f->m.wptr - f->m.memsz;
1186 if (unlikely(delta >= 0)) {
1187 f->m.wptr = delta;
1188 if (delta > 0) {
1189 memcpy(f->m.va, f->m.va + f->m.memsz, delta);
1190 DBG("wrapped descriptor\n");
1191 }
1192 }
1193 RET();
1194 }
1195
1196 /* bdx_rx_receive - recieves full packets from RXD fifo and pass them to OS
1197 * NOTE: a special treatment is given to non-continous descriptors
1198 * that start near the end, wraps around and continue at the beginning. a second
1199 * part is copied right after the first, and then descriptor is interpreted as
1200 * normal. fifo has an extra space to allow such operations
1201 * @priv - nic's private structure
1202 * @f - RXF fifo that needs skbs
1203 */
1204
1205 /* TBD: replace memcpy func call by explicite inline asm */
1206
1207 static int bdx_rx_receive(struct bdx_priv *priv, struct rxd_fifo *f, int budget)
1208 {
1209 struct sk_buff *skb, *skb2;
1210 struct rxd_desc *rxdd;
1211 struct rx_map *dm;
1212 struct rxf_fifo *rxf_fifo;
1213 int tmp_len, size;
1214 int done = 0;
1215 int max_done = BDX_MAX_RX_DONE;
1216 struct rxdb *db = NULL;
1217 /* Unmarshalled descriptor - copy of descriptor in host order */
1218 u32 rxd_val1;
1219 u16 len;
1220 u16 rxd_vlan;
1221
1222 ENTER;
1223 max_done = budget;
1224
1225 priv->ndev->last_rx = jiffies;
1226 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR;
1227
1228 size = f->m.wptr - f->m.rptr;
1229 if (size < 0)
1230 size = f->m.memsz + size; /* size is negative :-) */
1231
1232 while (size > 0) {
1233
1234 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr);
1235 rxd_val1 = CPU_CHIP_SWAP32(rxdd->rxd_val1);
1236
1237 len = CPU_CHIP_SWAP16(rxdd->len);
1238
1239 rxd_vlan = CPU_CHIP_SWAP16(rxdd->rxd_vlan);
1240
1241 print_rxdd(rxdd, rxd_val1, len, rxd_vlan);
1242
1243 tmp_len = GET_RXD_BC(rxd_val1) << 3;
1244 BDX_ASSERT(tmp_len <= 0);
1245 size -= tmp_len;
1246 if (size < 0) /* test for partially arrived descriptor */
1247 break;
1248
1249 f->m.rptr += tmp_len;
1250
1251 tmp_len = f->m.rptr - f->m.memsz;
1252 if (unlikely(tmp_len >= 0)) {
1253 f->m.rptr = tmp_len;
1254 if (tmp_len > 0) {
1255 DBG("wrapped desc rptr=%d tmp_len=%d\n",
1256 f->m.rptr, tmp_len);
1257 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len);
1258 }
1259 }
1260
1261 if (unlikely(GET_RXD_ERR(rxd_val1))) {
1262 DBG("rxd_err = 0x%x\n", GET_RXD_ERR(rxd_val1));
1263 priv->net_stats.rx_errors++;
1264 bdx_recycle_skb(priv, rxdd);
1265 continue;
1266 }
1267
1268 rxf_fifo = &priv->rxf_fifo0;
1269 db = priv->rxdb;
1270 dm = bdx_rxdb_addr_elem(db, rxdd->va_lo);
1271 skb = dm->skb;
1272
1273 if (len < BDX_COPYBREAK &&
1274 (skb2 = dev_alloc_skb(len + NET_IP_ALIGN))) {
1275 skb_reserve(skb2, NET_IP_ALIGN);
1276 /*skb_put(skb2, len); */
1277 pci_dma_sync_single_for_cpu(priv->pdev,
1278 dm->dma, rxf_fifo->m.pktsz,
1279 PCI_DMA_FROMDEVICE);
1280 memcpy(skb2->data, skb->data, len);
1281 bdx_recycle_skb(priv, rxdd);
1282 skb = skb2;
1283 } else {
1284 pci_unmap_single(priv->pdev,
1285 dm->dma, rxf_fifo->m.pktsz,
1286 PCI_DMA_FROMDEVICE);
1287 bdx_rxdb_free_elem(db, rxdd->va_lo);
1288 }
1289
1290 priv->net_stats.rx_bytes += len;
1291
1292 skb_put(skb, len);
1293 skb->dev = priv->ndev;
1294 skb->ip_summed = CHECKSUM_UNNECESSARY;
1295 skb->protocol = eth_type_trans(skb, priv->ndev);
1296
1297 /* Non-IP packets aren't checksum-offloaded */
1298 if (GET_RXD_PKT_ID(rxd_val1) == 0)
1299 skb->ip_summed = CHECKSUM_NONE;
1300
1301 NETIF_RX_MUX(priv, rxd_val1, rxd_vlan, skb);
1302
1303 if (++done >= max_done)
1304 break;
1305 }
1306
1307 priv->net_stats.rx_packets += done;
1308
1309 /* FIXME: do smth to minimize pci accesses */
1310 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1311
1312 bdx_rx_alloc_skbs(priv, &priv->rxf_fifo0);
1313
1314 RET(done);
1315 }
1316
1317 /*************************************************************************
1318 * Debug / Temprorary Code *
1319 *************************************************************************/
1320 static void print_rxdd(struct rxd_desc *rxdd, u32 rxd_val1, u16 len,
1321 u16 rxd_vlan)
1322 {
1323 DBG("ERROR: rxdd bc %d rxfq %d to %d type %d err %d rxp %d "
1324 "pkt_id %d vtag %d len %d vlan_id %d cfi %d prio %d "
1325 "va_lo %d va_hi %d\n",
1326 GET_RXD_BC(rxd_val1), GET_RXD_RXFQ(rxd_val1), GET_RXD_TO(rxd_val1),
1327 GET_RXD_TYPE(rxd_val1), GET_RXD_ERR(rxd_val1),
1328 GET_RXD_RXP(rxd_val1), GET_RXD_PKT_ID(rxd_val1),
1329 GET_RXD_VTAG(rxd_val1), len, GET_RXD_VLAN_ID(rxd_vlan),
1330 GET_RXD_CFI(rxd_vlan), GET_RXD_PRIO(rxd_vlan), rxdd->va_lo,
1331 rxdd->va_hi);
1332 }
1333
1334 static void print_rxfd(struct rxf_desc *rxfd)
1335 {
1336 DBG("=== RxF desc CHIP ORDER/ENDIANESS =============\n"
1337 "info 0x%x va_lo %u pa_lo 0x%x pa_hi 0x%x len 0x%x\n",
1338 rxfd->info, rxfd->va_lo, rxfd->pa_lo, rxfd->pa_hi, rxfd->len);
1339 }
1340
1341 /*
1342 * TX HW/SW interaction overview
1343 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1344 * There are 2 types of TX communication channels betwean driver and NIC.
1345 * 1) TX Free Fifo - TXF - holds ack descriptors for sent packets
1346 * 2) TX Data Fifo - TXD - holds descriptors of full buffers.
1347 *
1348 * Currently NIC supports TSO, checksuming and gather DMA
1349 * UFO and IP fragmentation is on the way
1350 *
1351 * RX SW Data Structures
1352 * ~~~~~~~~~~~~~~~~~~~~~
1353 * txdb - used to keep track of all skbs owned by SW and their dma addresses.
1354 * For TX case, ownership lasts from geting packet via hard_xmit and until HW
1355 * acknowledges sent by TXF descriptors.
1356 * Implemented as cyclic buffer.
1357 * fifo - keeps info about fifo's size and location, relevant HW registers,
1358 * usage and skb db. Each RXD and RXF Fifo has its own fifo structure.
1359 * Implemented as simple struct.
1360 *
1361 * TX SW Execution Flow
1362 * ~~~~~~~~~~~~~~~~~~~~
1363 * OS calls driver's hard_xmit method with packet to sent.
1364 * Driver creates DMA mappings, builds TXD descriptors and kicks HW
1365 * by updating TXD WPTR.
1366 * When packet is sent, HW write us TXF descriptor and SW frees original skb.
1367 * To prevent TXD fifo overflow without reading HW registers every time,
1368 * SW deploys "tx level" technique.
1369 * Upon strart up, tx level is initialized to TXD fifo length.
1370 * For every sent packet, SW gets its TXD descriptor sizei
1371 * (from precalculated array) and substructs it from tx level.
1372 * The size is also stored in txdb. When TXF ack arrives, SW fetch size of
1373 * original TXD descriptor from txdb and adds it to tx level.
1374 * When Tx level drops under some predefined treshhold, the driver
1375 * stops the TX queue. When TX level rises above that level,
1376 * the tx queue is enabled again.
1377 *
1378 * This technique avoids eccessive reading of RPTR and WPTR registers.
1379 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIS's throuput.
1380 */
1381
1382 /*************************************************************************
1383 * Tx DB *
1384 *************************************************************************/
1385 static inline int bdx_tx_db_size(struct txdb *db)
1386 {
1387 int taken = db->wptr - db->rptr;
1388 if (taken < 0)
1389 taken = db->size + 1 + taken; /* (size + 1) equals memsz */
1390
1391 return db->size - taken;
1392 }
1393
1394 /* __bdx_tx_ptr_next - helper function, increment read/write pointer + wrap
1395 * @d - tx data base
1396 * @ptr - read or write pointer
1397 */
1398 static inline void __bdx_tx_db_ptr_next(struct txdb *db, struct tx_map **pptr)
1399 {
1400 BDX_ASSERT(db == NULL || pptr == NULL); /* sanity */
1401
1402 BDX_ASSERT(*pptr != db->rptr && /* expect either read */
1403 *pptr != db->wptr); /* or write pointer */
1404
1405 BDX_ASSERT(*pptr < db->start || /* pointer has to be */
1406 *pptr >= db->end); /* in range */
1407
1408 ++*pptr;
1409 if (unlikely(*pptr == db->end))
1410 *pptr = db->start;
1411 }
1412
1413 /* bdx_tx_db_inc_rptr - increment read pointer
1414 * @d - tx data base
1415 */
1416 static inline void bdx_tx_db_inc_rptr(struct txdb *db)
1417 {
1418 BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */
1419 __bdx_tx_db_ptr_next(db, &db->rptr);
1420 }
1421
1422 /* bdx_tx_db_inc_rptr - increment write pointer
1423 * @d - tx data base
1424 */
1425 static inline void bdx_tx_db_inc_wptr(struct txdb *db)
1426 {
1427 __bdx_tx_db_ptr_next(db, &db->wptr);
1428 BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as
1429 a result of write */
1430 }
1431
1432 /* bdx_tx_db_init - creates and initializes tx db
1433 * @d - tx data base
1434 * @sz_type - size of tx fifo
1435 * Returns 0 on success, error code otherwise
1436 */
1437 static int bdx_tx_db_init(struct txdb *d, int sz_type)
1438 {
1439 int memsz = FIFO_SIZE * (1 << (sz_type + 1));
1440
1441 d->start = vmalloc(memsz);
1442 if (!d->start)
1443 return -ENOMEM;
1444
1445 /*
1446 * In order to differentiate between db is empty and db is full
1447 * states at least one element should always be empty in order to
1448 * avoid rptr == wptr which means db is empty
1449 */
1450 d->size = memsz / sizeof(struct tx_map) - 1;
1451 d->end = d->start + d->size + 1; /* just after last element */
1452
1453 /* all dbs are created equally empty */
1454 d->rptr = d->start;
1455 d->wptr = d->start;
1456
1457 return 0;
1458 }
1459
1460 /* bdx_tx_db_close - closes tx db and frees all memory
1461 * @d - tx data base
1462 */
1463 static void bdx_tx_db_close(struct txdb *d)
1464 {
1465 BDX_ASSERT(d == NULL);
1466
1467 if (d->start) {
1468 vfree(d->start);
1469 d->start = NULL;
1470 }
1471 }
1472
1473 /*************************************************************************
1474 * Tx Engine *
1475 *************************************************************************/
1476
1477 /* sizes of tx desc (including padding if needed) as function
1478 * of skb's frag number */
1479 static struct {
1480 u16 bytes;
1481 u16 qwords; /* qword = 64 bit */
1482 } txd_sizes[MAX_SKB_FRAGS + 1];
1483
1484 /* txdb_map_skb - creates and stores dma mappings for skb's data blocks
1485 * @priv - NIC private structure
1486 * @skb - socket buffer to map
1487 *
1488 * It makes dma mappings for skb's data blocks and writes them to PBL of
1489 * new tx descriptor. It also stores them in the tx db, so they could be
1490 * unmaped after data was sent. It is reponsibility of a caller to make
1491 * sure that there is enough space in the tx db. Last element holds pointer
1492 * to skb itself and marked with zero length
1493 */
1494 static inline void
1495 bdx_tx_map_skb(struct bdx_priv *priv, struct sk_buff *skb,
1496 struct txd_desc *txdd)
1497 {
1498 struct txdb *db = &priv->txdb;
1499 struct pbl *pbl = &txdd->pbl[0];
1500 int nr_frags = skb_shinfo(skb)->nr_frags;
1501 int i;
1502
1503 db->wptr->len = skb->len - skb->data_len;
1504 db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data,
1505 db->wptr->len, PCI_DMA_TODEVICE);
1506 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1507 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1508 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1509 DBG("=== pbl len: 0x%x ================\n", pbl->len);
1510 DBG("=== pbl pa_lo: 0x%x ================\n", pbl->pa_lo);
1511 DBG("=== pbl pa_hi: 0x%x ================\n", pbl->pa_hi);
1512 bdx_tx_db_inc_wptr(db);
1513
1514 for (i = 0; i < nr_frags; i++) {
1515 struct skb_frag_struct *frag;
1516
1517 frag = &skb_shinfo(skb)->frags[i];
1518 db->wptr->len = frag->size;
1519 db->wptr->addr.dma =
1520 pci_map_page(priv->pdev, frag->page, frag->page_offset,
1521 frag->size, PCI_DMA_TODEVICE);
1522
1523 pbl++;
1524 pbl->len = CPU_CHIP_SWAP32(db->wptr->len);
1525 pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma));
1526 pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma));
1527 bdx_tx_db_inc_wptr(db);
1528 }
1529
1530 /* add skb clean up info. */
1531 db->wptr->len = -txd_sizes[nr_frags].bytes;
1532 db->wptr->addr.skb = skb;
1533 bdx_tx_db_inc_wptr(db);
1534 }
1535
1536 /* init_txd_sizes - precalculate sizes of descriptors for skbs up to 16 frags
1537 * number of frags is used as index to fetch correct descriptors size,
1538 * instead of calculating it each time */
1539 static void __init init_txd_sizes(void)
1540 {
1541 int i, lwords;
1542
1543 /* 7 - is number of lwords in txd with one phys buffer
1544 * 3 - is number of lwords used for every additional phys buffer */
1545 for (i = 0; i < MAX_SKB_FRAGS + 1; i++) {
1546 lwords = 7 + (i * 3);
1547 if (lwords & 1)
1548 lwords++; /* pad it with 1 lword */
1549 txd_sizes[i].qwords = lwords >> 1;
1550 txd_sizes[i].bytes = lwords << 2;
1551 }
1552 }
1553
1554 /* bdx_tx_init - initialize all Tx related stuff.
1555 * Namely, TXD and TXF fifos, database etc */
1556 static int bdx_tx_init(struct bdx_priv *priv)
1557 {
1558 if (bdx_fifo_init(priv, &priv->txd_fifo0.m, priv->txd_size,
1559 regTXD_CFG0_0,
1560 regTXD_CFG1_0, regTXD_RPTR_0, regTXD_WPTR_0))
1561 goto err_mem;
1562 if (bdx_fifo_init(priv, &priv->txf_fifo0.m, priv->txf_size,
1563 regTXF_CFG0_0,
1564 regTXF_CFG1_0, regTXF_RPTR_0, regTXF_WPTR_0))
1565 goto err_mem;
1566
1567 /* The TX db has to keep mappings for all packets sent (on TxD)
1568 * and not yet reclaimed (on TxF) */
1569 if (bdx_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)))
1570 goto err_mem;
1571
1572 priv->tx_level = BDX_MAX_TX_LEVEL;
1573 #ifdef BDX_DELAY_WPTR
1574 priv->tx_update_mark = priv->tx_level - 1024;
1575 #endif
1576 return 0;
1577
1578 err_mem:
1579 ERR("tehuti: %s: Tx init failed\n", priv->ndev->name);
1580 return -ENOMEM;
1581 }
1582
1583 /*
1584 * bdx_tx_space - calculates avalable space in TX fifo
1585 * @priv - NIC private structure
1586 * Returns avaliable space in TX fifo in bytes
1587 */
1588 static inline int bdx_tx_space(struct bdx_priv *priv)
1589 {
1590 struct txd_fifo *f = &priv->txd_fifo0;
1591 int fsize;
1592
1593 f->m.rptr = READ_REG(priv, f->m.reg_RPTR) & TXF_WPTR_WR_PTR;
1594 fsize = f->m.rptr - f->m.wptr;
1595 if (fsize <= 0)
1596 fsize = f->m.memsz + fsize;
1597 return (fsize);
1598 }
1599
1600 /* bdx_tx_transmit - send packet to NIC
1601 * @skb - packet to send
1602 * ndev - network device assigned to NIC
1603 * Return codes:
1604 * o NETDEV_TX_OK everything ok.
1605 * o NETDEV_TX_BUSY Cannot transmit packet, try later
1606 * Usually a bug, means queue start/stop flow control is broken in
1607 * the driver. Note: the driver must NOT put the skb in its DMA ring.
1608 * o NETDEV_TX_LOCKED Locking failed, please retry quickly.
1609 */
1610 static int bdx_tx_transmit(struct sk_buff *skb, struct net_device *ndev)
1611 {
1612 struct bdx_priv *priv = ndev->priv;
1613 struct txd_fifo *f = &priv->txd_fifo0;
1614 int txd_checksum = 7; /* full checksum */
1615 int txd_lgsnd = 0;
1616 int txd_vlan_id = 0;
1617 int txd_vtag = 0;
1618 int txd_mss = 0;
1619
1620 int nr_frags = skb_shinfo(skb)->nr_frags;
1621 struct txd_desc *txdd;
1622 int len;
1623 unsigned long flags;
1624
1625 ENTER;
1626 local_irq_save(flags);
1627 if (!spin_trylock(&priv->tx_lock)) {
1628 local_irq_restore(flags);
1629 DBG("%s[%s]: TX locked, returning NETDEV_TX_LOCKED\n",
1630 BDX_DRV_NAME, ndev->name);
1631 return NETDEV_TX_LOCKED;
1632 }
1633
1634 /* build tx descriptor */
1635 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */
1636 txdd = (struct txd_desc *)(f->m.va + f->m.wptr);
1637 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL))
1638 txd_checksum = 0;
1639
1640 if (skb_shinfo(skb)->gso_size) {
1641 txd_mss = skb_shinfo(skb)->gso_size;
1642 txd_lgsnd = 1;
1643 DBG("skb %p skb len %d gso size = %d\n", skb, skb->len,
1644 txd_mss);
1645 }
1646
1647 if (vlan_tx_tag_present(skb)) {
1648 /*Cut VLAN ID to 12 bits */
1649 txd_vlan_id = vlan_tx_tag_get(skb) & BITS_MASK(12);
1650 txd_vtag = 1;
1651 }
1652
1653 txdd->length = CPU_CHIP_SWAP16(skb->len);
1654 txdd->mss = CPU_CHIP_SWAP16(txd_mss);
1655 txdd->txd_val1 =
1656 CPU_CHIP_SWAP32(TXD_W1_VAL
1657 (txd_sizes[nr_frags].qwords, txd_checksum, txd_vtag,
1658 txd_lgsnd, txd_vlan_id));
1659 DBG("=== TxD desc =====================\n");
1660 DBG("=== w1: 0x%x ================\n", txdd->txd_val1);
1661 DBG("=== w2: mss 0x%x len 0x%x\n", txdd->mss, txdd->length);
1662
1663 bdx_tx_map_skb(priv, skb, txdd);
1664
1665 /* increment TXD write pointer. In case of
1666 fifo wrapping copy reminder of the descriptor
1667 to the beginning */
1668 f->m.wptr += txd_sizes[nr_frags].bytes;
1669 len = f->m.wptr - f->m.memsz;
1670 if (unlikely(len >= 0)) {
1671 f->m.wptr = len;
1672 if (len > 0) {
1673 BDX_ASSERT(len > f->m.memsz);
1674 memcpy(f->m.va, f->m.va + f->m.memsz, len);
1675 }
1676 }
1677 BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */
1678
1679 priv->tx_level -= txd_sizes[nr_frags].bytes;
1680 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1681 #ifdef BDX_DELAY_WPTR
1682 if (priv->tx_level > priv->tx_update_mark) {
1683 /* Force memory writes to complete before letting h/w
1684 know there are new descriptors to fetch.
1685 (might be needed on platforms like IA64)
1686 wmb(); */
1687 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1688 } else {
1689 if (priv->tx_noupd++ > BDX_NO_UPD_PACKETS) {
1690 priv->tx_noupd = 0;
1691 WRITE_REG(priv, f->m.reg_WPTR,
1692 f->m.wptr & TXF_WPTR_WR_PTR);
1693 }
1694 }
1695 #else
1696 /* Force memory writes to complete before letting h/w
1697 know there are new descriptors to fetch.
1698 (might be needed on platforms like IA64)
1699 wmb(); */
1700 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1701
1702 #endif
1703 ndev->trans_start = jiffies;
1704
1705 priv->net_stats.tx_packets++;
1706 priv->net_stats.tx_bytes += skb->len;
1707
1708 if (priv->tx_level < BDX_MIN_TX_LEVEL) {
1709 DBG("%s: %s: TX Q STOP level %d\n",
1710 BDX_DRV_NAME, ndev->name, priv->tx_level);
1711 netif_stop_queue(ndev);
1712 }
1713
1714 spin_unlock_irqrestore(&priv->tx_lock, flags);
1715 return NETDEV_TX_OK;
1716 }
1717
1718 /* bdx_tx_cleanup - clean TXF fifo, run in the context of IRQ.
1719 * @priv - bdx adapter
1720 * It scans TXF fifo for descriptors, frees DMA mappings and reports to OS
1721 * that those packets were sent
1722 */
1723 static void bdx_tx_cleanup(struct bdx_priv *priv)
1724 {
1725 struct txf_fifo *f = &priv->txf_fifo0;
1726 struct txdb *db = &priv->txdb;
1727 int tx_level = 0;
1728
1729 ENTER;
1730 f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK;
1731 BDX_ASSERT(f->m.rptr >= f->m.memsz); /* started with valid rptr */
1732
1733 while (f->m.wptr != f->m.rptr) {
1734 f->m.rptr += BDX_TXF_DESC_SZ;
1735 f->m.rptr &= f->m.size_mask;
1736
1737 /* unmap all the fragments */
1738 /* first has to come tx_maps containing dma */
1739 BDX_ASSERT(db->rptr->len == 0);
1740 do {
1741 BDX_ASSERT(db->rptr->addr.dma == 0);
1742 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1743 db->rptr->len, PCI_DMA_TODEVICE);
1744 bdx_tx_db_inc_rptr(db);
1745 } while (db->rptr->len > 0);
1746 tx_level -= db->rptr->len; /* '-' koz len is negative */
1747
1748 /* now should come skb pointer - free it */
1749 dev_kfree_skb_irq(db->rptr->addr.skb);
1750 bdx_tx_db_inc_rptr(db);
1751 }
1752
1753 /* let h/w know which TXF descriptors were cleaned */
1754 BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz);
1755 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR);
1756
1757 /* We reclaimed resources, so in case the Q is stopped by xmit callback,
1758 * we resume the transmition and use tx_lock to synchronize with xmit.*/
1759 spin_lock(&priv->tx_lock);
1760 priv->tx_level += tx_level;
1761 BDX_ASSERT(priv->tx_level <= 0 || priv->tx_level > BDX_MAX_TX_LEVEL);
1762 #ifdef BDX_DELAY_WPTR
1763 if (priv->tx_noupd) {
1764 priv->tx_noupd = 0;
1765 WRITE_REG(priv, priv->txd_fifo0.m.reg_WPTR,
1766 priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR);
1767 }
1768 #endif
1769
1770 if (unlikely(netif_queue_stopped(priv->ndev)
1771 && netif_carrier_ok(priv->ndev)
1772 && (priv->tx_level >= BDX_MIN_TX_LEVEL))) {
1773 DBG("%s: %s: TX Q WAKE level %d\n",
1774 BDX_DRV_NAME, priv->ndev->name, priv->tx_level);
1775 netif_wake_queue(priv->ndev);
1776 }
1777 spin_unlock(&priv->tx_lock);
1778 }
1779
1780 /* bdx_tx_free_skbs - frees all skbs from TXD fifo.
1781 * It gets called when OS stops this dev, eg upon "ifconfig down" or rmmod
1782 */
1783 static void bdx_tx_free_skbs(struct bdx_priv *priv)
1784 {
1785 struct txdb *db = &priv->txdb;
1786
1787 ENTER;
1788 while (db->rptr != db->wptr) {
1789 if (likely(db->rptr->len))
1790 pci_unmap_page(priv->pdev, db->rptr->addr.dma,
1791 db->rptr->len, PCI_DMA_TODEVICE);
1792 else
1793 dev_kfree_skb(db->rptr->addr.skb);
1794 bdx_tx_db_inc_rptr(db);
1795 }
1796 RET();
1797 }
1798
1799 /* bdx_tx_free - frees all Tx resources */
1800 static void bdx_tx_free(struct bdx_priv *priv)
1801 {
1802 ENTER;
1803 bdx_tx_free_skbs(priv);
1804 bdx_fifo_free(priv, &priv->txd_fifo0.m);
1805 bdx_fifo_free(priv, &priv->txf_fifo0.m);
1806 bdx_tx_db_close(&priv->txdb);
1807 }
1808
1809 /* bdx_tx_push_desc - push descriptor to TxD fifo
1810 * @priv - NIC private structure
1811 * @data - desc's data
1812 * @size - desc's size
1813 *
1814 * Pushes desc to TxD fifo and overlaps it if needed.
1815 * NOTE: this func does not check for available space. this is responsibility
1816 * of the caller. Neither does it check that data size is smaller then
1817 * fifo size.
1818 */
1819 static void bdx_tx_push_desc(struct bdx_priv *priv, void *data, int size)
1820 {
1821 struct txd_fifo *f = &priv->txd_fifo0;
1822 int i = f->m.memsz - f->m.wptr;
1823
1824 if (size == 0)
1825 return;
1826
1827 if (i > size) {
1828 memcpy(f->m.va + f->m.wptr, data, size);
1829 f->m.wptr += size;
1830 } else {
1831 memcpy(f->m.va + f->m.wptr, data, i);
1832 f->m.wptr = size - i;
1833 memcpy(f->m.va, data + i, f->m.wptr);
1834 }
1835 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR);
1836 }
1837
1838 /* bdx_tx_push_desc_safe - push descriptor to TxD fifo in a safe way
1839 * @priv - NIC private structure
1840 * @data - desc's data
1841 * @size - desc's size
1842 *
1843 * NOTE: this func does check for available space and, if neccessary, waits for
1844 * NIC to read existing data before writing new one.
1845 */
1846 static void bdx_tx_push_desc_safe(struct bdx_priv *priv, void *data, int size)
1847 {
1848 int timer = 0;
1849 ENTER;
1850
1851 while (size > 0) {
1852 /* we substruct 8 because when fifo is full rptr == wptr
1853 which also means that fifo is empty, we can understand
1854 the difference, but could hw do the same ??? :) */
1855 int avail = bdx_tx_space(priv) - 8;
1856 if (avail <= 0) {
1857 if (timer++ > 300) { /* prevent endless loop */
1858 DBG("timeout while writing desc to TxD fifo\n");
1859 break;
1860 }
1861 udelay(50); /* give hw a chance to clean fifo */
1862 continue;
1863 }
1864 avail = MIN(avail, size);
1865 DBG("about to push %d bytes starting %p size %d\n", avail,
1866 data, size);
1867 bdx_tx_push_desc(priv, data, avail);
1868 size -= avail;
1869 data += avail;
1870 }
1871 RET();
1872 }
1873
1874 /**
1875 * bdx_probe - Device Initialization Routine
1876 * @pdev: PCI device information struct
1877 * @ent: entry in bdx_pci_tbl
1878 *
1879 * Returns 0 on success, negative on failure
1880 *
1881 * bdx_probe initializes an adapter identified by a pci_dev structure.
1882 * The OS initialization, configuring of the adapter private structure,
1883 * and a hardware reset occur.
1884 *
1885 * functions and their order used as explained in
1886 * /usr/src/linux/Documentation/DMA-{API,mapping}.txt
1887 *
1888 */
1889
1890 /* TBD: netif_msg should be checked and implemented. I disable it for now */
1891 static int __devinit
1892 bdx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1893 {
1894 struct net_device *ndev;
1895 struct bdx_priv *priv;
1896 int err, pci_using_dac, port;
1897 unsigned long pciaddr;
1898 u32 regionSize;
1899 struct pci_nic *nic;
1900
1901 ENTER;
1902
1903 nic = vmalloc(sizeof(*nic));
1904 if (!nic)
1905 RET(-ENOMEM);
1906
1907 /************** pci *****************/
1908 if ((err = pci_enable_device(pdev))) /* it trigers interrupt, dunno why. */
1909 goto err_pci; /* it's not a problem though */
1910
1911 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
1912 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1913 pci_using_dac = 1;
1914 } else {
1915 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) ||
1916 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1917 printk(KERN_ERR "tehuti: No usable DMA configuration"
1918 ", aborting\n");
1919 goto err_dma;
1920 }
1921 pci_using_dac = 0;
1922 }
1923
1924 if ((err = pci_request_regions(pdev, BDX_DRV_NAME)))
1925 goto err_dma;
1926
1927 pci_set_master(pdev);
1928
1929 pciaddr = pci_resource_start(pdev, 0);
1930 if (!pciaddr) {
1931 err = -EIO;
1932 ERR("tehuti: no MMIO resource\n");
1933 goto err_out_res;
1934 }
1935 if ((regionSize = pci_resource_len(pdev, 0)) < BDX_REGS_SIZE) {
1936 err = -EIO;
1937 ERR("tehuti: MMIO resource (%x) too small\n", regionSize);
1938 goto err_out_res;
1939 }
1940
1941 nic->regs = ioremap(pciaddr, regionSize);
1942 if (!nic->regs) {
1943 err = -EIO;
1944 ERR("tehuti: ioremap failed\n");
1945 goto err_out_res;
1946 }
1947
1948 if (pdev->irq < 2) {
1949 err = -EIO;
1950 ERR("tehuti: invalid irq (%d)\n", pdev->irq);
1951 goto err_out_iomap;
1952 }
1953 pci_set_drvdata(pdev, nic);
1954
1955 if (pdev->device == 0x3014)
1956 nic->port_num = 2;
1957 else
1958 nic->port_num = 1;
1959
1960 print_hw_id(pdev);
1961
1962 bdx_hw_reset_direct(nic->regs);
1963
1964 nic->irq_type = IRQ_INTX;
1965 #ifdef BDX_MSI
1966 if ((readl(nic->regs + FPGA_VER) & 0xFFF) >= 378) {
1967 if ((err = pci_enable_msi(pdev)))
1968 ERR("Tehuti: Can't eneble msi. error is %d\n", err);
1969 else
1970 nic->irq_type = IRQ_MSI;
1971 } else
1972 DBG("HW does not support MSI\n");
1973 #endif
1974
1975 /************** netdev **************/
1976 for (port = 0; port < nic->port_num; port++) {
1977 if (!(ndev = alloc_etherdev(sizeof(struct bdx_priv)))) {
1978 err = -ENOMEM;
1979 printk(KERN_ERR "tehuti: alloc_etherdev failed\n");
1980 goto err_out_iomap;
1981 }
1982
1983 ndev->open = bdx_open;
1984 ndev->stop = bdx_close;
1985 ndev->hard_start_xmit = bdx_tx_transmit;
1986 ndev->do_ioctl = bdx_ioctl;
1987 ndev->set_multicast_list = bdx_setmulti;
1988 ndev->get_stats = bdx_get_stats;
1989 ndev->change_mtu = bdx_change_mtu;
1990 ndev->set_mac_address = bdx_set_mac;
1991 ndev->tx_queue_len = BDX_NDEV_TXQ_LEN;
1992 ndev->vlan_rx_register = bdx_vlan_rx_register;
1993 ndev->vlan_rx_add_vid = bdx_vlan_rx_add_vid;
1994 ndev->vlan_rx_kill_vid = bdx_vlan_rx_kill_vid;
1995
1996 bdx_ethtool_ops(ndev); /* ethtool interface */
1997
1998 /* these fields are used for info purposes only
1999 * so we can have them same for all ports of the board */
2000 ndev->if_port = port;
2001 ndev->base_addr = pciaddr;
2002 ndev->mem_start = pciaddr;
2003 ndev->mem_end = pciaddr + regionSize;
2004 ndev->irq = pdev->irq;
2005 ndev->features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO
2006 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
2007 NETIF_F_HW_VLAN_FILTER
2008 /*| NETIF_F_FRAGLIST */
2009 ;
2010
2011 if (pci_using_dac)
2012 ndev->features |= NETIF_F_HIGHDMA;
2013
2014 /************** priv ****************/
2015 priv = nic->priv[port] = ndev->priv;
2016
2017 memset(priv, 0, sizeof(struct bdx_priv));
2018 priv->pBdxRegs = nic->regs + port * 0x8000;
2019 priv->port = port;
2020 priv->pdev = pdev;
2021 priv->ndev = ndev;
2022 priv->nic = nic;
2023 priv->msg_enable = BDX_DEF_MSG_ENABLE;
2024
2025 netif_napi_add(ndev, &priv->napi, bdx_poll, 64);
2026
2027 if ((readl(nic->regs + FPGA_VER) & 0xFFF) == 308) {
2028 DBG("HW statistics not supported\n");
2029 priv->stats_flag = 0;
2030 } else {
2031 priv->stats_flag = 1;
2032 }
2033
2034 /* Initialize fifo sizes. */
2035 priv->txd_size = 2;
2036 priv->txf_size = 2;
2037 priv->rxd_size = 2;
2038 priv->rxf_size = 3;
2039
2040 /* Initialize the initial coalescing registers. */
2041 priv->rdintcm = INT_REG_VAL(0x20, 1, 4, 12);
2042 priv->tdintcm = INT_REG_VAL(0x20, 1, 0, 12);
2043
2044 /* ndev->xmit_lock spinlock is not used.
2045 * Private priv->tx_lock is used for synchronization
2046 * between transmit and TX irq cleanup. In addition
2047 * set multicast list callback has to use priv->tx_lock.
2048 */
2049 #ifdef BDX_LLTX
2050 ndev->features |= NETIF_F_LLTX;
2051 #endif
2052 spin_lock_init(&priv->tx_lock);
2053
2054 /*bdx_hw_reset(priv); */
2055 if (bdx_read_mac(priv)) {
2056 printk(KERN_ERR "tehuti: load MAC address failed\n");
2057 goto err_out_iomap;
2058 }
2059 SET_NETDEV_DEV(ndev, &pdev->dev);
2060 if ((err = register_netdev(ndev))) {
2061 printk(KERN_ERR "tehuti: register_netdev failed\n");
2062 goto err_out_free;
2063 }
2064 netif_carrier_off(ndev);
2065 netif_stop_queue(ndev);
2066
2067 print_eth_id(ndev);
2068 }
2069 RET(0);
2070
2071 err_out_free:
2072 free_netdev(ndev);
2073 err_out_iomap:
2074 iounmap(nic->regs);
2075 err_out_res:
2076 pci_release_regions(pdev);
2077 err_dma:
2078 pci_disable_device(pdev);
2079 err_pci:
2080 vfree(nic);
2081
2082 RET(err);
2083 }
2084
2085 /****************** Ethtool interface *********************/
2086 /* get strings for tests */
2087 static const char
2088 bdx_test_names[][ETH_GSTRING_LEN] = {
2089 "No tests defined"
2090 };
2091
2092 /* get strings for statistics counters */
2093 static const char
2094 bdx_stat_names[][ETH_GSTRING_LEN] = {
2095 "InUCast", /* 0x7200 */
2096 "InMCast", /* 0x7210 */
2097 "InBCast", /* 0x7220 */
2098 "InPkts", /* 0x7230 */
2099 "InErrors", /* 0x7240 */
2100 "InDropped", /* 0x7250 */
2101 "FrameTooLong", /* 0x7260 */
2102 "FrameSequenceErrors", /* 0x7270 */
2103 "InVLAN", /* 0x7280 */
2104 "InDroppedDFE", /* 0x7290 */
2105 "InDroppedIntFull", /* 0x72A0 */
2106 "InFrameAlignErrors", /* 0x72B0 */
2107
2108 /* 0x72C0-0x72E0 RSRV */
2109
2110 "OutUCast", /* 0x72F0 */
2111 "OutMCast", /* 0x7300 */
2112 "OutBCast", /* 0x7310 */
2113 "OutPkts", /* 0x7320 */
2114
2115 /* 0x7330-0x7360 RSRV */
2116
2117 "OutVLAN", /* 0x7370 */
2118 "InUCastOctects", /* 0x7380 */
2119 "OutUCastOctects", /* 0x7390 */
2120
2121 /* 0x73A0-0x73B0 RSRV */
2122
2123 "InBCastOctects", /* 0x73C0 */
2124 "OutBCastOctects", /* 0x73D0 */
2125 "InOctects", /* 0x73E0 */
2126 "OutOctects", /* 0x73F0 */
2127 };
2128
2129 /*
2130 * bdx_get_settings - get device-specific settings
2131 * @netdev
2132 * @ecmd
2133 */
2134 static int bdx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
2135 {
2136 u32 rdintcm;
2137 u32 tdintcm;
2138 struct bdx_priv *priv = netdev->priv;
2139
2140 rdintcm = priv->rdintcm;
2141 tdintcm = priv->tdintcm;
2142
2143 ecmd->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
2144 ecmd->advertising = (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
2145 ecmd->speed = SPEED_10000;
2146 ecmd->duplex = DUPLEX_FULL;
2147 ecmd->port = PORT_FIBRE;
2148 ecmd->transceiver = XCVR_EXTERNAL; /* what does it mean? */
2149 ecmd->autoneg = AUTONEG_DISABLE;
2150
2151 /* PCK_TH measures in multiples of FIFO bytes
2152 We translate to packets */
2153 ecmd->maxtxpkt =
2154 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2155 ecmd->maxrxpkt =
2156 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2157
2158 return 0;
2159 }
2160
2161 /*
2162 * bdx_get_drvinfo - report driver information
2163 * @netdev
2164 * @drvinfo
2165 */
2166 static void
2167 bdx_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
2168 {
2169 struct bdx_priv *priv = netdev->priv;
2170
2171 strlcat(drvinfo->driver, BDX_DRV_NAME, sizeof(drvinfo->driver));
2172 strlcat(drvinfo->version, BDX_DRV_VERSION, sizeof(drvinfo->version));
2173 strlcat(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
2174 strlcat(drvinfo->bus_info, pci_name(priv->pdev),
2175 sizeof(drvinfo->bus_info));
2176
2177 drvinfo->n_stats = ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
2178 drvinfo->testinfo_len = 0;
2179 drvinfo->regdump_len = 0;
2180 drvinfo->eedump_len = 0;
2181 }
2182
2183 /*
2184 * bdx_get_rx_csum - report whether receive checksums are turned on or off
2185 * @netdev
2186 */
2187 static u32 bdx_get_rx_csum(struct net_device *netdev)
2188 {
2189 return 1; /* always on */
2190 }
2191
2192 /*
2193 * bdx_get_tx_csum - report whether transmit checksums are turned on or off
2194 * @netdev
2195 */
2196 static u32 bdx_get_tx_csum(struct net_device *netdev)
2197 {
2198 return (netdev->features & NETIF_F_IP_CSUM) != 0;
2199 }
2200
2201 /*
2202 * bdx_get_coalesce - get interrupt coalescing parameters
2203 * @netdev
2204 * @ecoal
2205 */
2206 static int
2207 bdx_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2208 {
2209 u32 rdintcm;
2210 u32 tdintcm;
2211 struct bdx_priv *priv = netdev->priv;
2212
2213 rdintcm = priv->rdintcm;
2214 tdintcm = priv->tdintcm;
2215
2216 /* PCK_TH measures in multiples of FIFO bytes
2217 We translate to packets */
2218 ecoal->rx_coalesce_usecs = GET_INT_COAL(rdintcm) * INT_COAL_MULT;
2219 ecoal->rx_max_coalesced_frames =
2220 ((GET_PCK_TH(rdintcm) * PCK_TH_MULT) / sizeof(struct rxf_desc));
2221
2222 ecoal->tx_coalesce_usecs = GET_INT_COAL(tdintcm) * INT_COAL_MULT;
2223 ecoal->tx_max_coalesced_frames =
2224 ((GET_PCK_TH(tdintcm) * PCK_TH_MULT) / BDX_TXF_DESC_SZ);
2225
2226 /* adaptive parameters ignored */
2227 return 0;
2228 }
2229
2230 /*
2231 * bdx_set_coalesce - set interrupt coalescing parameters
2232 * @netdev
2233 * @ecoal
2234 */
2235 static int
2236 bdx_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecoal)
2237 {
2238 u32 rdintcm;
2239 u32 tdintcm;
2240 struct bdx_priv *priv = netdev->priv;
2241 int rx_coal;
2242 int tx_coal;
2243 int rx_max_coal;
2244 int tx_max_coal;
2245
2246 /* Check for valid input */
2247 rx_coal = ecoal->rx_coalesce_usecs / INT_COAL_MULT;
2248 tx_coal = ecoal->tx_coalesce_usecs / INT_COAL_MULT;
2249 rx_max_coal = ecoal->rx_max_coalesced_frames;
2250 tx_max_coal = ecoal->tx_max_coalesced_frames;
2251
2252 /* Translate from packets to multiples of FIFO bytes */
2253 rx_max_coal =
2254 (((rx_max_coal * sizeof(struct rxf_desc)) + PCK_TH_MULT - 1)
2255 / PCK_TH_MULT);
2256 tx_max_coal =
2257 (((tx_max_coal * BDX_TXF_DESC_SZ) + PCK_TH_MULT - 1)
2258 / PCK_TH_MULT);
2259
2260 if ((rx_coal > 0x7FFF) || (tx_coal > 0x7FFF)
2261 || (rx_max_coal > 0xF) || (tx_max_coal > 0xF))
2262 return -EINVAL;
2263
2264 rdintcm = INT_REG_VAL(rx_coal, GET_INT_COAL_RC(priv->rdintcm),
2265 GET_RXF_TH(priv->rdintcm), rx_max_coal);
2266 tdintcm = INT_REG_VAL(tx_coal, GET_INT_COAL_RC(priv->tdintcm), 0,
2267 tx_max_coal);
2268
2269 priv->rdintcm = rdintcm;
2270 priv->tdintcm = tdintcm;
2271
2272 WRITE_REG(priv, regRDINTCM0, rdintcm);
2273 WRITE_REG(priv, regTDINTCM0, tdintcm);
2274
2275 return 0;
2276 }
2277
2278 /* Convert RX fifo size to number of pending packets */
2279 static inline int bdx_rx_fifo_size_to_packets(int rx_size)
2280 {
2281 return ((FIFO_SIZE * (1 << rx_size)) / sizeof(struct rxf_desc));
2282 }
2283
2284 /* Convert TX fifo size to number of pending packets */
2285 static inline int bdx_tx_fifo_size_to_packets(int tx_size)
2286 {
2287 return ((FIFO_SIZE * (1 << tx_size)) / BDX_TXF_DESC_SZ);
2288 }
2289
2290 /*
2291 * bdx_get_ringparam - report ring sizes
2292 * @netdev
2293 * @ring
2294 */
2295 static void
2296 bdx_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2297 {
2298 struct bdx_priv *priv = netdev->priv;
2299
2300 /*max_pending - the maximum-sized FIFO we allow */
2301 ring->rx_max_pending = bdx_rx_fifo_size_to_packets(3);
2302 ring->tx_max_pending = bdx_tx_fifo_size_to_packets(3);
2303 ring->rx_pending = bdx_rx_fifo_size_to_packets(priv->rxf_size);
2304 ring->tx_pending = bdx_tx_fifo_size_to_packets(priv->txd_size);
2305 }
2306
2307 /*
2308 * bdx_set_ringparam - set ring sizes
2309 * @netdev
2310 * @ring
2311 */
2312 static int
2313 bdx_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
2314 {
2315 struct bdx_priv *priv = netdev->priv;
2316 int rx_size = 0;
2317 int tx_size = 0;
2318
2319 for (; rx_size < 4; rx_size++) {
2320 if (bdx_rx_fifo_size_to_packets(rx_size) >= ring->rx_pending)
2321 break;
2322 }
2323 if (rx_size == 4)
2324 rx_size = 3;
2325
2326 for (; tx_size < 4; tx_size++) {
2327 if (bdx_tx_fifo_size_to_packets(tx_size) >= ring->tx_pending)
2328 break;
2329 }
2330 if (tx_size == 4)
2331 tx_size = 3;
2332
2333 /*Is there anything to do? */
2334 if ((rx_size == priv->rxf_size)
2335 && (tx_size == priv->txd_size))
2336 return 0;
2337
2338 priv->rxf_size = rx_size;
2339 if (rx_size > 1)
2340 priv->rxd_size = rx_size - 1;
2341 else
2342 priv->rxd_size = rx_size;
2343
2344 priv->txf_size = priv->txd_size = tx_size;
2345
2346 if (netif_running(netdev)) {
2347 bdx_close(netdev);
2348 bdx_open(netdev);
2349 }
2350 return 0;
2351 }
2352
2353 /*
2354 * bdx_get_strings - return a set of strings that describe the requested objects
2355 * @netdev
2356 * @data
2357 */
2358 static void bdx_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2359 {
2360 switch (stringset) {
2361 case ETH_SS_TEST:
2362 memcpy(data, *bdx_test_names, sizeof(bdx_test_names));
2363 break;
2364 case ETH_SS_STATS:
2365 memcpy(data, *bdx_stat_names, sizeof(bdx_stat_names));
2366 break;
2367 }
2368 }
2369
2370 /*
2371 * bdx_get_stats_count - return number of 64bit statistics counters
2372 * @netdev
2373 */
2374 static int bdx_get_stats_count(struct net_device *netdev)
2375 {
2376 struct bdx_priv *priv = netdev->priv;
2377 BDX_ASSERT(ARRAY_SIZE(bdx_stat_names)
2378 != sizeof(struct bdx_stats) / sizeof(u64));
2379 return ((priv->stats_flag) ? ARRAY_SIZE(bdx_stat_names) : 0);
2380 }
2381
2382 /*
2383 * bdx_get_ethtool_stats - return device's hardware L2 statistics
2384 * @netdev
2385 * @stats
2386 * @data
2387 */
2388 static void bdx_get_ethtool_stats(struct net_device *netdev,
2389 struct ethtool_stats *stats, u64 *data)
2390 {
2391 struct bdx_priv *priv = netdev->priv;
2392
2393 if (priv->stats_flag) {
2394
2395 /* Update stats from HW */
2396 bdx_update_stats(priv);
2397
2398 /* Copy data to user buffer */
2399 memcpy(data, &priv->hw_stats, sizeof(priv->hw_stats));
2400 }
2401 }
2402
2403 /*
2404 * bdx_ethtool_ops - ethtool interface implementation
2405 * @netdev
2406 */
2407 static void bdx_ethtool_ops(struct net_device *netdev)
2408 {
2409 static struct ethtool_ops bdx_ethtool_ops = {
2410 .get_settings = bdx_get_settings,
2411 .get_drvinfo = bdx_get_drvinfo,
2412 .get_link = ethtool_op_get_link,
2413 .get_coalesce = bdx_get_coalesce,
2414 .set_coalesce = bdx_set_coalesce,
2415 .get_ringparam = bdx_get_ringparam,
2416 .set_ringparam = bdx_set_ringparam,
2417 .get_rx_csum = bdx_get_rx_csum,
2418 .get_tx_csum = bdx_get_tx_csum,
2419 .get_sg = ethtool_op_get_sg,
2420 .get_tso = ethtool_op_get_tso,
2421 .get_strings = bdx_get_strings,
2422 .get_stats_count = bdx_get_stats_count,
2423 .get_ethtool_stats = bdx_get_ethtool_stats,
2424 };
2425
2426 SET_ETHTOOL_OPS(netdev, &bdx_ethtool_ops);
2427 }
2428
2429 /**
2430 * bdx_remove - Device Removal Routine
2431 * @pdev: PCI device information struct
2432 *
2433 * bdx_remove is called by the PCI subsystem to alert the driver
2434 * that it should release a PCI device. The could be caused by a
2435 * Hot-Plug event, or because the driver is going to be removed from
2436 * memory.
2437 **/
2438 static void __devexit bdx_remove(struct pci_dev *pdev)
2439 {
2440 struct pci_nic *nic = pci_get_drvdata(pdev);
2441 struct net_device *ndev;
2442 int port;
2443
2444 for (port = 0; port < nic->port_num; port++) {
2445 ndev = nic->priv[port]->ndev;
2446 unregister_netdev(ndev);
2447 free_netdev(ndev);
2448 }
2449
2450 /*bdx_hw_reset_direct(nic->regs); */
2451 #ifdef BDX_MSI
2452 if (nic->irq_type == IRQ_MSI)
2453 pci_disable_msi(pdev);
2454 #endif
2455
2456 iounmap(nic->regs);
2457 pci_release_regions(pdev);
2458 pci_disable_device(pdev);
2459 pci_set_drvdata(pdev, NULL);
2460 vfree(nic);
2461
2462 RET();
2463 }
2464
2465 static struct pci_driver bdx_pci_driver = {
2466 .name = BDX_DRV_NAME,
2467 .id_table = bdx_pci_tbl,
2468 .probe = bdx_probe,
2469 .remove = __devexit_p(bdx_remove),
2470 };
2471
2472 /*
2473 * print_driver_id - print parameters of the driver build
2474 */
2475 static void __init print_driver_id(void)
2476 {
2477 printk(KERN_INFO "%s: %s, %s\n", BDX_DRV_NAME, BDX_DRV_DESC,
2478 BDX_DRV_VERSION);
2479 printk(KERN_INFO "%s: Options: hw_csum %s\n", BDX_DRV_NAME,
2480 BDX_MSI_STRING);
2481 }
2482
2483 static int __init bdx_module_init(void)
2484 {
2485 ENTER;
2486 bdx_firmware_endianess();
2487 init_txd_sizes();
2488 print_driver_id();
2489 RET(pci_register_driver(&bdx_pci_driver));
2490 }
2491
2492 module_init(bdx_module_init);
2493
2494 static void __exit bdx_module_exit(void)
2495 {
2496 ENTER;
2497 pci_unregister_driver(&bdx_pci_driver);
2498 RET();
2499 }
2500
2501 module_exit(bdx_module_exit);
2502
2503 MODULE_LICENSE("GPL");
2504 MODULE_AUTHOR(DRIVER_AUTHOR);
2505 MODULE_DESCRIPTION(BDX_DRV_DESC);
WRT350N Kernel Patches