drivers/net/wireless/ath5k/ath5k.h

   1 /*
   2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _ATH5K_H
  19 #define _ATH5K_H
  20
  21 /* Set this to 1 to disable regulatory domain restrictions for channel tests.
  22  * WARNING: This is for debuging only and has side effects (eg. scan takes too
  23  * long and results timeouts). It's also illegal to tune to some of the
  24  * supported frequencies in some countries, so use this at your own risk,
  25  * you've been warned. */
  26 #define CHAN_DEBUG      0
  27
  28 #include <linux/io.h>
  29 #include <linux/types.h>
  30 #include <net/mac80211.h>
  31
  32 #include "hw.h"
  33 #include "regdom.h"
  34
  35 /* PCI IDs */
  36 #define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
  37 #define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
  38 #define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
  39 #define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
  40 #define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
  41 #define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
  42 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
  43 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
  44 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
  45 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
  46 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
  47 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
  48 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
  49 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
  50 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
  51 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
  52 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
  53 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
  54 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
  55 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
  56 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
  57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
  58 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
  59 #define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
  60 #define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
  61 #define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
  62 #define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
  63 #define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
  64
  65 /****************************\
  66   GENERIC DRIVER DEFINITIONS
  67 \****************************/
  68
  69 #define ATH5K_PRINTF(fmt, ...)   printk("%s: " fmt, __func__, ##__VA_ARGS__)
  70
  71 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
  72         printk(_level "ath5k %s: " _fmt, \
  73                 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
  74                 ##__VA_ARGS__)
  75
  76 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
  77         if (net_ratelimit()) \
  78                 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
  79         } while (0)
  80
  81 #define ATH5K_INFO(_sc, _fmt, ...) \
  82         ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
  83
  84 #define ATH5K_WARN(_sc, _fmt, ...) \
  85         ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
  86
  87 #define ATH5K_ERR(_sc, _fmt, ...) \
  88         ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
  89
  90 /*
  91  * Some tuneable values (these should be changeable by the user)
  92  */
  93 #define AR5K_TUNE_DMA_BEACON_RESP               2
  94 #define AR5K_TUNE_SW_BEACON_RESP                10
  95 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
  96 #define AR5K_TUNE_RADAR_ALERT                   false
  97 #define AR5K_TUNE_MIN_TX_FIFO_THRES             1
  98 #define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
  99 #define AR5K_TUNE_REGISTER_TIMEOUT              20000
 100 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
 101  * be the max value. */
 102 #define AR5K_TUNE_RSSI_THRES                   129
 103 /* This must be set when setting the RSSI threshold otherwise it can
 104  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
 105  * the BMISS_THRES will be seen as 0, seems harware doesn't keep
 106  * track of it. Max value depends on harware. For AR5210 this is just 7.
 107  * For AR5211+ this seems to be up to 255. */
 108 #define AR5K_TUNE_BMISS_THRES                  7
 109 #define AR5K_TUNE_REGISTER_DWELL_TIME           20000
 110 #define AR5K_TUNE_BEACON_INTERVAL               100
 111 #define AR5K_TUNE_AIFS                          2
 112 #define AR5K_TUNE_AIFS_11B                      2
 113 #define AR5K_TUNE_AIFS_XR                       0
 114 #define AR5K_TUNE_CWMIN                         15
 115 #define AR5K_TUNE_CWMIN_11B                     31
 116 #define AR5K_TUNE_CWMIN_XR                      3
 117 #define AR5K_TUNE_CWMAX                         1023
 118 #define AR5K_TUNE_CWMAX_11B                     1023
 119 #define AR5K_TUNE_CWMAX_XR                      7
 120 #define AR5K_TUNE_NOISE_FLOOR                   -72
 121 #define AR5K_TUNE_MAX_TXPOWER                   60
 122 #define AR5K_TUNE_DEFAULT_TXPOWER               30
 123 #define AR5K_TUNE_TPC_TXPOWER                   true
 124 #define AR5K_TUNE_ANT_DIVERSITY                 true
 125 #define AR5K_TUNE_HWTXTRIES                     4
 126
 127 /* token to use for aifs, cwmin, cwmax in MadWiFi */
 128 #define AR5K_TXQ_USEDEFAULT     ((u32) -1)
 129
 130 /* GENERIC CHIPSET DEFINITIONS */
 131
 132 /* MAC Chips */
 133 enum ath5k_version {
 134         AR5K_AR5210     = 0,
 135         AR5K_AR5211     = 1,
 136         AR5K_AR5212     = 2,
 137 };
 138
 139 /* PHY Chips */
 140 enum ath5k_radio {
 141         AR5K_RF5110     = 0,
 142         AR5K_RF5111     = 1,
 143         AR5K_RF5112     = 2,
 144         AR5K_RF5413     = 3,
 145 };
 146
 147 /*
 148  * Common silicon revision/version values
 149  */
 150
 151 enum ath5k_srev_type {
 152         AR5K_VERSION_VER,
 153         AR5K_VERSION_RAD,
 154 };
 155
 156 struct ath5k_srev_name {
 157         const char              *sr_name;
 158         enum ath5k_srev_type    sr_type;
 159         u_int                   sr_val;
 160 };
 161
 162 #define AR5K_SREV_UNKNOWN       0xffff
 163
 164 #define AR5K_SREV_VER_AR5210    0x00
 165 #define AR5K_SREV_VER_AR5311    0x10
 166 #define AR5K_SREV_VER_AR5311A   0x20
 167 #define AR5K_SREV_VER_AR5311B   0x30
 168 #define AR5K_SREV_VER_AR5211    0x40
 169 #define AR5K_SREV_VER_AR5212    0x50
 170 #define AR5K_SREV_VER_AR5213    0x55
 171 #define AR5K_SREV_VER_AR5213A   0x59
 172 #define AR5K_SREV_VER_AR2424    0xa0
 173 #define AR5K_SREV_VER_AR5424    0xa3
 174 #define AR5K_SREV_VER_AR5413    0xa4
 175 #define AR5K_SREV_VER_AR5414    0xa5
 176 #define AR5K_SREV_VER_AR5416    0xc0    /* ? */
 177 #define AR5K_SREV_VER_AR5418    0xca
 178
 179 #define AR5K_SREV_RAD_5110      0x00
 180 #define AR5K_SREV_RAD_5111      0x10
 181 #define AR5K_SREV_RAD_5111A     0x15
 182 #define AR5K_SREV_RAD_2111      0x20
 183 #define AR5K_SREV_RAD_5112      0x30
 184 #define AR5K_SREV_RAD_5112A     0x35
 185 #define AR5K_SREV_RAD_2112      0x40
 186 #define AR5K_SREV_RAD_2112A     0x45
 187 #define AR5K_SREV_RAD_SC1       0x63    /* Found on 5413/5414 */
 188 #define AR5K_SREV_RAD_SC2       0xa2    /* Found on 2424/5424 */
 189 #define AR5K_SREV_RAD_5133      0xc0    /* MIMO found on 5418 */
 190
 191 /* IEEE defs */
 192
 193 #define IEEE80211_MAX_LEN       2500
 194
 195 /* TODO add support to mac80211 for vendor-specific rates and modes */
 196
 197 /*
 198  * Some of this information is based on Documentation from:
 199  *
 200  * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
 201  *
 202  * Modulation for Atheros' eXtended Range - range enhancing extension that is
 203  * supposed to double the distance an Atheros client device can keep a
 204  * connection with an Atheros access point. This is achieved by increasing
 205  * the receiver sensitivity up to, -105dBm, which is about 20dB above what
 206  * the 802.11 specifications demand. In addition, new (proprietary) data rates
 207  * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
 208  *
 209  * Please note that can you either use XR or TURBO but you cannot use both,
 210  * they are exclusive.
 211  *
 212  */
 213 #define MODULATION_XR           0x00000200
 214 /*
 215  * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
 216  * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
 217  * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
 218  * channels. To use this feature your Access Point must also suport it.
 219  * There is also a distinction between "static" and "dynamic" turbo modes:
 220  *
 221  * - Static: is the dumb version: devices set to this mode stick to it until
 222  *     the mode is turned off.
 223  * - Dynamic: is the intelligent version, the network decides itself if it
 224  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
 225  *     (which would get used in turbo mode), or when a non-turbo station joins
 226  *     the network, turbo mode won't be used until the situation changes again.
 227  *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
 228  *     monitors the used radio band in order to decide whether turbo mode may
 229  *     be used or not.
 230  *
 231  * This article claims Super G sticks to bonding of channels 5 and 6 for
 232  * USA:
 233  *
 234  * http://www.pcworld.com/article/id,113428-page,1/article.html
 235  *
 236  * The channel bonding seems to be driver specific though. In addition to
 237  * deciding what channels will be used, these "Turbo" modes are accomplished
 238  * by also enabling the following features:
 239  *
 240  * - Bursting: allows multiple frames to be sent at once, rather than pausing
 241  *     after each frame. Bursting is a standards-compliant feature that can be
 242  *     used with any Access Point.
 243  * - Fast frames: increases the amount of information that can be sent per
 244  *     frame, also resulting in a reduction of transmission overhead. It is a
 245  *     proprietary feature that needs to be supported by the Access Point.
 246  * - Compression: data frames are compressed in real time using a Lempel Ziv
 247  *     algorithm. This is done transparently. Once this feature is enabled,
 248  *     compression and decompression takes place inside the chipset, without
 249  *     putting additional load on the host CPU.
 250  *
 251  */
 252 #define MODULATION_TURBO        0x00000080
 253
 254 enum ath5k_vendor_mode {
 255         MODE_ATHEROS_TURBO = NUM_IEEE80211_MODES+1,
 256         MODE_ATHEROS_TURBOG
 257 };
 258
 259 /* Number of supported mac80211 enum ieee80211_phymode modes by this driver */
 260 #define NUM_DRIVER_MODES        3
 261
 262 /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */
 263 #define AR5K_SET_SHORT_PREAMBLE 0x04
 264
 265 #define HAS_SHPREAMBLE(_ix) (rt->rates[_ix].modulation == IEEE80211_RATE_CCK_2)
 266 #define SHPREAMBLE_FLAG(_ix) (HAS_SHPREAMBLE(_ix) ? AR5K_SET_SHORT_PREAMBLE : 0)
 267
 268 /****************\
 269   TX DEFINITIONS
 270 \****************/
 271
 272 /*
 273  * Tx Descriptor
 274  */
 275 struct ath5k_tx_status {
 276         u16     ts_seqnum;
 277         u16     ts_tstamp;
 278         u8      ts_status;
 279         u8      ts_rate;
 280         s8      ts_rssi;
 281         u8      ts_shortretry;
 282         u8      ts_longretry;
 283         u8      ts_virtcol;
 284         u8      ts_antenna;
 285 };
 286
 287 #define AR5K_TXSTAT_ALTRATE     0x80
 288 #define AR5K_TXERR_XRETRY       0x01
 289 #define AR5K_TXERR_FILT         0x02
 290 #define AR5K_TXERR_FIFO         0x04
 291
 292 /**
 293  * enum ath5k_tx_queue - Queue types used to classify tx queues.
 294  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
 295  * @AR5K_TX_QUEUE_DATA: A normal data queue
 296  * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
 297  * @AR5K_TX_QUEUE_BEACON: The beacon queue
 298  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
 299  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
 300  */
 301 enum ath5k_tx_queue {
 302         AR5K_TX_QUEUE_INACTIVE = 0,
 303         AR5K_TX_QUEUE_DATA,
 304         AR5K_TX_QUEUE_XR_DATA,
 305         AR5K_TX_QUEUE_BEACON,
 306         AR5K_TX_QUEUE_CAB,
 307         AR5K_TX_QUEUE_UAPSD,
 308 };
 309
 310 #define AR5K_NUM_TX_QUEUES              10
 311 #define AR5K_NUM_TX_QUEUES_NOQCU        2
 312
 313 /*
 314  * Queue syb-types to classify normal data queues.
 315  * These are the 4 Access Categories as defined in
 316  * WME spec. 0 is the lowest priority and 4 is the
 317  * highest. Normal data that hasn't been classified
 318  * goes to the Best Effort AC.
 319  */
 320 enum ath5k_tx_queue_subtype {
 321         AR5K_WME_AC_BK = 0,     /*Background traffic*/
 322         AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
 323         AR5K_WME_AC_VI,         /*Video traffic*/
 324         AR5K_WME_AC_VO,         /*Voice traffic*/
 325 };
 326
 327 /*
 328  * Queue ID numbers as returned by the hw functions, each number
 329  * represents a hw queue. If hw does not support hw queues
 330  * (eg 5210) all data goes in one queue. These match
 331  * d80211 definitions (net80211/MadWiFi don't use them).
 332  */
 333 enum ath5k_tx_queue_id {
 334         AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
 335         AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
 336         AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
 337         AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
 338         AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
 339         AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
 340         AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
 341         AR5K_TX_QUEUE_ID_UAPSD          = 8,
 342         AR5K_TX_QUEUE_ID_XR_DATA        = 9,
 343 };
 344
 345
 346 /*
 347  * Flags to set hw queue's parameters...
 348  */
 349 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
 350 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
 351 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
 352 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
 353 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
 354 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0020  /* Disable random post-backoff */
 355 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040  /* Enable ready time expiry policy (?)*/
 356 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080  /* Enable backoff while bursting */
 357 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x0100  /* Disable backoff while bursting */
 358 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x0200  /* Enable hw compression -not implemented-*/
 359
 360 /*
 361  * A struct to hold tx queue's parameters
 362  */
 363 struct ath5k_txq_info {
 364         enum ath5k_tx_queue tqi_type;
 365         enum ath5k_tx_queue_subtype tqi_subtype;
 366         u16     tqi_flags;      /* Tx queue flags (see above) */
 367         u32     tqi_aifs;       /* Arbitrated Interframe Space */
 368         s32     tqi_cw_min;     /* Minimum Contention Window */
 369         s32     tqi_cw_max;     /* Maximum Contention Window */
 370         u32     tqi_cbr_period; /* Constant bit rate period */
 371         u32     tqi_cbr_overflow_limit;
 372         u32     tqi_burst_time;
 373         u32     tqi_ready_time; /* Not used */
 374 };
 375
 376 /*
 377  * Transmit packet types.
 378  * These are not fully used inside OpenHAL yet
 379  */
 380 enum ath5k_pkt_type {
 381         AR5K_PKT_TYPE_NORMAL            = 0,
 382         AR5K_PKT_TYPE_ATIM              = 1,
 383         AR5K_PKT_TYPE_PSPOLL            = 2,
 384         AR5K_PKT_TYPE_BEACON            = 3,
 385         AR5K_PKT_TYPE_PROBE_RESP        = 4,
 386         AR5K_PKT_TYPE_PIFS              = 5,
 387 };
 388
 389 /*
 390  * TX power and TPC settings
 391  */
 392 #define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
 393         ((0 & 1) << ((_v) + 6)) |                               \
 394         (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v))     \
 395 )
 396
 397 #define AR5K_TXPOWER_CCK(_r, _v)        (                       \
 398         (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
 399 )
 400
 401 /*
 402  * DMA size definitions (2^n+2)
 403  */
 404 enum ath5k_dmasize {
 405         AR5K_DMASIZE_4B = 0,
 406         AR5K_DMASIZE_8B,
 407         AR5K_DMASIZE_16B,
 408         AR5K_DMASIZE_32B,
 409         AR5K_DMASIZE_64B,
 410         AR5K_DMASIZE_128B,
 411         AR5K_DMASIZE_256B,
 412         AR5K_DMASIZE_512B
 413 };
 414
 415
 416 /****************\
 417   RX DEFINITIONS
 418 \****************/
 419
 420 /*
 421  * Rx Descriptor
 422  */
 423 struct ath5k_rx_status {
 424         u16     rs_datalen;
 425         u16     rs_tstamp;
 426         u8      rs_status;
 427         u8      rs_phyerr;
 428         s8      rs_rssi;
 429         u8      rs_keyix;
 430         u8      rs_rate;
 431         u8      rs_antenna;
 432         u8      rs_more;
 433 };
 434
 435 #define AR5K_RXERR_CRC          0x01
 436 #define AR5K_RXERR_PHY          0x02
 437 #define AR5K_RXERR_FIFO         0x04
 438 #define AR5K_RXERR_DECRYPT      0x08
 439 #define AR5K_RXERR_MIC          0x10
 440 #define AR5K_RXKEYIX_INVALID    ((u8) - 1)
 441 #define AR5K_TXKEYIX_INVALID    ((u32) - 1)
 442
 443 struct ath5k_mib_stats {
 444         u32     ackrcv_bad;
 445         u32     rts_bad;
 446         u32     rts_good;
 447         u32     fcs_bad;
 448         u32     beacons;
 449 };
 450
 451
 452
 453
 454 /**************************\
 455  BEACON TIMERS DEFINITIONS
 456 \**************************/
 457
 458 #define AR5K_BEACON_PERIOD      0x0000ffff
 459 #define AR5K_BEACON_ENA         0x00800000 /*enable beacon xmit*/
 460 #define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
 461
 462 #if 0
 463 /**
 464  * struct ath5k_beacon_state - Per-station beacon timer state.
 465  * @bs_interval: in TU's, can also include the above flags
 466  * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
 467  *      Point Coordination Function capable AP
 468  */
 469 struct ath5k_beacon_state {
 470         u32     bs_next_beacon;
 471         u32     bs_next_dtim;
 472         u32     bs_interval;
 473         u8      bs_dtim_period;
 474         u8      bs_cfp_period;
 475         u16     bs_cfp_max_duration;
 476         u16     bs_cfp_du_remain;
 477         u16     bs_tim_offset;
 478         u16     bs_sleep_duration;
 479         u16     bs_bmiss_threshold;
 480         u32     bs_cfp_next;
 481 };
 482 #endif
 483
 484
 485 /*
 486  * TSF to TU conversion:
 487  *
 488  * TSF is a 64bit value in usec (microseconds).
 489  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
 490  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
 491  */
 492 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
 493
 494
 495
 496 /********************\
 497   COMMON DEFINITIONS
 498 \********************/
 499
 500 /*
 501  * Atheros descriptor
 502  */
 503 struct ath5k_desc {
 504         u32     ds_link;
 505         u32     ds_data;
 506         u32     ds_ctl0;
 507         u32     ds_ctl1;
 508         u32     ds_hw[4];
 509
 510         union {
 511                 struct ath5k_rx_status rx;
 512                 struct ath5k_tx_status tx;
 513         } ds_us;
 514
 515 #define ds_rxstat ds_us.rx
 516 #define ds_txstat ds_us.tx
 517
 518 } __packed;
 519
 520 #define AR5K_RXDESC_INTREQ      0x0020
 521
 522 #define AR5K_TXDESC_CLRDMASK    0x0001
 523 #define AR5K_TXDESC_NOACK       0x0002  /*[5211+]*/
 524 #define AR5K_TXDESC_RTSENA      0x0004
 525 #define AR5K_TXDESC_CTSENA      0x0008
 526 #define AR5K_TXDESC_INTREQ      0x0010
 527 #define AR5K_TXDESC_VEOL        0x0020  /*[5211+]*/
 528
 529 #define AR5K_SLOT_TIME_9        396
 530 #define AR5K_SLOT_TIME_20       880
 531 #define AR5K_SLOT_TIME_MAX      0xffff
 532
 533 /* channel_flags */
 534 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
 535 #define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 536 #define CHANNEL_CCK     0x0020  /* CCK channel */
 537 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 538 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
 539 #define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
 540 #define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
 541 #define CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
 542 #define CHANNEL_XR      0x0800  /* XR channel */
 543
 544 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 545 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 546 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
 547 #define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 548 #define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
 549 #define CHANNEL_108A    CHANNEL_T
 550 #define CHANNEL_108G    CHANNEL_TG
 551 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 552
 553 #define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
 554                 CHANNEL_TURBO)
 555
 556 #define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 557 #define CHANNEL_MODES           CHANNEL_ALL
 558
 559 /*
 560  * Used internaly in OpenHAL (ar5211.c/ar5212.c
 561  * for reset_tx_queue). Also see struct struct ieee80211_channel.
 562  */
 563 #define IS_CHAN_XR(_c)  ((_c.val & CHANNEL_XR) != 0)
 564 #define IS_CHAN_B(_c)   ((_c.val & CHANNEL_B) != 0)
 565
 566 /*
 567  * The following structure will be used to map 2GHz channels to
 568  * 5GHz Atheros channels.
 569  */
 570 struct ath5k_athchan_2ghz {
 571         u32     a2_flags;
 572         u16     a2_athchan;
 573 };
 574
 575 /*
 576  * Rate definitions
 577  * TODO: Clean them up or move them on mac80211 -most of these infos are
 578  *       used by the rate control algorytm on MadWiFi.
 579  */
 580
 581 /* Max number of rates on the rate table and what it seems
 582  * Atheros hardware supports */
 583 #define AR5K_MAX_RATES 32
 584
 585 /**
 586  * struct ath5k_rate - rate structure
 587  * @valid: is this a valid rate for the current mode
 588  * @modulation: respective mac80211 modulation
 589  * @rate_kbps: rate in kbit/s
 590  * @rate_code: hardware rate value, used in &struct ath5k_desc, on RX on
 591  *     &struct ath5k_rx_status.rs_rate and on TX on
 592  *     &struct ath5k_tx_status.ts_rate. Seems the ar5xxx harware supports
 593  *     up to 32 rates, indexed by 1-32. This means we really only need
 594  *     6 bits for the rate_code.
 595  * @dot11_rate: respective IEEE-802.11 rate value
 596  * @control_rate: index of rate assumed to be used to send control frames.
 597  *     This can be used to set override the value on the rate duration
 598  *     registers. This is only useful if we can override in the harware at
 599  *     what rate we want to send control frames at. Note that IEEE-802.11
 600  *     Ch. 9.6 (after IEEE 802.11g changes) defines the rate at which we
 601  *     should send ACK/CTS, if we change this value we can be breaking
 602  *     the spec.
 603  *
 604  * This structure is used to get the RX rate or set the TX rate on the
 605  * hardware descriptors. It is also used for internal modulation control
 606  * and settings.
 607  *
 608  * On RX after the &struct ath5k_desc is parsed by the appropriate
 609  * ah_proc_rx_desc() the respective hardware rate value is set in
 610  * &struct ath5k_rx_status.rs_rate. On TX the desired rate is set in
 611  * &struct ath5k_tx_status.ts_rate which is later used to setup the
 612  * &struct ath5k_desc correctly. This is the hardware rate map we are
 613  * aware of:
 614  *
 615  * rate_code   1       2       3       4       5       6       7       8
 616  * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
 617  *
 618  * rate_code   9       10      11      12      13      14      15      16
 619  * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
 620  *
 621  * rate_code   17      18      19      20      21      22      23      24
 622  * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
 623  *
 624  * rate_code   25      26      27      28      29      30      31      32
 625  * rate_kbps   5500    2000    1000    ?       ?       ?       ?       ?
 626  *
 627  */
 628 struct ath5k_rate {
 629         u8      valid;
 630         u32     modulation;
 631         u16     rate_kbps;
 632         u8      rate_code;
 633         u8      dot11_rate;
 634         u8      control_rate;
 635 };
 636
 637 /* XXX: GRR all this stuff to get leds blinking ??? (check out setcurmode) */
 638 struct ath5k_rate_table {
 639         u16     rate_count;
 640         u8      rate_code_to_index[AR5K_MAX_RATES];     /* Back-mapping */
 641         struct ath5k_rate rates[AR5K_MAX_RATES];
 642 };
 643
 644 /*
 645  * Rate tables...
 646  */
 647 #define AR5K_RATES_11A { 8, {                                   \
 648         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 649         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 650         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 651         { 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 0 },           \
 652         { 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 0 },            \
 653         { 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 2 },          \
 654         { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 2 },           \
 655         { 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 4 },           \
 656         { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 4 },           \
 657         { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 4 },            \
 658         { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 4 } }         \
 659 }
 660
 661 #define AR5K_RATES_11B { 4, {                                           \
 662         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 663         255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,     \
 664         3, 2, 1, 0, 255, 255, 255, 255 }, {                             \
 665         { 1, IEEE80211_RATE_CCK, 1000, 27, 130, 0 },    \
 666         { 1, IEEE80211_RATE_CCK_2, 2000, 26, 132, 1 },  \
 667         { 1, IEEE80211_RATE_CCK_2, 5500, 25, 139, 1 },  \
 668         { 1, IEEE80211_RATE_CCK_2, 11000, 24, 150, 1 } }        \
 669 }
 670
 671 #define AR5K_RATES_11G { 12, {                                  \
 672         255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4,    \
 673         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 674         3, 2, 1, 0, 255, 255, 255, 255 }, {                     \
 675         { 1, IEEE80211_RATE_CCK, 1000, 27, 2, 0 },              \
 676         { 1, IEEE80211_RATE_CCK_2, 2000, 26, 4, 1 },            \
 677         { 1, IEEE80211_RATE_CCK_2, 5500, 25, 11, 1 },           \
 678         { 1, IEEE80211_RATE_CCK_2, 11000, 24, 22, 1 },  \
 679         { 0, IEEE80211_RATE_OFDM, 6000, 11, 12, 4 },    \
 680         { 0, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 },    \
 681         { 1, IEEE80211_RATE_OFDM, 12000, 10, 24, 6 },   \
 682         { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 },   \
 683         { 1, IEEE80211_RATE_OFDM, 24000, 9, 48, 8 },    \
 684         { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 },   \
 685         { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 },    \
 686         { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \
 687 }
 688
 689 #define AR5K_RATES_TURBO { 8, {                                 \
 690         255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0,     \
 691         7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255,     \
 692         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 693         { 1, MODULATION_TURBO, 6000, 11, 140, 0 },      \
 694         { 1, MODULATION_TURBO, 9000, 15, 18, 0 },       \
 695         { 1, MODULATION_TURBO, 12000, 10, 152, 2 },     \
 696         { 1, MODULATION_TURBO, 18000, 14, 36, 2 },      \
 697         { 1, MODULATION_TURBO, 24000, 9, 176, 4 },      \
 698         { 1, MODULATION_TURBO, 36000, 13, 72, 4 },      \
 699         { 1, MODULATION_TURBO, 48000, 8, 96, 4 },       \
 700         { 1, MODULATION_TURBO, 54000, 12, 108, 4 } }    \
 701 }
 702
 703 #define AR5K_RATES_XR { 12, {                                   \
 704         255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4,            \
 705         11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255,    \
 706         255, 255, 255, 255, 255, 255, 255, 255 }, {             \
 707         { 1, MODULATION_XR, 500, 7, 129, 0 },           \
 708         { 1, MODULATION_XR, 1000, 2, 139, 1 },          \
 709         { 1, MODULATION_XR, 2000, 6, 150, 2 },          \
 710         { 1, MODULATION_XR, 3000, 1, 150, 3 },          \
 711         { 1, IEEE80211_RATE_OFDM, 6000, 11, 140, 4 },   \
 712         { 1, IEEE80211_RATE_OFDM, 9000, 15, 18, 4 },    \
 713         { 1, IEEE80211_RATE_OFDM, 12000, 10, 152, 6 },  \
 714         { 1, IEEE80211_RATE_OFDM, 18000, 14, 36, 6 },   \
 715         { 1, IEEE80211_RATE_OFDM, 24000, 9, 176, 8 },   \
 716         { 1, IEEE80211_RATE_OFDM, 36000, 13, 72, 8 },   \
 717         { 1, IEEE80211_RATE_OFDM, 48000, 8, 96, 8 },    \
 718         { 1, IEEE80211_RATE_OFDM, 54000, 12, 108, 8 } } \
 719 }
 720
 721 /*
 722  * Crypto definitions
 723  */
 724
 725 #define AR5K_KEYCACHE_SIZE      8
 726
 727 /***********************\
 728  HW RELATED DEFINITIONS
 729 \***********************/
 730
 731 /*
 732  * Misc definitions
 733  */
 734 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
 735
 736 #define AR5K_ASSERT_ENTRY(_e, _s) do {          \
 737         if (_e >= _s)                           \
 738                 return (false);                 \
 739 } while (0)
 740
 741
 742 enum ath5k_ant_setting {
 743         AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
 744         AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
 745         AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
 746         AR5K_ANT_MAX            = 3,
 747 };
 748
 749 /*
 750  * Hardware interrupt abstraction
 751  */
 752
 753 /**
 754  * enum ath5k_int - Hardware interrupt masks helpers
 755  *
 756  * @AR5K_INT_RX: mask to identify received frame interrupts, of type
 757  *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
 758  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
 759  * @AR5K_INT_RXNOFRM: No frame received (?)
 760  * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
 761  *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
 762  *      LinkPtr is NULL. For more details, refer to:
 763  *      http://www.freepatentsonline.com/20030225739.html
 764  * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
 765  *      Note that Rx overrun is not always fatal, on some chips we can continue
 766  *      operation without reseting the card, that's why int_fatal is not
 767  *      common for all chips.
 768  * @AR5K_INT_TX: mask to identify received frame interrupts, of type
 769  *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
 770  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
 771  * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
 772  *      We currently do increments on interrupt by
 773  *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
 774  * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
 775  *      checked. We should do this with ath5k_hw_update_mib_counters() but
 776  *      it seems we should also then do some noise immunity work.
 777  * @AR5K_INT_RXPHY: RX PHY Error
 778  * @AR5K_INT_RXKCM: ??
 779  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
 780  *      beacon that must be handled in software. The alternative is if you
 781  *      have VEOL support, in that case you let the hardware deal with things.
 782  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
 783  *      beacons from the AP have associated with, we should probably try to
 784  *      reassociate. When in IBSS mode this might mean we have not received
 785  *      any beacons from any local stations. Note that every station in an
 786  *      IBSS schedules to send beacons at the Target Beacon Transmission Time
 787  *      (TBTT) with a random backoff.
 788  * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
 789  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
 790  *      until properly handled
 791  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
 792  *      errors. These types of errors we can enable seem to be of type
 793  *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
 794  * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
 795  * @AR5K_INT_NOCARD: signals the card has been removed
 796  * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
 797  *      bit value
 798  *
 799  * These are mapped to take advantage of some common bits
 800  * between the MACs, to be able to set intr properties
 801  * easier. Some of them are not used yet inside hw.c. Most map
 802  * to the respective hw interrupt value as they are common amogst different
 803  * MACs.
 804  */
 805 enum ath5k_int {
 806         AR5K_INT_RX     = 0x00000001, /* Not common */
 807         AR5K_INT_RXDESC = 0x00000002,
 808         AR5K_INT_RXNOFRM = 0x00000008,
 809         AR5K_INT_RXEOL  = 0x00000010,
 810         AR5K_INT_RXORN  = 0x00000020,
 811         AR5K_INT_TX     = 0x00000040, /* Not common */
 812         AR5K_INT_TXDESC = 0x00000080,
 813         AR5K_INT_TXURN  = 0x00000800,
 814         AR5K_INT_MIB    = 0x00001000,
 815         AR5K_INT_RXPHY  = 0x00004000,
 816         AR5K_INT_RXKCM  = 0x00008000,
 817         AR5K_INT_SWBA   = 0x00010000,
 818         AR5K_INT_BMISS  = 0x00040000,
 819         AR5K_INT_BNR    = 0x00100000, /* Not common */
 820         AR5K_INT_GPIO   = 0x01000000,
 821         AR5K_INT_FATAL  = 0x40000000, /* Not common */
 822         AR5K_INT_GLOBAL = 0x80000000,
 823
 824         AR5K_INT_COMMON  = AR5K_INT_RXNOFRM
 825                         | AR5K_INT_RXDESC
 826                         | AR5K_INT_RXEOL
 827                         | AR5K_INT_RXORN
 828                         | AR5K_INT_TXURN
 829                         | AR5K_INT_TXDESC
 830                         | AR5K_INT_MIB
 831                         | AR5K_INT_RXPHY
 832                         | AR5K_INT_RXKCM
 833                         | AR5K_INT_SWBA
 834                         | AR5K_INT_BMISS
 835                         | AR5K_INT_GPIO,
 836         AR5K_INT_NOCARD = 0xffffffff
 837 };
 838
 839 /*
 840  * Power management
 841  */
 842 enum ath5k_power_mode {
 843         AR5K_PM_UNDEFINED = 0,
 844         AR5K_PM_AUTO,
 845         AR5K_PM_AWAKE,
 846         AR5K_PM_FULL_SLEEP,
 847         AR5K_PM_NETWORK_SLEEP,
 848 };
 849
 850 /*
 851  * These match net80211 definitions (not used in
 852  * d80211).
 853  */
 854 #define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
 855 #define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
 856 #define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
 857 #define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
 858 #define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
 859
 860 /* GPIO-controlled software LED */
 861 #define AR5K_SOFTLED_PIN        0
 862 #define AR5K_SOFTLED_ON         0
 863 #define AR5K_SOFTLED_OFF        1
 864
 865 /*
 866  * Chipset capabilities -see ath5k_hw_get_capability-
 867  * get_capability function is not yet fully implemented
 868  * in OpenHAL so most of these don't work yet...
 869  */
 870 enum ath5k_capability_type {
 871         AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
 872         AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
 873         AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
 874         AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
 875         AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
 876         AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
 877         AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
 878         AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
 879         AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
 880         AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
 881         AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
 882         AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
 883         AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
 884         AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
 885         AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
 886         AR5K_CAP_XR                     = 16,   /* Supports XR mode */
 887         AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
 888         AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
 889         AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
 890         AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
 891 };
 892
 893 struct ath5k_capabilities {
 894         /*
 895          * Supported PHY modes
 896          * (ie. CHANNEL_A, CHANNEL_B, ...)
 897          */
 898         DECLARE_BITMAP(cap_mode, NUM_DRIVER_MODES);
 899
 900         /*
 901          * Frequency range (without regulation restrictions)
 902          */
 903         struct {
 904                 u16     range_2ghz_min;
 905                 u16     range_2ghz_max;
 906                 u16     range_5ghz_min;
 907                 u16     range_5ghz_max;
 908         } cap_range;
 909
 910         /*
 911          * Active regulation domain settings
 912          */
 913         struct {
 914                 enum ath5k_regdom reg_current;
 915                 enum ath5k_regdom reg_hw;
 916         } cap_regdomain;
 917
 918         /*
 919          * Values stored in the EEPROM (some of them...)
 920          */
 921         struct ath5k_eeprom_info        cap_eeprom;
 922
 923         /*
 924          * Queue information
 925          */
 926         struct {
 927                 u8      q_tx_num;
 928         } cap_queues;
 929 };
 930
 931
 932 /***************************************\
 933   HARDWARE ABSTRACTION LAYER STRUCTURE
 934 \***************************************/
 935
 936 /*
 937  * Misc defines
 938  */
 939
 940 #define AR5K_MAX_GPIO           10
 941 #define AR5K_MAX_RF_BANKS       8
 942
 943 struct ath5k_hw {
 944         u32                     ah_magic;
 945
 946         struct ath5k_softc      *ah_sc;
 947         void __iomem            *ah_iobase;
 948
 949         enum ath5k_int          ah_imr;
 950
 951         enum ieee80211_if_types ah_op_mode;
 952         enum ath5k_power_mode   ah_power_mode;
 953         struct ieee80211_channel ah_current_channel;
 954         bool                    ah_turbo;
 955         bool                    ah_calibration;
 956         bool                    ah_running;
 957         bool                    ah_single_chip;
 958         enum ath5k_rfgain       ah_rf_gain;
 959
 960         u32                     ah_mac_srev;
 961         u16                     ah_mac_version;
 962         u16                     ah_mac_revision;
 963         u16                     ah_phy_revision;
 964         u16                     ah_radio_5ghz_revision;
 965         u16                     ah_radio_2ghz_revision;
 966
 967         enum ath5k_version      ah_version;
 968         enum ath5k_radio        ah_radio;
 969         u32                     ah_phy;
 970
 971         bool                    ah_5ghz;
 972         bool                    ah_2ghz;
 973
 974 #define ah_regdomain            ah_capabilities.cap_regdomain.reg_current
 975 #define ah_regdomain_hw         ah_capabilities.cap_regdomain.reg_hw
 976 #define ah_modes                ah_capabilities.cap_mode
 977 #define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
 978
 979         u32                     ah_atim_window;
 980         u32                     ah_aifs;
 981         u32                     ah_cw_min;
 982         u32                     ah_cw_max;
 983         bool                    ah_software_retry;
 984         u32                     ah_limit_tx_retries;
 985
 986         u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 987         bool                    ah_ant_diversity;
 988
 989         u8                      ah_sta_id[ETH_ALEN];
 990
 991         /* Current BSSID we are trying to assoc to / creating.
 992          * This is passed by mac80211 on config_interface() and cached here for
 993          * use in resets */
 994         u8                      ah_bssid[ETH_ALEN];
 995
 996         u32                     ah_gpio[AR5K_MAX_GPIO];
 997         int                     ah_gpio_npins;
 998
 999         struct ath5k_capabilities ah_capabilities;
1000
1001         struct ath5k_txq_info   ah_txq[AR5K_NUM_TX_QUEUES];
1002         u32                     ah_txq_status;
1003         u32                     ah_txq_imr_txok;
1004         u32                     ah_txq_imr_txerr;
1005         u32                     ah_txq_imr_txurn;
1006         u32                     ah_txq_imr_txdesc;
1007         u32                     ah_txq_imr_txeol;
1008         u32                     *ah_rf_banks;
1009         size_t                  ah_rf_banks_size;
1010         struct ath5k_gain       ah_gain;
1011         u32                     ah_offset[AR5K_MAX_RF_BANKS];
1012
1013         struct {
1014                 u16             txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1015                 u16             txp_rates[AR5K_MAX_RATES];
1016                 s16             txp_min;
1017                 s16             txp_max;
1018                 bool            txp_tpc;
1019                 s16             txp_ofdm;
1020         } ah_txpower;
1021
1022         struct {
1023                 bool            r_enabled;
1024                 int             r_last_alert;
1025                 struct ieee80211_channel r_last_channel;
1026         } ah_radar;
1027
1028         /* noise floor from last periodic calibration */
1029         s32                     ah_noise_floor;
1030
1031         /*
1032          * Function pointers
1033          */
1034         int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1035                 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1036                 unsigned int, unsigned int, unsigned int, unsigned int,
1037                 unsigned int, unsigned int, unsigned int);
1038         bool (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1039                 unsigned int, unsigned int, unsigned int, unsigned int,
1040                 unsigned int, unsigned int);
1041         int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *);
1042         int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *);
1043 };
1044
1045 /*
1046  * Prototypes
1047  */
1048
1049 /* General Functions */
1050 extern int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, bool is_set);
1051 /* Attach/Detach Functions */
1052 extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
1053 extern const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah, unsigned int mode);
1054 extern void ath5k_hw_detach(struct ath5k_hw *ah);
1055 /* Reset Functions */
1056 extern int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, struct ieee80211_channel *channel, bool change_channel);
1057 /* Power management functions */
1058 extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
1059 /* DMA Related Functions */
1060 extern void ath5k_hw_start_rx(struct ath5k_hw *ah);
1061 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1062 extern u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah);
1063 extern void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr);
1064 extern int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue);
1065 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1066 extern u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue);
1067 extern int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr);
1068 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1069 /* Interrupt handling */
1070 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1071 extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1072 extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1073 /* EEPROM access functions */
1074 extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
1075 /* Protocol Control Unit Functions */
1076 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1077 /* BSSID Functions */
1078 extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1079 extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1080 extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1081 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1082 /* Receive start/stop functions */
1083 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1084 extern void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah);
1085 /* RX Filter functions */
1086 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1087 extern int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index);
1088 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1089 extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1090 extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1091 /* Beacon related functions */
1092 extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1093 extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1094 extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1095 extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1096 #if 0
1097 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1098 extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1099 extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1100 #endif
1101 extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ath5k_mib_stats *statistics);
1102 /* ACK bit rate */
1103 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1104 /* ACK/CTS Timeouts */
1105 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1106 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1107 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1108 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1109 /* Key table (WEP) functions */
1110 extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1111 extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1112 extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1113 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1114 /* Queue Control Unit, DFS Control Unit Functions */
1115 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info);
1116 extern int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue, const struct ath5k_txq_info *queue_info);
1117 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
1118 extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1119 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1120 extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1121 extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1122 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
1123 /* Hardware Descriptor Functions */
1124 extern int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, u32 size, unsigned int flags);
1125 /* GPIO Functions */
1126 extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1127 extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1128 extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1129 extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1130 extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1131 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1132 /* Regulatory Domain/Channels Setup */
1133 extern u16 ath5k_get_regdomain(struct ath5k_hw *ah);
1134 /* Misc functions */
1135 extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1136
1137
1138 /* Initial register settings functions */
1139 extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1140 /* Initialize RF */
1141 extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1142 extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1143 extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1144 extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
1145
1146
1147 /* PHY/RF channel functions */
1148 extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1149 extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1150 /* PHY calibration */
1151 extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1152 extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1153 /* Misc PHY functions */
1154 extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1155 extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1156 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1157 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1158 /* TX power setup */
1159 extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1160 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1161
1162
1163 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1164 {
1165         return ioread32(ah->ah_iobase + reg);
1166 }
1167
1168 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1169 {
1170         iowrite32(val, ah->ah_iobase + reg);
1171 }
1172
1173 #endif