?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / net / wireless / ath5k / initvals.c
blob2c22f1d4ee64026fbf0b1f075a7bbe31ef358284
1 /*
2 * Initial register settings functions
3 *
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 #include "ath5k.h"
23 #include "base.h"
24 #include "reg.h"
25
26 /*
27 * MAC/PHY REGISTERS
28 */
29
30
31 /*
32 * Mode-independent initial register writes
33 */
34
35 struct ath5k_ini {
36 u16 ini_register;
37 u32 ini_value;
38
39 enum {
40 AR5K_INI_WRITE = 0, /* Default */
41 AR5K_INI_READ = 1, /* Cleared on read */
42 } ini_mode;
43 };
44
45 /*
46 * Mode specific initial register values
47 */
48
49 struct ath5k_ini_mode {
50 u16 mode_register;
51 u32 mode_value[5];
52 };
53
54 /* Initial register settings for AR5210 */
55 static const struct ath5k_ini ar5210_ini[] = {
56 /* PCU and MAC registers */
57 { AR5K_NOQCU_TXDP0, 0 },
58 { AR5K_NOQCU_TXDP1, 0 },
59 { AR5K_RXDP, 0 },
60 { AR5K_CR, 0 },
61 { AR5K_ISR, 0, AR5K_INI_READ },
62 { AR5K_IMR, 0 },
63 { AR5K_IER, AR5K_IER_DISABLE },
64 { AR5K_BSR, 0, AR5K_INI_READ },
65 { AR5K_TXCFG, AR5K_DMASIZE_128B },
66 { AR5K_RXCFG, AR5K_DMASIZE_128B },
67 { AR5K_CFG, AR5K_INIT_CFG },
68 { AR5K_TOPS, AR5K_INIT_TOPS },
69 { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM },
70 { AR5K_RPGTO, AR5K_INIT_RPGTO },
71 { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM },
72 { AR5K_SFR, 0 },
73 { AR5K_MIBC, 0 },
74 { AR5K_MISC, 0 },
75 { AR5K_RX_FILTER_5210, 0 },
76 { AR5K_MCAST_FILTER0_5210, 0 },
77 { AR5K_MCAST_FILTER1_5210, 0 },
78 { AR5K_TX_MASK0, 0 },
79 { AR5K_TX_MASK1, 0 },
80 { AR5K_CLR_TMASK, 0 },
81 { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES },
82 { AR5K_DIAG_SW_5210, 0 },
83 { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES },
84 { AR5K_TSF_L32_5210, 0 },
85 { AR5K_TIMER0_5210, 0 },
86 { AR5K_TIMER1_5210, 0xffffffff },
87 { AR5K_TIMER2_5210, 0xffffffff },
88 { AR5K_TIMER3_5210, 1 },
89 { AR5K_CFP_DUR_5210, 0 },
90 { AR5K_CFP_PERIOD_5210, 0 },
91 /* PHY registers */
92 { AR5K_PHY(0), 0x00000047 },
93 { AR5K_PHY_AGC, 0x00000000 },
94 { AR5K_PHY(3), 0x09848ea6 },
95 { AR5K_PHY(4), 0x3d32e000 },
96 { AR5K_PHY(5), 0x0000076b },
97 { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE },
98 { AR5K_PHY(8), 0x02020200 },
99 { AR5K_PHY(9), 0x00000e0e },
100 { AR5K_PHY(10), 0x0a020201 },
101 { AR5K_PHY(11), 0x00036ffc },
102 { AR5K_PHY(12), 0x00000000 },
103 { AR5K_PHY(13), 0x00000e0e },
104 { AR5K_PHY(14), 0x00000007 },
105 { AR5K_PHY(15), 0x00020100 },
106 { AR5K_PHY(16), 0x89630000 },
107 { AR5K_PHY(17), 0x1372169c },
108 { AR5K_PHY(18), 0x0018b633 },
109 { AR5K_PHY(19), 0x1284613c },
110 { AR5K_PHY(20), 0x0de8b8e0 },
111 { AR5K_PHY(21), 0x00074859 },
112 { AR5K_PHY(22), 0x7e80beba },
113 { AR5K_PHY(23), 0x313a665e },
114 { AR5K_PHY_AGCCTL, 0x00001d08 },
115 { AR5K_PHY(25), 0x0001ce00 },
116 { AR5K_PHY(26), 0x409a4190 },
117 { AR5K_PHY(28), 0x0000000f },
118 { AR5K_PHY(29), 0x00000080 },
119 { AR5K_PHY(30), 0x00000004 },
120 { AR5K_PHY(31), 0x00000018 }, /* 0x987c */
121 { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */
122 { AR5K_PHY(65), 0x00000000 },
123 { AR5K_PHY(66), 0x00000000 },
124 { AR5K_PHY(67), 0x00800000 },
125 { AR5K_PHY(68), 0x00000003 },
126 /* BB gain table (64bytes) */
127 { AR5K_BB_GAIN(0), 0x00000000 },
128 { AR5K_BB_GAIN(1), 0x00000020 },
129 { AR5K_BB_GAIN(2), 0x00000010 },
130 { AR5K_BB_GAIN(3), 0x00000030 },
131 { AR5K_BB_GAIN(4), 0x00000008 },
132 { AR5K_BB_GAIN(5), 0x00000028 },
133 { AR5K_BB_GAIN(6), 0x00000028 },
134 { AR5K_BB_GAIN(7), 0x00000004 },
135 { AR5K_BB_GAIN(8), 0x00000024 },
136 { AR5K_BB_GAIN(9), 0x00000014 },
137 { AR5K_BB_GAIN(10), 0x00000034 },
138 { AR5K_BB_GAIN(11), 0x0000000c },
139 { AR5K_BB_GAIN(12), 0x0000002c },
140 { AR5K_BB_GAIN(13), 0x00000002 },
141 { AR5K_BB_GAIN(14), 0x00000022 },
142 { AR5K_BB_GAIN(15), 0x00000012 },
143 { AR5K_BB_GAIN(16), 0x00000032 },
144 { AR5K_BB_GAIN(17), 0x0000000a },
145 { AR5K_BB_GAIN(18), 0x0000002a },
146 { AR5K_BB_GAIN(19), 0x00000001 },
147 { AR5K_BB_GAIN(20), 0x00000021 },
148 { AR5K_BB_GAIN(21), 0x00000011 },
149 { AR5K_BB_GAIN(22), 0x00000031 },
150 { AR5K_BB_GAIN(23), 0x00000009 },
151 { AR5K_BB_GAIN(24), 0x00000029 },
152 { AR5K_BB_GAIN(25), 0x00000005 },
153 { AR5K_BB_GAIN(26), 0x00000025 },
154 { AR5K_BB_GAIN(27), 0x00000015 },
155 { AR5K_BB_GAIN(28), 0x00000035 },
156 { AR5K_BB_GAIN(29), 0x0000000d },
157 { AR5K_BB_GAIN(30), 0x0000002d },
158 { AR5K_BB_GAIN(31), 0x00000003 },
159 { AR5K_BB_GAIN(32), 0x00000023 },
160 { AR5K_BB_GAIN(33), 0x00000013 },
161 { AR5K_BB_GAIN(34), 0x00000033 },
162 { AR5K_BB_GAIN(35), 0x0000000b },
163 { AR5K_BB_GAIN(36), 0x0000002b },
164 { AR5K_BB_GAIN(37), 0x00000007 },
165 { AR5K_BB_GAIN(38), 0x00000027 },
166 { AR5K_BB_GAIN(39), 0x00000017 },
167 { AR5K_BB_GAIN(40), 0x00000037 },
168 { AR5K_BB_GAIN(41), 0x0000000f },
169 { AR5K_BB_GAIN(42), 0x0000002f },
170 { AR5K_BB_GAIN(43), 0x0000002f },
171 { AR5K_BB_GAIN(44), 0x0000002f },
172 { AR5K_BB_GAIN(45), 0x0000002f },
173 { AR5K_BB_GAIN(46), 0x0000002f },
174 { AR5K_BB_GAIN(47), 0x0000002f },
175 { AR5K_BB_GAIN(48), 0x0000002f },
176 { AR5K_BB_GAIN(49), 0x0000002f },
177 { AR5K_BB_GAIN(50), 0x0000002f },
178 { AR5K_BB_GAIN(51), 0x0000002f },
179 { AR5K_BB_GAIN(52), 0x0000002f },
180 { AR5K_BB_GAIN(53), 0x0000002f },
181 { AR5K_BB_GAIN(54), 0x0000002f },
182 { AR5K_BB_GAIN(55), 0x0000002f },
183 { AR5K_BB_GAIN(56), 0x0000002f },
184 { AR5K_BB_GAIN(57), 0x0000002f },
185 { AR5K_BB_GAIN(58), 0x0000002f },
186 { AR5K_BB_GAIN(59), 0x0000002f },
187 { AR5K_BB_GAIN(60), 0x0000002f },
188 { AR5K_BB_GAIN(61), 0x0000002f },
189 { AR5K_BB_GAIN(62), 0x0000002f },
190 { AR5K_BB_GAIN(63), 0x0000002f },
191 /* 5110 RF gain table (64btes) */
192 { AR5K_RF_GAIN(0), 0x0000001d },
193 { AR5K_RF_GAIN(1), 0x0000005d },
194 { AR5K_RF_GAIN(2), 0x0000009d },
195 { AR5K_RF_GAIN(3), 0x000000dd },
196 { AR5K_RF_GAIN(4), 0x0000011d },
197 { AR5K_RF_GAIN(5), 0x00000021 },
198 { AR5K_RF_GAIN(6), 0x00000061 },
199 { AR5K_RF_GAIN(7), 0x000000a1 },
200 { AR5K_RF_GAIN(8), 0x000000e1 },
201 { AR5K_RF_GAIN(9), 0x00000031 },
202 { AR5K_RF_GAIN(10), 0x00000071 },
203 { AR5K_RF_GAIN(11), 0x000000b1 },
204 { AR5K_RF_GAIN(12), 0x0000001c },
205 { AR5K_RF_GAIN(13), 0x0000005c },
206 { AR5K_RF_GAIN(14), 0x00000029 },
207 { AR5K_RF_GAIN(15), 0x00000069 },
208 { AR5K_RF_GAIN(16), 0x000000a9 },
209 { AR5K_RF_GAIN(17), 0x00000020 },
210 { AR5K_RF_GAIN(18), 0x00000019 },
211 { AR5K_RF_GAIN(19), 0x00000059 },
212 { AR5K_RF_GAIN(20), 0x00000099 },
213 { AR5K_RF_GAIN(21), 0x00000030 },
214 { AR5K_RF_GAIN(22), 0x00000005 },
215 { AR5K_RF_GAIN(23), 0x00000025 },
216 { AR5K_RF_GAIN(24), 0x00000065 },
217 { AR5K_RF_GAIN(25), 0x000000a5 },
218 { AR5K_RF_GAIN(26), 0x00000028 },
219 { AR5K_RF_GAIN(27), 0x00000068 },
220 { AR5K_RF_GAIN(28), 0x0000001f },
221 { AR5K_RF_GAIN(29), 0x0000001e },
222 { AR5K_RF_GAIN(30), 0x00000018 },
223 { AR5K_RF_GAIN(31), 0x00000058 },
224 { AR5K_RF_GAIN(32), 0x00000098 },
225 { AR5K_RF_GAIN(33), 0x00000003 },
226 { AR5K_RF_GAIN(34), 0x00000004 },
227 { AR5K_RF_GAIN(35), 0x00000044 },
228 { AR5K_RF_GAIN(36), 0x00000084 },
229 { AR5K_RF_GAIN(37), 0x00000013 },
230 { AR5K_RF_GAIN(38), 0x00000012 },
231 { AR5K_RF_GAIN(39), 0x00000052 },
232 { AR5K_RF_GAIN(40), 0x00000092 },
233 { AR5K_RF_GAIN(41), 0x000000d2 },
234 { AR5K_RF_GAIN(42), 0x0000002b },
235 { AR5K_RF_GAIN(43), 0x0000002a },
236 { AR5K_RF_GAIN(44), 0x0000006a },
237 { AR5K_RF_GAIN(45), 0x000000aa },
238 { AR5K_RF_GAIN(46), 0x0000001b },
239 { AR5K_RF_GAIN(47), 0x0000001a },
240 { AR5K_RF_GAIN(48), 0x0000005a },
241 { AR5K_RF_GAIN(49), 0x0000009a },
242 { AR5K_RF_GAIN(50), 0x000000da },
243 { AR5K_RF_GAIN(51), 0x00000006 },
244 { AR5K_RF_GAIN(52), 0x00000006 },
245 { AR5K_RF_GAIN(53), 0x00000006 },
246 { AR5K_RF_GAIN(54), 0x00000006 },
247 { AR5K_RF_GAIN(55), 0x00000006 },
248 { AR5K_RF_GAIN(56), 0x00000006 },
249 { AR5K_RF_GAIN(57), 0x00000006 },
250 { AR5K_RF_GAIN(58), 0x00000006 },
251 { AR5K_RF_GAIN(59), 0x00000006 },
252 { AR5K_RF_GAIN(60), 0x00000006 },
253 { AR5K_RF_GAIN(61), 0x00000006 },
254 { AR5K_RF_GAIN(62), 0x00000006 },
255 { AR5K_RF_GAIN(63), 0x00000006 },
256 /* PHY activation */
257 { AR5K_PHY(53), 0x00000020 },
258 { AR5K_PHY(51), 0x00000004 },
259 { AR5K_PHY(50), 0x00060106 },
260 { AR5K_PHY(39), 0x0000006d },
261 { AR5K_PHY(48), 0x00000000 },
262 { AR5K_PHY(52), 0x00000014 },
263 { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE },
264 };
265
266 /* Initial register settings for AR5211 */
267 static const struct ath5k_ini ar5211_ini[] = {
268 { AR5K_RXDP, 0x00000000 },
269 { AR5K_RTSD0, 0x84849c9c },
270 { AR5K_RTSD1, 0x7c7c7c7c },
271 { AR5K_RXCFG, 0x00000005 },
272 { AR5K_MIBC, 0x00000000 },
273 { AR5K_TOPS, 0x00000008 },
274 { AR5K_RXNOFRM, 0x00000008 },
275 { AR5K_TXNOFRM, 0x00000010 },
276 { AR5K_RPGTO, 0x00000000 },
277 { AR5K_RFCNT, 0x0000001f },
278 { AR5K_QUEUE_TXDP(0), 0x00000000 },
279 { AR5K_QUEUE_TXDP(1), 0x00000000 },
280 { AR5K_QUEUE_TXDP(2), 0x00000000 },
281 { AR5K_QUEUE_TXDP(3), 0x00000000 },
282 { AR5K_QUEUE_TXDP(4), 0x00000000 },
283 { AR5K_QUEUE_TXDP(5), 0x00000000 },
284 { AR5K_QUEUE_TXDP(6), 0x00000000 },
285 { AR5K_QUEUE_TXDP(7), 0x00000000 },
286 { AR5K_QUEUE_TXDP(8), 0x00000000 },
287 { AR5K_QUEUE_TXDP(9), 0x00000000 },
288 { AR5K_DCU_FP, 0x00000000 },
289 { AR5K_STA_ID1, 0x00000000 },
290 { AR5K_BSS_ID0, 0x00000000 },
291 { AR5K_BSS_ID1, 0x00000000 },
292 { AR5K_RSSI_THR, 0x00000000 },
293 { AR5K_CFP_PERIOD_5211, 0x00000000 },
294 { AR5K_TIMER0_5211, 0x00000030 },
295 { AR5K_TIMER1_5211, 0x0007ffff },
296 { AR5K_TIMER2_5211, 0x01ffffff },
297 { AR5K_TIMER3_5211, 0x00000031 },
298 { AR5K_CFP_DUR_5211, 0x00000000 },
299 { AR5K_RX_FILTER_5211, 0x00000000 },
300 { AR5K_MCAST_FILTER0_5211, 0x00000000 },
301 { AR5K_MCAST_FILTER1_5211, 0x00000002 },
302 { AR5K_DIAG_SW_5211, 0x00000000 },
303 { AR5K_ADDAC_TEST, 0x00000000 },
304 { AR5K_DEFAULT_ANTENNA, 0x00000000 },
305 /* PHY registers */
306 { AR5K_PHY_AGC, 0x00000000 },
307 { AR5K_PHY(3), 0x2d849093 },
308 { AR5K_PHY(4), 0x7d32e000 },
309 { AR5K_PHY(5), 0x00000f6b },
310 { AR5K_PHY_ACT, 0x00000000 },
311 { AR5K_PHY(11), 0x00026ffe },
312 { AR5K_PHY(12), 0x00000000 },
313 { AR5K_PHY(15), 0x00020100 },
314 { AR5K_PHY(16), 0x206a017a },
315 { AR5K_PHY(19), 0x1284613c },
316 { AR5K_PHY(21), 0x00000859 },
317 { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */
318 { AR5K_PHY(27), 0x050cb081 },
319 { AR5K_PHY(28), 0x0000000f },
320 { AR5K_PHY(29), 0x00000080 },
321 { AR5K_PHY(30), 0x0000000c },
322 { AR5K_PHY(64), 0x00000000 },
323 { AR5K_PHY(65), 0x00000000 },
324 { AR5K_PHY(66), 0x00000000 },
325 { AR5K_PHY(67), 0x00800000 },
326 { AR5K_PHY(68), 0x00000001 },
327 { AR5K_PHY(71), 0x0000092a },
328 { AR5K_PHY_IQ, 0x00000000 },
329 { AR5K_PHY(73), 0x00058a05 },
330 { AR5K_PHY(74), 0x00000001 },
331 { AR5K_PHY(75), 0x00000000 },
332 { AR5K_PHY_PAPD_PROBE, 0x00000000 },
333 { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */
334 { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */
335 { AR5K_PHY(79), 0x0000003f }, /* 0x993c */
336 { AR5K_PHY(80), 0x00000004 },
337 { AR5K_PHY(82), 0x00000000 },
338 { AR5K_PHY(83), 0x00000000 },
339 { AR5K_PHY(84), 0x00000000 },
340 { AR5K_PHY_RADAR, 0x5d50f14c },
341 { AR5K_PHY(86), 0x00000018 },
342 { AR5K_PHY(87), 0x004b6a8e },
343 /* Initial Power table (32bytes)
344 * common on all cards/modes.
345 * Note: Table is rewritten during
346 * txpower setup later using calibration
347 * data etc. so next write is non-common
348 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff },
349 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff },
350 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff },
351 { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff },
352 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff },
353 { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff },
354 { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff },
355 { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff },
356 { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff },
357 { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff },
358 { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff },
359 { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff },
360 { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff },
361 { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff },
362 { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff },
363 { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff },
364 { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff },
365 { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff },
366 { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff },
367 { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff },
368 { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff },
369 { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff },
370 { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff },
371 { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff },
372 { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff },
373 { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff },
374 { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff },
375 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff },
376 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff },
377 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff },
378 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff },*/
379 { AR5K_PHY_CCKTXCTL, 0x00000000 },
380 { AR5K_PHY(642), 0x503e4646 },
381 { AR5K_PHY_GAIN_2GHZ, 0x6480416c },
382 { AR5K_PHY(644), 0x0199a003 },
383 { AR5K_PHY(645), 0x044cd610 },
384 { AR5K_PHY(646), 0x13800040 },
385 { AR5K_PHY(647), 0x1be00060 },
386 { AR5K_PHY(648), 0x0c53800a },
387 { AR5K_PHY(649), 0x0014df3b },
388 { AR5K_PHY(650), 0x000001b5 },
389 { AR5K_PHY(651), 0x00000020 },
390 };
391
392 /* Initial mode-specific settings for AR5211
393 * XXX: how about g / gTurbo ? RF5111 supports it, how about AR5211 ?
394 * Maybe 5211 supports OFDM-only g but we need to test it !
395 */
396 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
397 { AR5K_TXCFG,
398 /* a aTurbo b */
399 { 0x00000015, 0x00000015, 0x0000001d } },
400 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
401 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
402 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
403 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
404 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
405 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
406 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
407 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
408 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
409 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
410 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
411 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
412 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
413 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
414 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
415 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
416 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
417 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
418 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
419 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f } },
420 { AR5K_DCU_GBL_IFS_SLOT,
421 { 0x00000168, 0x000001e0, 0x000001b8 } },
422 { AR5K_DCU_GBL_IFS_SIFS,
423 { 0x00000230, 0x000001e0, 0x000000b0 } },
424 { AR5K_DCU_GBL_IFS_EIFS,
425 { 0x00000d98, 0x00001180, 0x00001f48 } },
426 { AR5K_DCU_GBL_IFS_MISC,
427 { 0x0000a0e0, 0x00014068, 0x00005880 } },
428 { AR5K_TIME_OUT,
429 { 0x04000400, 0x08000800, 0x20003000 } },
430 { AR5K_USEC_5211,
431 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95 } },
432 { AR5K_PHY_TURBO,
433 { 0x00000000, 0x00000003, 0x00000000 } },
434 { AR5K_PHY(8),
435 { 0x02020200, 0x02020200, 0x02010200 } },
436 { AR5K_PHY(9),
437 { 0x00000e0e, 0x00000e0e, 0x00000707 } },
438 { AR5K_PHY(10),
439 { 0x0a020001, 0x0a020001, 0x05010000 } },
440 { AR5K_PHY(13),
441 { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
442 { AR5K_PHY(14),
443 { 0x00000007, 0x00000007, 0x0000000b } },
444 { AR5K_PHY(17),
445 { 0x1372169c, 0x137216a5, 0x137216a8 } },
446 { AR5K_PHY(18),
447 { 0x0018ba67, 0x0018ba67, 0x0018ba69 } },
448 { AR5K_PHY(20),
449 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
450 { AR5K_PHY_SIG,
451 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e } },
452 { AR5K_PHY_AGCCOARSE,
453 { 0x31375d5e, 0x31375d5e, 0x313a5d5e } },
454 { AR5K_PHY_AGCCTL,
455 { 0x0000bd10, 0x0000bd10, 0x0000bd38 } },
456 { AR5K_PHY_NF,
457 { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
458 { AR5K_PHY_RX_DELAY,
459 { 0x00002710, 0x00002710, 0x0000157c } },
460 { AR5K_PHY(70),
461 { 0x00000190, 0x00000190, 0x00000084 } },
462 { AR5K_PHY_FRAME_CTL_5211,
463 { 0x6fe01020, 0x6fe01020, 0x6fe00920 } },
464 { AR5K_PHY_PCDAC_TXPOWER_BASE_5211,
465 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff } },
466 { AR5K_RF_BUFFER_CONTROL_4,
467 { 0x00000010, 0x00000014, 0x00000010 } },
468 };
469
470 /* Initial register settings for AR5212 */
471 static const struct ath5k_ini ar5212_ini[] = {
472 { AR5K_RXDP, 0x00000000 },
473 { AR5K_RXCFG, 0x00000005 },
474 { AR5K_MIBC, 0x00000000 },
475 { AR5K_TOPS, 0x00000008 },
476 { AR5K_RXNOFRM, 0x00000008 },
477 { AR5K_TXNOFRM, 0x00000010 },
478 { AR5K_RPGTO, 0x00000000 },
479 { AR5K_RFCNT, 0x0000001f },
480 { AR5K_QUEUE_TXDP(0), 0x00000000 },
481 { AR5K_QUEUE_TXDP(1), 0x00000000 },
482 { AR5K_QUEUE_TXDP(2), 0x00000000 },
483 { AR5K_QUEUE_TXDP(3), 0x00000000 },
484 { AR5K_QUEUE_TXDP(4), 0x00000000 },
485 { AR5K_QUEUE_TXDP(5), 0x00000000 },
486 { AR5K_QUEUE_TXDP(6), 0x00000000 },
487 { AR5K_QUEUE_TXDP(7), 0x00000000 },
488 { AR5K_QUEUE_TXDP(8), 0x00000000 },
489 { AR5K_QUEUE_TXDP(9), 0x00000000 },
490 { AR5K_DCU_FP, 0x00000000 },
491 { AR5K_DCU_TXP, 0x00000000 },
492 { AR5K_DCU_TX_FILTER, 0x00000000 },
493 /* Unknown table */
494 { 0x1078, 0x00000000 },
495 { 0x10b8, 0x00000000 },
496 { 0x10f8, 0x00000000 },
497 { 0x1138, 0x00000000 },
498 { 0x1178, 0x00000000 },
499 { 0x11b8, 0x00000000 },
500 { 0x11f8, 0x00000000 },
501 { 0x1238, 0x00000000 },
502 { 0x1278, 0x00000000 },
503 { 0x12b8, 0x00000000 },
504 { 0x12f8, 0x00000000 },
505 { 0x1338, 0x00000000 },
506 { 0x1378, 0x00000000 },
507 { 0x13b8, 0x00000000 },
508 { 0x13f8, 0x00000000 },
509 { 0x1438, 0x00000000 },
510 { 0x1478, 0x00000000 },
511 { 0x14b8, 0x00000000 },
512 { 0x14f8, 0x00000000 },
513 { 0x1538, 0x00000000 },
514 { 0x1578, 0x00000000 },
515 { 0x15b8, 0x00000000 },
516 { 0x15f8, 0x00000000 },
517 { 0x1638, 0x00000000 },
518 { 0x1678, 0x00000000 },
519 { 0x16b8, 0x00000000 },
520 { 0x16f8, 0x00000000 },
521 { 0x1738, 0x00000000 },
522 { 0x1778, 0x00000000 },
523 { 0x17b8, 0x00000000 },
524 { 0x17f8, 0x00000000 },
525 { 0x103c, 0x00000000 },
526 { 0x107c, 0x00000000 },
527 { 0x10bc, 0x00000000 },
528 { 0x10fc, 0x00000000 },
529 { 0x113c, 0x00000000 },
530 { 0x117c, 0x00000000 },
531 { 0x11bc, 0x00000000 },
532 { 0x11fc, 0x00000000 },
533 { 0x123c, 0x00000000 },
534 { 0x127c, 0x00000000 },
535 { 0x12bc, 0x00000000 },
536 { 0x12fc, 0x00000000 },
537 { 0x133c, 0x00000000 },
538 { 0x137c, 0x00000000 },
539 { 0x13bc, 0x00000000 },
540 { 0x13fc, 0x00000000 },
541 { 0x143c, 0x00000000 },
542 { 0x147c, 0x00000000 },
543 { AR5K_DCU_TX_FILTER_CLR, 0x00000000 },
544 { AR5K_DCU_TX_FILTER_SET, 0x00000000 },
545 { AR5K_STA_ID1, 0x00000000 },
546 { AR5K_BSS_ID0, 0x00000000 },
547 { AR5K_BSS_ID1, 0x00000000 },
548 /*{ AR5K_RSSI_THR, 0x00000000 },*/ /* Found on SuperAG cards */
549 { AR5K_BEACON_5211, 0x00000000 }, /* Found on SuperAG cards */
550 { AR5K_CFP_PERIOD_5211, 0x00000000 }, /* Found on SuperAG cards */
551 { AR5K_TIMER0_5211, 0x00000030 }, /* Found on SuperAG cards */
552 { AR5K_TIMER1_5211, 0x0007ffff }, /* Found on SuperAG cards */
553 { AR5K_TIMER2_5211, 0x01ffffff }, /* Found on SuperAG cards */
554 { AR5K_TIMER3_5211, 0x00000031 }, /* Found on SuperAG cards */
555 { AR5K_CFP_DUR_5211, 0x00000000 }, /* Found on SuperAG cards */
556 { AR5K_RX_FILTER_5211, 0x00000000 },
557 { AR5K_DIAG_SW_5211, 0x00000000 },
558 { AR5K_ADDAC_TEST, 0x00000000 },
559 { AR5K_DEFAULT_ANTENNA, 0x00000000 },
560 { 0x8080, 0x00000000 },
561 /*{ 0x805c, 0xffffc7ff },*/ /* Old value */
562 { 0x805c, 0x000fc78f },
563 { AR5K_NAV_5211, 0x00000000 }, /* Not found on recent */
564 { AR5K_RTS_OK_5211, 0x00000000 }, /* dumps but it makes */
565 { AR5K_RTS_FAIL_5211, 0x00000000 }, /* sense to reset counters */
566 { AR5K_ACK_FAIL_5211, 0x00000000 }, /* since pcu registers */
567 { AR5K_FCS_FAIL_5211, 0x00000000 }, /* are skiped during chan*/
568 { AR5K_BEACON_CNT_5211, 0x00000000 }, /* change */
569 { AR5K_XRMODE, 0x2a82301a },
570 { AR5K_XRDELAY, 0x05dc01e0 },
571 { AR5K_XRTIMEOUT, 0x1f402710 },
572 { AR5K_XRCHIRP, 0x01f40000 },
573 { AR5K_XRSTOMP, 0x00001e1c },
574 { AR5K_SLEEP0, 0x0002aaaa }, /* Found on SuperAG cards */
575 { AR5K_SLEEP1, 0x02005555 }, /* Found on SuperAG cards */
576 { AR5K_SLEEP2, 0x00000000 }, /* Found on SuperAG cards */
577 { AR5K_BSS_IDM0, 0xffffffff },
578 { AR5K_BSS_IDM1, 0x0000ffff },
579 { AR5K_TXPC, 0x00000000 },
580 { AR5K_PROFCNT_TX, 0x00000000 },
581 { AR5K_PROFCNT_RX, 0x00000000 },
582 { AR5K_PROFCNT_RXCLR, 0x00000000 },
583 { AR5K_PROFCNT_CYCLE, 0x00000000 },
584 { 0x80fc, 0x00000088 },
585 { AR5K_RATE_DUR(0), 0x00000000 },
586 { AR5K_RATE_DUR(1), 0x0000008c },
587 { AR5K_RATE_DUR(2), 0x000000e4 },
588 { AR5K_RATE_DUR(3), 0x000002d5 },
589 { AR5K_RATE_DUR(4), 0x00000000 },
590 { AR5K_RATE_DUR(5), 0x00000000 },
591 { AR5K_RATE_DUR(6), 0x000000a0 },
592 { AR5K_RATE_DUR(7), 0x000001c9 },
593 { AR5K_RATE_DUR(8), 0x0000002c },
594 { AR5K_RATE_DUR(9), 0x0000002c },
595 { AR5K_RATE_DUR(10), 0x00000030 },
596 { AR5K_RATE_DUR(11), 0x0000003c },
597 { AR5K_RATE_DUR(12), 0x0000002c },
598 { AR5K_RATE_DUR(13), 0x0000002c },
599 { AR5K_RATE_DUR(14), 0x00000030 },
600 { AR5K_RATE_DUR(15), 0x0000003c },
601 { AR5K_RATE_DUR(16), 0x00000000 },
602 { AR5K_RATE_DUR(17), 0x00000000 },
603 { AR5K_RATE_DUR(18), 0x00000000 },
604 { AR5K_RATE_DUR(19), 0x00000000 },
605 { AR5K_RATE_DUR(20), 0x00000000 },
606 { AR5K_RATE_DUR(21), 0x00000000 },
607 { AR5K_RATE_DUR(22), 0x00000000 },
608 { AR5K_RATE_DUR(23), 0x00000000 },
609 { AR5K_RATE_DUR(24), 0x000000d5 },
610 { AR5K_RATE_DUR(25), 0x000000df },
611 { AR5K_RATE_DUR(26), 0x00000102 },
612 { AR5K_RATE_DUR(27), 0x0000013a },
613 { AR5K_RATE_DUR(28), 0x00000075 },
614 { AR5K_RATE_DUR(29), 0x0000007f },
615 { AR5K_RATE_DUR(30), 0x000000a2 },
616 { AR5K_RATE_DUR(31), 0x00000000 },
617 { 0x8100, 0x00010002},
618 { AR5K_TSF_PARM, 0x00000001 },
619 { 0x8108, 0x000000c0 },
620 { AR5K_PHY_ERR_FIL, 0x00000000 },
621 { 0x8110, 0x00000168 },
622 { 0x8114, 0x00000000 },
623 /* Some kind of table
624 * also notice ...03<-02<-01<-00) */
625 { 0x87c0, 0x03020100 },
626 { 0x87c4, 0x07060504 },
627 { 0x87c8, 0x0b0a0908 },
628 { 0x87cc, 0x0f0e0d0c },
629 { 0x87d0, 0x13121110 },
630 { 0x87d4, 0x17161514 },
631 { 0x87d8, 0x1b1a1918 },
632 { 0x87dc, 0x1f1e1d1c },
633 /* loop ? */
634 { 0x87e0, 0x03020100 },
635 { 0x87e4, 0x07060504 },
636 { 0x87e8, 0x0b0a0908 },
637 { 0x87ec, 0x0f0e0d0c },
638 { 0x87f0, 0x13121110 },
639 { 0x87f4, 0x17161514 },
640 { 0x87f8, 0x1b1a1918 },
641 { 0x87fc, 0x1f1e1d1c },
642 /* PHY registers */
643 /*{ AR5K_PHY_AGC, 0x00000000 },*/
644 { AR5K_PHY(3), 0xad848e19 },
645 { AR5K_PHY(4), 0x7d28e000 },
646 { AR5K_PHY_TIMING_3, 0x9c0a9f6b },
647 { AR5K_PHY_ACT, 0x00000000 },
648 /*{ AR5K_PHY(11), 0x00022ffe },*/
649 /*{ AR5K_PHY(15), 0x00020100 },*/
650 { AR5K_PHY(16), 0x206a017a },
651 /*{ AR5K_PHY(19), 0x1284613c },*/
652 { AR5K_PHY(21), 0x00000859 },
653 { AR5K_PHY(64), 0x00000000 },
654 { AR5K_PHY(65), 0x00000000 },
655 { AR5K_PHY(66), 0x00000000 },
656 { AR5K_PHY(67), 0x00800000 },
657 { AR5K_PHY(68), 0x00000001 },
658 /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */
659 { AR5K_PHY(71), 0x00000c80 },
660 { AR5K_PHY_IQ, 0x05100000 },
661 { AR5K_PHY(74), 0x00000001 },
662 { AR5K_PHY(75), 0x00000004 },
663 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 },
664 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d },
665 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },
666 /*{ AR5K_PHY(80), 0x00000004 },*/
667 { AR5K_PHY(82), 0x9280b212 },
668 { AR5K_PHY_RADAR, 0x5d50e188 },
669 /*{ AR5K_PHY(86), 0x000000ff },*/
670 { AR5K_PHY(87), 0x004b6a8e },
671 { AR5K_PHY(90), 0x000003ce },
672 { AR5K_PHY(92), 0x192fb515 },
673 /*{ AR5K_PHY(93), 0x00000000 },*/
674 { AR5K_PHY(94), 0x00000001 },
675 { AR5K_PHY(95), 0x00000000 },
676 /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */
677 /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */
678 { AR5K_PHY(644), 0x00806333 },
679 { AR5K_PHY(645), 0x00106c10 },
680 { AR5K_PHY(646), 0x009c4060 },
681 /*{ AR5K_PHY(647), 0x1483800a },*/ /* Old value */
682 { AR5K_PHY(647), 0x1483800a },
683 { AR5K_PHY(648), 0x01831061 },
684 { AR5K_PHY(649), 0x00000400 },
685 /*{ AR5K_PHY(650), 0x000001b5 },*/
686 { AR5K_PHY(651), 0x00000000 },
687 { AR5K_PHY_TXPOWER_RATE3, 0x20202020 },
688 { AR5K_PHY_TXPOWER_RATE2, 0x20202020 },
689 /*{ AR5K_PHY(655), 0x13c889af },*/
690 { AR5K_PHY(656), 0x38490a20 },
691 { AR5K_PHY(657), 0x00007bb6 },
692 { AR5K_PHY(658), 0x0fff3ffc },
693 /*{ AR5K_PHY_CCKTXCTL, 0x00000000 },*/
694 };
695
696 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
697 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
698 { AR5K_PHY(640),
699 /* a/XR aTurbo b g (DYN) gTurbo */
700 { 0x00000008, 0x00000008, 0x0000000b, 0x0000000e, 0x0000000e } },
701 { AR5K_PHY(0),
702 { 0x00000007, 0x00000007, 0x00000007, 0x00000007, 0x00000007 } },
703 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
704 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
705 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
706 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
707 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
708 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
709 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
710 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
711 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
712 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
713 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
714 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
715 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
716 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
717 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
718 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
719 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
720 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
721 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
722 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
723 { AR5K_DCU_GBL_IFS_SIFS,
724 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
725 { AR5K_DCU_GBL_IFS_SLOT,
726 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
727 { AR5K_DCU_GBL_IFS_EIFS,
728 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
729 { AR5K_DCU_GBL_IFS_MISC,
730 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
731 { AR5K_TIME_OUT,
732 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
733 { AR5K_PHY_TURBO,
734 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
735 { AR5K_PHY(8),
736 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
737 { AR5K_PHY(9),
738 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
739 { AR5K_PHY(17),
740 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
741 { AR5K_PHY_AGCCTL,
742 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d18 } },
743 { AR5K_PHY_NF,
744 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
745 { AR5K_PHY(26),
746 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
747 { AR5K_PHY(70),
748 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
749 { AR5K_PHY(73),
750 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
751 { 0xa230,
752 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
753 };
754
755 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
756 /* New dump pending */
757 static const struct ath5k_ini_mode ar5212_rf5111_ini_mode_end[] = {
758 { AR5K_PHY(640), /* This one differs from ar5212_ini_mode_start ! */
759 /* a/XR aTurbo b g (DYN) gTurbo */
760 { 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000006 } },
761 { AR5K_TXCFG,
762 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
763 { AR5K_USEC_5211,
764 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
765 { AR5K_PHY(10),
766 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
767 { AR5K_PHY(13),
768 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
769 { AR5K_PHY(14),
770 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
771 { AR5K_PHY(18),
772 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
773 { AR5K_PHY(20),
774 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
775 { AR5K_PHY_SIG,
776 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
777 { AR5K_PHY_AGCCOARSE,
778 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
779 { AR5K_PHY(27),
780 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
781 { AR5K_PHY_RX_DELAY,
782 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
783 { AR5K_PHY_FRAME_CTL_5211,
784 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
785 { AR5K_PHY_GAIN_2GHZ,
786 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
787 { 0xa21c,
788 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
789 { AR5K_DCU_FP,
790 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
791 { AR5K_PHY_AGC,
792 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
793 { AR5K_PHY(11),
794 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } },
795 { AR5K_PHY(15),
796 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } },
797 { AR5K_PHY(19),
798 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } },
799 { AR5K_PHY_PAPD_PROBE,
800 { 0x00004883, 0x00004883, 0x00004883, 0x00004883, 0x00004883 } },
801 { AR5K_PHY(80),
802 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } },
803 { AR5K_PHY(86),
804 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
805 { AR5K_PHY(93),
806 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
807 { AR5K_PHY_SPENDING,
808 { 0x00000018, 0x00000018, 0x00000018, 0x00000018, 0x00000018 } },
809 { AR5K_PHY_CCKTXCTL,
810 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
811 { AR5K_PHY(642),
812 { 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
813 { 0xa23c,
814 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
815 };
816
817 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
818 /* XXX: No dumps for turbog yet, but i found settings from old values so it should be ok */
819 static const struct ath5k_ini_mode ar5212_rf5112_ini_mode_end[] = {
820 { AR5K_TXCFG,
821 /* a/XR aTurbo b g (DYN) gTurbo */
822 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
823 { AR5K_USEC_5211,
824 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
825 { AR5K_PHY(10),
826 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
827 { AR5K_PHY(13),
828 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
829 { AR5K_PHY(14),
830 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
831 { AR5K_PHY(18),
832 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
833 { AR5K_PHY(20),
834 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
835 { AR5K_PHY_SIG,
836 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7ee80d2e } },
837 { AR5K_PHY_AGCCOARSE,
838 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
839 { AR5K_PHY(27),
840 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
841 { AR5K_PHY_RX_DELAY,
842 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
843 { AR5K_PHY_FRAME_CTL_5211,
844 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
845 { AR5K_PHY_CCKTXCTL,
846 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
847 { AR5K_PHY(642),
848 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
849 { AR5K_PHY_GAIN_2GHZ,
850 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
851 { 0xa21c,
852 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
853 { AR5K_DCU_FP,
854 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
855 { AR5K_PHY_AGC,
856 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
857 { AR5K_PHY(11),
858 { 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe, 0x00022ffe } },
859 { AR5K_PHY(15),
860 { 0x00020100, 0x00020100, 0x00020100, 0x00020100, 0x00020100 } },
861 { AR5K_PHY(19),
862 { 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c, 0x1284613c } },
863 { AR5K_PHY_PAPD_PROBE,
864 { 0x00004882, 0x00004882, 0x00004882, 0x00004882, 0x00004882 } },
865 { AR5K_PHY(80),
866 { 0x00000004, 0x00000004, 0x00000004, 0x00000004, 0x00000004 } },
867 { AR5K_PHY(86),
868 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
869 { AR5K_PHY(93),
870 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
871 { 0xa228,
872 { 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5, 0x000001b5 } },
873 { 0xa23c,
874 { 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af } },
875 };
876
877 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
878 /* XXX: No dumps for turbog yet, so turbog is the same with g here with some
879 * minor tweaking based on dumps from other chips */
880 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
881 { AR5K_TXCFG,
882 /* a/XR aTurbo b g gTurbo */
883 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
884 { AR5K_USEC_5211,
885 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
886 { AR5K_PHY(10),
887 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
888 { AR5K_PHY(13),
889 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
890 { AR5K_PHY(14),
891 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
892 { AR5K_PHY(18),
893 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
894 { AR5K_PHY(20),
895 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
896 { AR5K_PHY_SIG,
897 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
898 { AR5K_PHY_AGCCOARSE,
899 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
900 { AR5K_PHY(27),
901 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
902 { AR5K_PHY_RX_DELAY,
903 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
904 { AR5K_PHY_FRAME_CTL_5211,
905 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
906 { AR5K_PHY_CCKTXCTL,
907 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
908 { AR5K_PHY(642),
909 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
910 { AR5K_PHY_GAIN_2GHZ,
911 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
912 { 0xa21c,
913 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
914 { 0xa300,
915 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
916 { 0xa304,
917 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
918 { 0xa308,
919 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
920 { 0xa30c,
921 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
922 { 0xa310,
923 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
924 { 0xa314,
925 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
926 { 0xa318,
927 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
928 { 0xa31c,
929 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
930 { 0xa320,
931 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
932 { 0xa324,
933 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
934 { 0xa328,
935 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
936 { 0xa32c,
937 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
938 { 0xa330,
939 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
940 { 0xa334,
941 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
942 { AR5K_DCU_FP,
943 { 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0, 0x000003e0 } },
944 { 0x4068,
945 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
946 { 0x8060,
947 { 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f, 0x0000000f } },
948 { 0x809c,
949 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
950 { 0x80a0,
951 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
952 { 0x8118,
953 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
954 { 0x811c,
955 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
956 { 0x8120,
957 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
958 { 0x8124,
959 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
960 { 0x8128,
961 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
962 { 0x812c,
963 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
964 { 0x8130,
965 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
966 { 0x8134,
967 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
968 { 0x8138,
969 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
970 { 0x813c,
971 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
972 { 0x8140,
973 { 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9, 0x800003f9 } },
974 { 0x8144,
975 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
976 { AR5K_PHY_AGC,
977 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
978 { AR5K_PHY(11),
979 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
980 { AR5K_PHY(15),
981 { 0x00200400, 0x00200400, 0x00200400, 0x00200400, 0x00200400 } },
982 { AR5K_PHY(19),
983 { 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c } },
984 { AR5K_PHY_SCR,
985 { 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f, 0x0000001f } },
986 { AR5K_PHY_SLMT,
987 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
988 { AR5K_PHY_SCAL,
989 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
990 { AR5K_PHY(86),
991 { 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff } },
992 { AR5K_PHY(96),
993 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
994 { AR5K_PHY(97),
995 { 0x02800000, 0x02800000, 0x02800000, 0x02800000, 0x02800000 } },
996 { AR5K_PHY(104),
997 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
998 { AR5K_PHY(120),
999 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1000 { AR5K_PHY(121),
1001 { 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa, 0xaaaaaaaa } },
1002 { AR5K_PHY(122),
1003 { 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478, 0x3c466478 } },
1004 { AR5K_PHY(123),
1005 { 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa } },
1006 { AR5K_PHY_SCLOCK,
1007 { 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c } },
1008 { AR5K_PHY_SDELAY,
1009 { 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff, 0x000000ff } },
1010 { AR5K_PHY_SPENDING,
1011 { 0x00000014, 0x00000014, 0x00000014, 0x00000014, 0x00000014 } },
1012 { 0xa228,
1013 { 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5 } },
1014 { 0xa23c,
1015 { 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af, 0x93c889af } },
1016 { 0xa24c,
1017 { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
1018 { 0xa250,
1019 { 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000 } },
1020 { 0xa254,
1021 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1022 { 0xa258,
1023 { 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380 } },
1024 { 0xa25c,
1025 { 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01 } },
1026 { 0xa260,
1027 { 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01, 0x5f690f01 } },
1028 { 0xa264,
1029 { 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11 } },
1030 { 0xa268,
1031 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1032 { 0xa26c,
1033 { 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a, 0x0c30c16a } },
1034 { 0xa270,
1035 { 0x00820820, 0x00820820, 0x00820820, 0x00820820, 0x00820820 } },
1036 { 0xa274,
1037 { 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa, 0x081b7caa } },
1038 { 0xa278,
1039 { 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce } },
1040 { 0xa27c,
1041 { 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce } },
1042 { 0xa338,
1043 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1044 { 0xa33c,
1045 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1046 { 0xa340,
1047 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1048 { 0xa344,
1049 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
1050 { 0xa348,
1051 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1052 { 0xa34c,
1053 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1054 { 0xa350,
1055 { 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff } },
1056 { 0xa354,
1057 { 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff } },
1058 { 0xa358,
1059 { 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f } },
1060 { 0xa35c,
1061 { 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f } },
1062 { 0xa360,
1063 { 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207 } },
1064 { 0xa364,
1065 { 0x17601685, 0x17601685, 0x17601685, 0x17601685, 0x17601685 } },
1066 { 0xa368,
1067 { 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104 } },
1068 { 0xa36c,
1069 { 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03 } },
1070 { 0xa370,
1071 { 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883 } },
1072 { 0xa374,
1073 { 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803 } },
1074 { 0xa378,
1075 { 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682 } },
1076 { 0xa37c,
1077 { 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482 } },
1078 { 0xa380,
1079 { 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba } },
1080 { 0xa384,
1081 { 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0 } },
1082 };
1083
1084 /*
1085 * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with
1086 * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI)
1087 */
1088
1089 /* RF5111 Initial BaseBand Gain settings */
1090 static const struct ath5k_ini rf5111_ini_bbgain[] = {
1091 { AR5K_BB_GAIN(0), 0x00000000 },
1092 { AR5K_BB_GAIN(1), 0x00000020 },
1093 { AR5K_BB_GAIN(2), 0x00000010 },
1094 { AR5K_BB_GAIN(3), 0x00000030 },
1095 { AR5K_BB_GAIN(4), 0x00000008 },
1096 { AR5K_BB_GAIN(5), 0x00000028 },
1097 { AR5K_BB_GAIN(6), 0x00000004 },
1098 { AR5K_BB_GAIN(7), 0x00000024 },
1099 { AR5K_BB_GAIN(8), 0x00000014 },
1100 { AR5K_BB_GAIN(9), 0x00000034 },
1101 { AR5K_BB_GAIN(10), 0x0000000c },
1102 { AR5K_BB_GAIN(11), 0x0000002c },
1103 { AR5K_BB_GAIN(12), 0x00000002 },
1104 { AR5K_BB_GAIN(13), 0x00000022 },
1105 { AR5K_BB_GAIN(14), 0x00000012 },
1106 { AR5K_BB_GAIN(15), 0x00000032 },
1107 { AR5K_BB_GAIN(16), 0x0000000a },
1108 { AR5K_BB_GAIN(17), 0x0000002a },
1109 { AR5K_BB_GAIN(18), 0x00000006 },
1110 { AR5K_BB_GAIN(19), 0x00000026 },
1111 { AR5K_BB_GAIN(20), 0x00000016 },
1112 { AR5K_BB_GAIN(21), 0x00000036 },
1113 { AR5K_BB_GAIN(22), 0x0000000e },
1114 { AR5K_BB_GAIN(23), 0x0000002e },
1115 { AR5K_BB_GAIN(24), 0x00000001 },
1116 { AR5K_BB_GAIN(25), 0x00000021 },
1117 { AR5K_BB_GAIN(26), 0x00000011 },
1118 { AR5K_BB_GAIN(27), 0x00000031 },
1119 { AR5K_BB_GAIN(28), 0x00000009 },
1120 { AR5K_BB_GAIN(29), 0x00000029 },
1121 { AR5K_BB_GAIN(30), 0x00000005 },
1122 { AR5K_BB_GAIN(31), 0x00000025 },
1123 { AR5K_BB_GAIN(32), 0x00000015 },
1124 { AR5K_BB_GAIN(33), 0x00000035 },
1125 { AR5K_BB_GAIN(34), 0x0000000d },
1126 { AR5K_BB_GAIN(35), 0x0000002d },
1127 { AR5K_BB_GAIN(36), 0x00000003 },
1128 { AR5K_BB_GAIN(37), 0x00000023 },
1129 { AR5K_BB_GAIN(38), 0x00000013 },
1130 { AR5K_BB_GAIN(39), 0x00000033 },
1131 { AR5K_BB_GAIN(40), 0x0000000b },
1132 { AR5K_BB_GAIN(41), 0x0000002b },
1133 { AR5K_BB_GAIN(42), 0x0000002b },
1134 { AR5K_BB_GAIN(43), 0x0000002b },
1135 { AR5K_BB_GAIN(44), 0x0000002b },
1136 { AR5K_BB_GAIN(45), 0x0000002b },
1137 { AR5K_BB_GAIN(46), 0x0000002b },
1138 { AR5K_BB_GAIN(47), 0x0000002b },
1139 { AR5K_BB_GAIN(48), 0x0000002b },
1140 { AR5K_BB_GAIN(49), 0x0000002b },
1141 { AR5K_BB_GAIN(50), 0x0000002b },
1142 { AR5K_BB_GAIN(51), 0x0000002b },
1143 { AR5K_BB_GAIN(52), 0x0000002b },
1144 { AR5K_BB_GAIN(53), 0x0000002b },
1145 { AR5K_BB_GAIN(54), 0x0000002b },
1146 { AR5K_BB_GAIN(55), 0x0000002b },
1147 { AR5K_BB_GAIN(56), 0x0000002b },
1148 { AR5K_BB_GAIN(57), 0x0000002b },
1149 { AR5K_BB_GAIN(58), 0x0000002b },
1150 { AR5K_BB_GAIN(59), 0x0000002b },
1151 { AR5K_BB_GAIN(60), 0x0000002b },
1152 { AR5K_BB_GAIN(61), 0x0000002b },
1153 { AR5K_BB_GAIN(62), 0x00000002 },
1154 { AR5K_BB_GAIN(63), 0x00000016 },
1155 };
1156
1157 /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414) */
1158 static const struct ath5k_ini rf5112_ini_bbgain[] = {
1159 { AR5K_BB_GAIN(0), 0x00000000 },
1160 { AR5K_BB_GAIN(1), 0x00000001 },
1161 { AR5K_BB_GAIN(2), 0x00000002 },
1162 { AR5K_BB_GAIN(3), 0x00000003 },
1163 { AR5K_BB_GAIN(4), 0x00000004 },
1164 { AR5K_BB_GAIN(5), 0x00000005 },
1165 { AR5K_BB_GAIN(6), 0x00000008 },
1166 { AR5K_BB_GAIN(7), 0x00000009 },
1167 { AR5K_BB_GAIN(8), 0x0000000a },
1168 { AR5K_BB_GAIN(9), 0x0000000b },
1169 { AR5K_BB_GAIN(10), 0x0000000c },
1170 { AR5K_BB_GAIN(11), 0x0000000d },
1171 { AR5K_BB_GAIN(12), 0x00000010 },
1172 { AR5K_BB_GAIN(13), 0x00000011 },
1173 { AR5K_BB_GAIN(14), 0x00000012 },
1174 { AR5K_BB_GAIN(15), 0x00000013 },
1175 { AR5K_BB_GAIN(16), 0x00000014 },
1176 { AR5K_BB_GAIN(17), 0x00000015 },
1177 { AR5K_BB_GAIN(18), 0x00000018 },
1178 { AR5K_BB_GAIN(19), 0x00000019 },
1179 { AR5K_BB_GAIN(20), 0x0000001a },
1180 { AR5K_BB_GAIN(21), 0x0000001b },
1181 { AR5K_BB_GAIN(22), 0x0000001c },
1182 { AR5K_BB_GAIN(23), 0x0000001d },
1183 { AR5K_BB_GAIN(24), 0x00000020 },
1184 { AR5K_BB_GAIN(25), 0x00000021 },
1185 { AR5K_BB_GAIN(26), 0x00000022 },
1186 { AR5K_BB_GAIN(27), 0x00000023 },
1187 { AR5K_BB_GAIN(28), 0x00000024 },
1188 { AR5K_BB_GAIN(29), 0x00000025 },
1189 { AR5K_BB_GAIN(30), 0x00000028 },
1190 { AR5K_BB_GAIN(31), 0x00000029 },
1191 { AR5K_BB_GAIN(32), 0x0000002a },
1192 { AR5K_BB_GAIN(33), 0x0000002b },
1193 { AR5K_BB_GAIN(34), 0x0000002c },
1194 { AR5K_BB_GAIN(35), 0x0000002d },
1195 { AR5K_BB_GAIN(36), 0x00000030 },
1196 { AR5K_BB_GAIN(37), 0x00000031 },
1197 { AR5K_BB_GAIN(38), 0x00000032 },
1198 { AR5K_BB_GAIN(39), 0x00000033 },
1199 { AR5K_BB_GAIN(40), 0x00000034 },
1200 { AR5K_BB_GAIN(41), 0x00000035 },
1201 { AR5K_BB_GAIN(42), 0x00000035 },
1202 { AR5K_BB_GAIN(43), 0x00000035 },
1203 { AR5K_BB_GAIN(44), 0x00000035 },
1204 { AR5K_BB_GAIN(45), 0x00000035 },
1205 { AR5K_BB_GAIN(46), 0x00000035 },
1206 { AR5K_BB_GAIN(47), 0x00000035 },
1207 { AR5K_BB_GAIN(48), 0x00000035 },
1208 { AR5K_BB_GAIN(49), 0x00000035 },
1209 { AR5K_BB_GAIN(50), 0x00000035 },
1210 { AR5K_BB_GAIN(51), 0x00000035 },
1211 { AR5K_BB_GAIN(52), 0x00000035 },
1212 { AR5K_BB_GAIN(53), 0x00000035 },
1213 { AR5K_BB_GAIN(54), 0x00000035 },
1214 { AR5K_BB_GAIN(55), 0x00000035 },
1215 { AR5K_BB_GAIN(56), 0x00000035 },
1216 { AR5K_BB_GAIN(57), 0x00000035 },
1217 { AR5K_BB_GAIN(58), 0x00000035 },
1218 { AR5K_BB_GAIN(59), 0x00000035 },
1219 { AR5K_BB_GAIN(60), 0x00000035 },
1220 { AR5K_BB_GAIN(61), 0x00000035 },
1221 { AR5K_BB_GAIN(62), 0x00000010 },
1222 { AR5K_BB_GAIN(63), 0x0000001a },
1223 };
1224
1225
1226 /*
1227 * Write initial register dump
1228 */
1229 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
1230 const struct ath5k_ini *ini_regs, bool change_channel)
1231 {
1232 unsigned int i;
1233
1234 /* Write initial registers */
1235 for (i = 0; i < size; i++) {
1236 /* On channel change there is
1237 * no need to mess with PCU */
1238 if (change_channel &&
1239 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
1240 ini_regs[i].ini_register <= AR5K_PCU_MAX)
1241 continue;
1242
1243 switch (ini_regs[i].ini_mode) {
1244 case AR5K_INI_READ:
1245 /* Cleared on read */
1246 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
1247 break;
1248 case AR5K_INI_WRITE:
1249 default:
1250 AR5K_REG_WAIT(i);
1251 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
1252 ini_regs[i].ini_register);
1253 }
1254 }
1255 }
1256
1257 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
1258 unsigned int size, const struct ath5k_ini_mode *ini_mode,
1259 u8 mode)
1260 {
1261 unsigned int i;
1262
1263 for (i = 0; i < size; i++) {
1264 AR5K_REG_WAIT(i);
1265 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
1266 (u32)ini_mode[i].mode_register);
1267 }
1268
1269 }
1270
1271 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
1272 {
1273 /*
1274 * Write initial register settings
1275 */
1276
1277 /* For AR5212 and combatible */
1278 if (ah->ah_version == AR5K_AR5212){
1279
1280 /* First set of mode-specific settings */
1281 ath5k_hw_ini_mode_registers(ah,
1282 ARRAY_SIZE(ar5212_ini_mode_start),
1283 ar5212_ini_mode_start, mode);
1284
1285 /*
1286 * Write initial settings common for all modes
1287 */
1288 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini),
1289 ar5212_ini, change_channel);
1290
1291 /* Second set of mode-specific settings */
1292 if (ah->ah_radio == AR5K_RF5111){
1293 ath5k_hw_ini_mode_registers(ah,
1294 ARRAY_SIZE(ar5212_rf5111_ini_mode_end),
1295 ar5212_rf5111_ini_mode_end, mode);
1296 /* Baseband gain table */
1297 ath5k_hw_ini_registers(ah,
1298 ARRAY_SIZE(rf5111_ini_bbgain),
1299 rf5111_ini_bbgain, change_channel);
1300 } else if (ah->ah_radio == AR5K_RF5112){
1301 ath5k_hw_ini_mode_registers(ah,
1302 ARRAY_SIZE(ar5212_rf5112_ini_mode_end),
1303 ar5212_rf5112_ini_mode_end, mode);
1304 /* Baseband gain table */
1305 ath5k_hw_ini_registers(ah,
1306 ARRAY_SIZE(rf5112_ini_bbgain),
1307 rf5112_ini_bbgain, change_channel);
1308 } else if (ah->ah_radio == AR5K_RF5413){
1309 ath5k_hw_ini_mode_registers(ah,
1310 ARRAY_SIZE(rf5413_ini_mode_end),
1311 rf5413_ini_mode_end, mode);
1312 /* Baseband gain table */
1313 ath5k_hw_ini_registers(ah,
1314 ARRAY_SIZE(rf5112_ini_bbgain),
1315 rf5112_ini_bbgain, change_channel);
1316 }
1317 /* For AR5211 */
1318 } else if (ah->ah_version == AR5K_AR5211) {
1319
1320 if(mode > 2){ /* AR5K_INI_VAL_11B */
1321 ATH5K_ERR(ah->ah_sc,"unsupported channel mode: %d\n", mode);
1322 return -EINVAL;
1323 }
1324
1325 /* Mode-specific settings */
1326 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
1327 ar5211_ini_mode, mode);
1328
1329 /*
1330 * Write initial settings common for all modes
1331 */
1332 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
1333 ar5211_ini, change_channel);
1334
1335 /* AR5211 only comes with 5111 */
1336
1337 /* Baseband gain table */
1338 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
1339 rf5111_ini_bbgain, change_channel);
1340 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
1341 } else if (ah->ah_version == AR5K_AR5210) {
1342 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
1343 ar5210_ini, change_channel);
1344 }
1345
1346 return 0;
1347 }
WRT350N Kernel Patches