include/asm-x86/pgtable-3level.h

   1 #ifndef _I386_PGTABLE_3LEVEL_H
   2 #define _I386_PGTABLE_3LEVEL_H
   3
   4 /*
   5  * Intel Physical Address Extension (PAE) Mode - three-level page
   6  * tables on PPro+ CPUs.
   7  *
   8  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
   9  */
  10
  11 #define pte_ERROR(e) \
  12         printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
  13 #define pmd_ERROR(e) \
  14         printk("%s:%d: bad pmd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pmd_val(e))
  15 #define pgd_ERROR(e) \
  16         printk("%s:%d: bad pgd %p(%016Lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
  17
  18 #define pud_none(pud)                           0
  19 #define pud_bad(pud)                            0
  20 #define pud_present(pud)                        1
  21
  22 /* Rules for using set_pte: the pte being assigned *must* be
  23  * either not present or in a state where the hardware will
  24  * not attempt to update the pte.  In places where this is
  25  * not possible, use pte_get_and_clear to obtain the old pte
  26  * value and then use set_pte to update it.  -ben
  27  */
  28 static inline void native_set_pte(pte_t *ptep, pte_t pte)
  29 {
  30         ptep->pte_high = pte.pte_high;
  31         smp_wmb();
  32         ptep->pte_low = pte.pte_low;
  33 }
  34
  35 /*
  36  * Since this is only called on user PTEs, and the page fault handler
  37  * must handle the already racy situation of simultaneous page faults,
  38  * we are justified in merely clearing the PTE present bit, followed
  39  * by a set.  The ordering here is important.
  40  */
  41 static inline void native_set_pte_present(struct mm_struct *mm, unsigned long addr,
  42                                           pte_t *ptep, pte_t pte)
  43 {
  44         ptep->pte_low = 0;
  45         smp_wmb();
  46         ptep->pte_high = pte.pte_high;
  47         smp_wmb();
  48         ptep->pte_low = pte.pte_low;
  49 }
  50
  51 static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
  52 {
  53         set_64bit((unsigned long long *)(ptep),native_pte_val(pte));
  54 }
  55 static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
  56 {
  57         set_64bit((unsigned long long *)(pmdp),native_pmd_val(pmd));
  58 }
  59 static inline void native_set_pud(pud_t *pudp, pud_t pud)
  60 {
  61         *pudp = pud;
  62 }
  63
  64 /*
  65  * For PTEs and PDEs, we must clear the P-bit first when clearing a page table
  66  * entry, so clear the bottom half first and enforce ordering with a compiler
  67  * barrier.
  68  */
  69 static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
  70 {
  71         ptep->pte_low = 0;
  72         smp_wmb();
  73         ptep->pte_high = 0;
  74 }
  75
  76 static inline void native_pmd_clear(pmd_t *pmd)
  77 {
  78         u32 *tmp = (u32 *)pmd;
  79         *tmp = 0;
  80         smp_wmb();
  81         *(tmp + 1) = 0;
  82 }
  83
  84 /*
  85  * Pentium-II erratum A13: in PAE mode we explicitly have to flush
  86  * the TLB via cr3 if the top-level pgd is changed...
  87  * We do not let the generic code free and clear pgd entries due to
  88  * this erratum.
  89  */
  90 static inline void pud_clear (pud_t * pud) { }
  91
  92 #define pud_page(pud) \
  93 ((struct page *) __va(pud_val(pud) & PAGE_MASK))
  94
  95 #define pud_page_vaddr(pud) \
  96 ((unsigned long) __va(pud_val(pud) & PAGE_MASK))
  97
  98
  99 /* Find an entry in the second-level page table.. */
 100 #define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
 101                         pmd_index(address))
 102
 103 #ifdef CONFIG_SMP
 104 static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 105 {
 106         pte_t res;
 107
 108         /* xchg acts as a barrier before the setting of the high bits */
 109         res.pte_low = xchg(&ptep->pte_low, 0);
 110         res.pte_high = ptep->pte_high;
 111         ptep->pte_high = 0;
 112
 113         return res;
 114 }
 115 #else
 116 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
 117 #endif
 118
 119 #define __HAVE_ARCH_PTE_SAME
 120 static inline int pte_same(pte_t a, pte_t b)
 121 {
 122         return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
 123 }
 124
 125 #define pte_page(x)     pfn_to_page(pte_pfn(x))
 126
 127 static inline int pte_none(pte_t pte)
 128 {
 129         return !pte.pte_low && !pte.pte_high;
 130 }
 131
 132 static inline unsigned long pte_pfn(pte_t pte)
 133 {
 134         return (pte_val(pte) & ~_PAGE_NX) >> PAGE_SHIFT;
 135 }
 136
 137 /*
 138  * Bits 0, 6 and 7 are taken in the low part of the pte,
 139  * put the 32 bits of offset into the high part.
 140  */
 141 #define pte_to_pgoff(pte) ((pte).pte_high)
 142 #define pgoff_to_pte(off) ((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
 143 #define PTE_FILE_MAX_BITS       32
 144
 145 /* Encode and de-code a swap entry */
 146 #define __swp_type(x)                   (((x).val) & 0x1f)
 147 #define __swp_offset(x)                 ((x).val >> 5)
 148 #define __swp_entry(type, offset)       ((swp_entry_t){(type) | (offset) << 5})
 149 #define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
 150 #define __swp_entry_to_pte(x)           ((pte_t){ { .pte_high = (x).val } })
 151
 152 #endif /* _I386_PGTABLE_3LEVEL_H */