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mm/slab.c: proper prototypes
[wrt350n-kernel.git] / drivers / media / dvb / frontends / cx24123.c
blob732e94aaa364779f53920780f7b04a5dc7e0e5fa
1 /*
2 Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
3
4 Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
5
6 Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/slab.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28
29 #include "dvb_frontend.h"
30 #include "cx24123.h"
31
32 #define XTAL 10111000
33
34 static int force_band;
35 static int debug;
36 #define dprintk(args...) \
37 do { \
38 if (debug) printk (KERN_DEBUG "cx24123: " args); \
39 } while (0)
40
41 struct cx24123_state
42 {
43 struct i2c_adapter* i2c;
44 const struct cx24123_config* config;
45
46 struct dvb_frontend frontend;
47
48 /* Some PLL specifics for tuning */
49 u32 VCAarg;
50 u32 VGAarg;
51 u32 bandselectarg;
52 u32 pllarg;
53 u32 FILTune;
54
55 /* The Demod/Tuner can't easily provide these, we cache them */
56 u32 currentfreq;
57 u32 currentsymbolrate;
58 };
59
60 /* Various tuner defaults need to be established for a given symbol rate Sps */
61 static struct
62 {
63 u32 symbolrate_low;
64 u32 symbolrate_high;
65 u32 VCAprogdata;
66 u32 VGAprogdata;
67 u32 FILTune;
68 } cx24123_AGC_vals[] =
69 {
70 {
71 .symbolrate_low = 1000000,
72 .symbolrate_high = 4999999,
73 /* the specs recommend other values for VGA offsets,
74 but tests show they are wrong */
75 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
76 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07,
77 .FILTune = 0x27f /* 0.41 V */
78 },
79 {
80 .symbolrate_low = 5000000,
81 .symbolrate_high = 14999999,
82 .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0,
83 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f,
84 .FILTune = 0x317 /* 0.90 V */
85 },
86 {
87 .symbolrate_low = 15000000,
88 .symbolrate_high = 45000000,
89 .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180,
90 .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f,
91 .FILTune = 0x145 /* 2.70 V */
92 },
93 };
94
95 /*
96 * Various tuner defaults need to be established for a given frequency kHz.
97 * fixme: The bounds on the bands do not match the doc in real life.
98 * fixme: Some of them have been moved, other might need adjustment.
99 */
100 static struct
101 {
102 u32 freq_low;
103 u32 freq_high;
104 u32 VCOdivider;
105 u32 progdata;
106 } cx24123_bandselect_vals[] =
107 {
108 /* band 1 */
109 {
110 .freq_low = 950000,
111 .freq_high = 1074999,
112 .VCOdivider = 4,
113 .progdata = (0 << 19) | (0 << 9) | 0x40,
114 },
115
116 /* band 2 */
117 {
118 .freq_low = 1075000,
119 .freq_high = 1177999,
120 .VCOdivider = 4,
121 .progdata = (0 << 19) | (0 << 9) | 0x80,
122 },
123
124 /* band 3 */
125 {
126 .freq_low = 1178000,
127 .freq_high = 1295999,
128 .VCOdivider = 2,
129 .progdata = (0 << 19) | (1 << 9) | 0x01,
130 },
131
132 /* band 4 */
133 {
134 .freq_low = 1296000,
135 .freq_high = 1431999,
136 .VCOdivider = 2,
137 .progdata = (0 << 19) | (1 << 9) | 0x02,
138 },
139
140 /* band 5 */
141 {
142 .freq_low = 1432000,
143 .freq_high = 1575999,
144 .VCOdivider = 2,
145 .progdata = (0 << 19) | (1 << 9) | 0x04,
146 },
147
148 /* band 6 */
149 {
150 .freq_low = 1576000,
151 .freq_high = 1717999,
152 .VCOdivider = 2,
153 .progdata = (0 << 19) | (1 << 9) | 0x08,
154 },
155
156 /* band 7 */
157 {
158 .freq_low = 1718000,
159 .freq_high = 1855999,
160 .VCOdivider = 2,
161 .progdata = (0 << 19) | (1 << 9) | 0x10,
162 },
163
164 /* band 8 */
165 {
166 .freq_low = 1856000,
167 .freq_high = 2035999,
168 .VCOdivider = 2,
169 .progdata = (0 << 19) | (1 << 9) | 0x20,
170 },
171
172 /* band 9 */
173 {
174 .freq_low = 2036000,
175 .freq_high = 2150000,
176 .VCOdivider = 2,
177 .progdata = (0 << 19) | (1 << 9) | 0x40,
178 },
179 };
180
181 static struct {
182 u8 reg;
183 u8 data;
184 } cx24123_regdata[] =
185 {
186 {0x00, 0x03}, /* Reset system */
187 {0x00, 0x00}, /* Clear reset */
188 {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */
189 {0x04, 0x10}, /* MPEG */
190 {0x05, 0x04}, /* MPEG */
191 {0x06, 0x31}, /* MPEG (default) */
192 {0x0b, 0x00}, /* Freq search start point (default) */
193 {0x0c, 0x00}, /* Demodulator sample gain (default) */
194 {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */
195 {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */
196 {0x0f, 0xfe}, /* FEC search mask (all supported codes) */
197 {0x10, 0x01}, /* Default search inversion, no repeat (default) */
198 {0x16, 0x00}, /* Enable reading of frequency */
199 {0x17, 0x01}, /* Enable EsNO Ready Counter */
200 {0x1c, 0x80}, /* Enable error counter */
201 {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */
202 {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */
203 {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */
204 {0x29, 0x00}, /* DiSEqC LNB_DC off */
205 {0x2a, 0xb0}, /* DiSEqC Parameters (default) */
206 {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */
207 {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */
208 {0x2d, 0x00},
209 {0x2e, 0x00},
210 {0x2f, 0x00},
211 {0x30, 0x00},
212 {0x31, 0x00},
213 {0x32, 0x8c}, /* DiSEqC Parameters (default) */
214 {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */
215 {0x34, 0x00},
216 {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */
217 {0x36, 0x02}, /* DiSEqC Parameters (default) */
218 {0x37, 0x3a}, /* DiSEqC Parameters (default) */
219 {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */
220 {0x44, 0x00}, /* Constellation (default) */
221 {0x45, 0x00}, /* Symbol count (default) */
222 {0x46, 0x0d}, /* Symbol rate estimator on (default) */
223 {0x56, 0xc1}, /* Error Counter = Viterbi BER */
224 {0x57, 0xff}, /* Error Counter Window (default) */
225 {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */
226 {0x67, 0x83}, /* Non-DCII symbol clock */
227 };
228
229 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
230 {
231 u8 buf[] = { reg, data };
232 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
233 int err;
234
235 if (debug>1)
236 printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n",
237 __FUNCTION__,reg, data);
238
239 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
240 printk("%s: writereg error(err == %i, reg == 0x%02x,"
241 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
242 return -EREMOTEIO;
243 }
244
245 return 0;
246 }
247
248 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
249 {
250 int ret;
251 u8 b0[] = { reg };
252 u8 b1[] = { 0 };
253 struct i2c_msg msg[] = {
254 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
255 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
256 };
257
258 ret = i2c_transfer(state->i2c, msg, 2);
259
260 if (ret != 2) {
261 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
262 return ret;
263 }
264
265 if (debug>1)
266 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);
267
268 return b1[0];
269 }
270
271 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
272 {
273 u8 nom_reg = cx24123_readreg(state, 0x0e);
274 u8 auto_reg = cx24123_readreg(state, 0x10);
275
276 switch (inversion) {
277 case INVERSION_OFF:
278 dprintk("%s: inversion off\n",__FUNCTION__);
279 cx24123_writereg(state, 0x0e, nom_reg & ~0x80);
280 cx24123_writereg(state, 0x10, auto_reg | 0x80);
281 break;
282 case INVERSION_ON:
283 dprintk("%s: inversion on\n",__FUNCTION__);
284 cx24123_writereg(state, 0x0e, nom_reg | 0x80);
285 cx24123_writereg(state, 0x10, auto_reg | 0x80);
286 break;
287 case INVERSION_AUTO:
288 dprintk("%s: inversion auto\n",__FUNCTION__);
289 cx24123_writereg(state, 0x10, auto_reg & ~0x80);
290 break;
291 default:
292 return -EINVAL;
293 }
294
295 return 0;
296 }
297
298 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
299 {
300 u8 val;
301
302 val = cx24123_readreg(state, 0x1b) >> 7;
303
304 if (val == 0) {
305 dprintk("%s: read inversion off\n",__FUNCTION__);
306 *inversion = INVERSION_OFF;
307 } else {
308 dprintk("%s: read inversion on\n",__FUNCTION__);
309 *inversion = INVERSION_ON;
310 }
311
312 return 0;
313 }
314
315 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
316 {
317 u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07;
318
319 if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
320 fec = FEC_AUTO;
321
322 /* Set the soft decision threshold */
323 if(fec == FEC_1_2)
324 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) | 0x01);
325 else
326 cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) & ~0x01);
327
328 switch (fec) {
329 case FEC_1_2:
330 dprintk("%s: set FEC to 1/2\n",__FUNCTION__);
331 cx24123_writereg(state, 0x0e, nom_reg | 0x01);
332 cx24123_writereg(state, 0x0f, 0x02);
333 break;
334 case FEC_2_3:
335 dprintk("%s: set FEC to 2/3\n",__FUNCTION__);
336 cx24123_writereg(state, 0x0e, nom_reg | 0x02);
337 cx24123_writereg(state, 0x0f, 0x04);
338 break;
339 case FEC_3_4:
340 dprintk("%s: set FEC to 3/4\n",__FUNCTION__);
341 cx24123_writereg(state, 0x0e, nom_reg | 0x03);
342 cx24123_writereg(state, 0x0f, 0x08);
343 break;
344 case FEC_4_5:
345 dprintk("%s: set FEC to 4/5\n",__FUNCTION__);
346 cx24123_writereg(state, 0x0e, nom_reg | 0x04);
347 cx24123_writereg(state, 0x0f, 0x10);
348 break;
349 case FEC_5_6:
350 dprintk("%s: set FEC to 5/6\n",__FUNCTION__);
351 cx24123_writereg(state, 0x0e, nom_reg | 0x05);
352 cx24123_writereg(state, 0x0f, 0x20);
353 break;
354 case FEC_6_7:
355 dprintk("%s: set FEC to 6/7\n",__FUNCTION__);
356 cx24123_writereg(state, 0x0e, nom_reg | 0x06);
357 cx24123_writereg(state, 0x0f, 0x40);
358 break;
359 case FEC_7_8:
360 dprintk("%s: set FEC to 7/8\n",__FUNCTION__);
361 cx24123_writereg(state, 0x0e, nom_reg | 0x07);
362 cx24123_writereg(state, 0x0f, 0x80);
363 break;
364 case FEC_AUTO:
365 dprintk("%s: set FEC to auto\n",__FUNCTION__);
366 cx24123_writereg(state, 0x0f, 0xfe);
367 break;
368 default:
369 return -EOPNOTSUPP;
370 }
371
372 return 0;
373 }
374
375 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
376 {
377 int ret;
378
379 ret = cx24123_readreg (state, 0x1b);
380 if (ret < 0)
381 return ret;
382 ret = ret & 0x07;
383
384 switch (ret) {
385 case 1:
386 *fec = FEC_1_2;
387 break;
388 case 2:
389 *fec = FEC_2_3;
390 break;
391 case 3:
392 *fec = FEC_3_4;
393 break;
394 case 4:
395 *fec = FEC_4_5;
396 break;
397 case 5:
398 *fec = FEC_5_6;
399 break;
400 case 6:
401 *fec = FEC_6_7;
402 break;
403 case 7:
404 *fec = FEC_7_8;
405 break;
406 default:
407 /* this can happen when there's no lock */
408 *fec = FEC_NONE;
409 }
410
411 return 0;
412 }
413
414 /* Approximation of closest integer of log2(a/b). It actually gives the
415 lowest integer i such that 2^i >= round(a/b) */
416 static u32 cx24123_int_log2(u32 a, u32 b)
417 {
418 u32 exp, nearest = 0;
419 u32 div = a / b;
420 if(a % b >= b / 2) ++div;
421 if(div < (1 << 31))
422 {
423 for(exp = 1; div > exp; nearest++)
424 exp += exp;
425 }
426 return nearest;
427 }
428
429 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
430 {
431 u32 tmp, sample_rate, ratio, sample_gain;
432 u8 pll_mult;
433
434 /* check if symbol rate is within limits */
435 if ((srate > state->frontend.ops.info.symbol_rate_max) ||
436 (srate < state->frontend.ops.info.symbol_rate_min))
437 return -EOPNOTSUPP;;
438
439 /* choose the sampling rate high enough for the required operation,
440 while optimizing the power consumed by the demodulator */
441 if (srate < (XTAL*2)/2)
442 pll_mult = 2;
443 else if (srate < (XTAL*3)/2)
444 pll_mult = 3;
445 else if (srate < (XTAL*4)/2)
446 pll_mult = 4;
447 else if (srate < (XTAL*5)/2)
448 pll_mult = 5;
449 else if (srate < (XTAL*6)/2)
450 pll_mult = 6;
451 else if (srate < (XTAL*7)/2)
452 pll_mult = 7;
453 else if (srate < (XTAL*8)/2)
454 pll_mult = 8;
455 else
456 pll_mult = 9;
457
458
459 sample_rate = pll_mult * XTAL;
460
461 /*
462 SYSSymbolRate[21:0] = (srate << 23) / sample_rate
463
464 We have to use 32 bit unsigned arithmetic without precision loss.
465 The maximum srate is 45000000 or 0x02AEA540. This number has
466 only 6 clear bits on top, hence we can shift it left only 6 bits
467 at a time. Borrowed from cx24110.c
468 */
469
470 tmp = srate << 6;
471 ratio = tmp / sample_rate;
472
473 tmp = (tmp % sample_rate) << 6;
474 ratio = (ratio << 6) + (tmp / sample_rate);
475
476 tmp = (tmp % sample_rate) << 6;
477 ratio = (ratio << 6) + (tmp / sample_rate);
478
479 tmp = (tmp % sample_rate) << 5;
480 ratio = (ratio << 5) + (tmp / sample_rate);
481
482
483 cx24123_writereg(state, 0x01, pll_mult * 6);
484
485 cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
486 cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff );
487 cx24123_writereg(state, 0x0a, (ratio ) & 0xff );
488
489 /* also set the demodulator sample gain */
490 sample_gain = cx24123_int_log2(sample_rate, srate);
491 tmp = cx24123_readreg(state, 0x0c) & ~0xe0;
492 cx24123_writereg(state, 0x0c, tmp | sample_gain << 5);
493
494 dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain);
495
496 return 0;
497 }
498
499 /*
500 * Based on the required frequency and symbolrate, the tuner AGC has to be configured
501 * and the correct band selected. Calculate those values
502 */
503 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
504 {
505 struct cx24123_state *state = fe->demodulator_priv;
506 u32 ndiv = 0, adiv = 0, vco_div = 0;
507 int i = 0;
508 int pump = 2;
509 int band = 0;
510 int num_bands = ARRAY_SIZE(cx24123_bandselect_vals);
511
512 /* Defaults for low freq, low rate */
513 state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
514 state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
515 state->bandselectarg = cx24123_bandselect_vals[0].progdata;
516 vco_div = cx24123_bandselect_vals[0].VCOdivider;
517
518 /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
519 for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++)
520 {
521 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
522 (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
523 state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
524 state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
525 state->FILTune = cx24123_AGC_vals[i].FILTune;
526 }
527 }
528
529 /* determine the band to use */
530 if(force_band < 1 || force_band > num_bands)
531 {
532 for (i = 0; i < num_bands; i++)
533 {
534 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
535 (cx24123_bandselect_vals[i].freq_high >= p->frequency) )
536 band = i;
537 }
538 }
539 else
540 band = force_band - 1;
541
542 state->bandselectarg = cx24123_bandselect_vals[band].progdata;
543 vco_div = cx24123_bandselect_vals[band].VCOdivider;
544
545 /* determine the charge pump current */
546 if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 )
547 pump = 0x01;
548 else
549 pump = 0x02;
550
551 /* Determine the N/A dividers for the requested lband freq (in kHz). */
552 /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
553 ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
554 adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
555
556 if (adiv == 0 && ndiv > 0)
557 ndiv--;
558
559 /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
560 state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
561
562 return 0;
563 }
564
565 /*
566 * Tuner data is 21 bits long, must be left-aligned in data.
567 * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
568 */
569 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
570 {
571 struct cx24123_state *state = fe->demodulator_priv;
572 unsigned long timeout;
573
574 dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data);
575
576 /* align the 21 bytes into to bit23 boundary */
577 data = data << 3;
578
579 /* Reset the demod pll word length to 0x15 bits */
580 cx24123_writereg(state, 0x21, 0x15);
581
582 /* write the msb 8 bits, wait for the send to be completed */
583 timeout = jiffies + msecs_to_jiffies(40);
584 cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
585 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
586 if (time_after(jiffies, timeout)) {
587 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
588 return -EREMOTEIO;
589 }
590 msleep(10);
591 }
592
593 /* send another 8 bytes, wait for the send to be completed */
594 timeout = jiffies + msecs_to_jiffies(40);
595 cx24123_writereg(state, 0x22, (data>>8) & 0xff );
596 while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
597 if (time_after(jiffies, timeout)) {
598 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
599 return -EREMOTEIO;
600 }
601 msleep(10);
602 }
603
604 /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
605 timeout = jiffies + msecs_to_jiffies(40);
606 cx24123_writereg(state, 0x22, (data) & 0xff );
607 while ((cx24123_readreg(state, 0x20) & 0x80)) {
608 if (time_after(jiffies, timeout)) {
609 printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
610 return -EREMOTEIO;
611 }
612 msleep(10);
613 }
614
615 /* Trigger the demod to configure the tuner */
616 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
617 cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
618
619 return 0;
620 }
621
622 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
623 {
624 struct cx24123_state *state = fe->demodulator_priv;
625 u8 val;
626
627 dprintk("frequency=%i\n", p->frequency);
628
629 if (cx24123_pll_calculate(fe, p) != 0) {
630 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
631 return -EINVAL;
632 }
633
634 /* Write the new VCO/VGA */
635 cx24123_pll_writereg(fe, p, state->VCAarg);
636 cx24123_pll_writereg(fe, p, state->VGAarg);
637
638 /* Write the new bandselect and pll args */
639 cx24123_pll_writereg(fe, p, state->bandselectarg);
640 cx24123_pll_writereg(fe, p, state->pllarg);
641
642 /* set the FILTUNE voltage */
643 val = cx24123_readreg(state, 0x28) & ~0x3;
644 cx24123_writereg(state, 0x27, state->FILTune >> 2);
645 cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
646
647 dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
648 state->bandselectarg,state->pllarg);
649
650 return 0;
651 }
652
653 static int cx24123_initfe(struct dvb_frontend* fe)
654 {
655 struct cx24123_state *state = fe->demodulator_priv;
656 int i;
657
658 dprintk("%s: init frontend\n",__FUNCTION__);
659
660 /* Configure the demod to a good set of defaults */
661 for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++)
662 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
663
664 /* Set the LNB polarity */
665 if(state->config->lnb_polarity)
666 cx24123_writereg(state, 0x32, cx24123_readreg(state, 0x32) | 0x02);
667
668 return 0;
669 }
670
671 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
672 {
673 struct cx24123_state *state = fe->demodulator_priv;
674 u8 val;
675
676 val = cx24123_readreg(state, 0x29) & ~0x40;
677
678 switch (voltage) {
679 case SEC_VOLTAGE_13:
680 dprintk("%s: setting voltage 13V\n", __FUNCTION__);
681 return cx24123_writereg(state, 0x29, val & 0x7f);
682 case SEC_VOLTAGE_18:
683 dprintk("%s: setting voltage 18V\n", __FUNCTION__);
684 return cx24123_writereg(state, 0x29, val | 0x80);
685 case SEC_VOLTAGE_OFF:
686 /* already handled in cx88-dvb */
687 return 0;
688 default:
689 return -EINVAL;
690 };
691
692 return 0;
693 }
694
695 /* wait for diseqc queue to become ready (or timeout) */
696 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
697 {
698 unsigned long timeout = jiffies + msecs_to_jiffies(200);
699 while (!(cx24123_readreg(state, 0x29) & 0x40)) {
700 if(time_after(jiffies, timeout)) {
701 printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
702 break;
703 }
704 msleep(10);
705 }
706 }
707
708 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
709 {
710 struct cx24123_state *state = fe->demodulator_priv;
711 int i, val, tone;
712
713 dprintk("%s:\n",__FUNCTION__);
714
715 /* stop continuous tone if enabled */
716 tone = cx24123_readreg(state, 0x29);
717 if (tone & 0x10)
718 cx24123_writereg(state, 0x29, tone & ~0x50);
719
720 /* wait for diseqc queue ready */
721 cx24123_wait_for_diseqc(state);
722
723 /* select tone mode */
724 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
725
726 for (i = 0; i < cmd->msg_len; i++)
727 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
728
729 val = cx24123_readreg(state, 0x29);
730 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
731
732 /* wait for diseqc message to finish sending */
733 cx24123_wait_for_diseqc(state);
734
735 /* restart continuous tone if enabled */
736 if (tone & 0x10) {
737 cx24123_writereg(state, 0x29, tone & ~0x40);
738 }
739
740 return 0;
741 }
742
743 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
744 {
745 struct cx24123_state *state = fe->demodulator_priv;
746 int val, tone;
747
748 dprintk("%s:\n", __FUNCTION__);
749
750 /* stop continuous tone if enabled */
751 tone = cx24123_readreg(state, 0x29);
752 if (tone & 0x10)
753 cx24123_writereg(state, 0x29, tone & ~0x50);
754
755 /* wait for diseqc queue ready */
756 cx24123_wait_for_diseqc(state);
757
758 /* select tone mode */
759 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4);
760 msleep(30);
761 val = cx24123_readreg(state, 0x29);
762 if (burst == SEC_MINI_A)
763 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
764 else if (burst == SEC_MINI_B)
765 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
766 else
767 return -EINVAL;
768
769 cx24123_wait_for_diseqc(state);
770 cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb);
771
772 /* restart continuous tone if enabled */
773 if (tone & 0x10) {
774 cx24123_writereg(state, 0x29, tone & ~0x40);
775 }
776 return 0;
777 }
778
779 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
780 {
781 struct cx24123_state *state = fe->demodulator_priv;
782
783 int sync = cx24123_readreg(state, 0x14);
784 int lock = cx24123_readreg(state, 0x20);
785
786 *status = 0;
787 if (lock & 0x01)
788 *status |= FE_HAS_SIGNAL;
789 if (sync & 0x02)
790 *status |= FE_HAS_CARRIER; /* Phase locked */
791 if (sync & 0x04)
792 *status |= FE_HAS_VITERBI;
793
794 /* Reed-Solomon Status */
795 if (sync & 0x08)
796 *status |= FE_HAS_SYNC;
797 if (sync & 0x80)
798 *status |= FE_HAS_LOCK; /*Full Sync */
799
800 return 0;
801 }
802
803 /*
804 * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
805 * is available, so this value doubles up to satisfy both measurements
806 */
807 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
808 {
809 struct cx24123_state *state = fe->demodulator_priv;
810
811 /* The true bit error rate is this value divided by
812 the window size (set as 256 * 255) */
813 *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
814 (cx24123_readreg(state, 0x1d) << 8 |
815 cx24123_readreg(state, 0x1e));
816
817 dprintk("%s: BER = %d\n",__FUNCTION__,*ber);
818
819 return 0;
820 }
821
822 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
823 {
824 struct cx24123_state *state = fe->demodulator_priv;
825
826 *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
827
828 dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength);
829
830 return 0;
831 }
832
833 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
834 {
835 struct cx24123_state *state = fe->demodulator_priv;
836
837 /* Inverted raw Es/N0 count, totally bogus but better than the
838 BER threshold. */
839 *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) |
840 (u16)cx24123_readreg(state, 0x19));
841
842 dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr);
843
844 return 0;
845 }
846
847 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
848 {
849 struct cx24123_state *state = fe->demodulator_priv;
850
851 dprintk("%s: set_frontend\n",__FUNCTION__);
852
853 if (state->config->set_ts_params)
854 state->config->set_ts_params(fe, 0);
855
856 state->currentfreq=p->frequency;
857 state->currentsymbolrate = p->u.qpsk.symbol_rate;
858
859 cx24123_set_inversion(state, p->inversion);
860 cx24123_set_fec(state, p->u.qpsk.fec_inner);
861 cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
862 cx24123_pll_tune(fe, p);
863
864 /* Enable automatic aquisition and reset cycle */
865 cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
866 cx24123_writereg(state, 0x00, 0x10);
867 cx24123_writereg(state, 0x00, 0);
868
869 return 0;
870 }
871
872 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
873 {
874 struct cx24123_state *state = fe->demodulator_priv;
875
876 dprintk("%s: get_frontend\n",__FUNCTION__);
877
878 if (cx24123_get_inversion(state, &p->inversion) != 0) {
879 printk("%s: Failed to get inversion status\n",__FUNCTION__);
880 return -EREMOTEIO;
881 }
882 if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
883 printk("%s: Failed to get fec status\n",__FUNCTION__);
884 return -EREMOTEIO;
885 }
886 p->frequency = state->currentfreq;
887 p->u.qpsk.symbol_rate = state->currentsymbolrate;
888
889 return 0;
890 }
891
892 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
893 {
894 struct cx24123_state *state = fe->demodulator_priv;
895 u8 val;
896
897 /* wait for diseqc queue ready */
898 cx24123_wait_for_diseqc(state);
899
900 val = cx24123_readreg(state, 0x29) & ~0x40;
901
902 switch (tone) {
903 case SEC_TONE_ON:
904 dprintk("%s: setting tone on\n", __FUNCTION__);
905 return cx24123_writereg(state, 0x29, val | 0x10);
906 case SEC_TONE_OFF:
907 dprintk("%s: setting tone off\n",__FUNCTION__);
908 return cx24123_writereg(state, 0x29, val & 0xef);
909 default:
910 printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
911 return -EINVAL;
912 }
913
914 return 0;
915 }
916
917 static int cx24123_tune(struct dvb_frontend* fe,
918 struct dvb_frontend_parameters* params,
919 unsigned int mode_flags,
920 int *delay,
921 fe_status_t *status)
922 {
923 int retval = 0;
924
925 if (params != NULL)
926 retval = cx24123_set_frontend(fe, params);
927
928 if (!(mode_flags & FE_TUNE_MODE_ONESHOT))
929 cx24123_read_status(fe, status);
930 *delay = HZ/10;
931
932 return retval;
933 }
934
935 static int cx24123_get_algo(struct dvb_frontend *fe)
936 {
937 return 1; //FE_ALGO_HW
938 }
939
940 static void cx24123_release(struct dvb_frontend* fe)
941 {
942 struct cx24123_state* state = fe->demodulator_priv;
943 dprintk("%s\n",__FUNCTION__);
944 kfree(state);
945 }
946
947 static struct dvb_frontend_ops cx24123_ops;
948
949 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
950 struct i2c_adapter* i2c)
951 {
952 struct cx24123_state* state = NULL;
953 int ret;
954
955 dprintk("%s\n",__FUNCTION__);
956
957 /* allocate memory for the internal state */
958 state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
959 if (state == NULL) {
960 printk("Unable to kmalloc\n");
961 goto error;
962 }
963
964 /* setup the state */
965 state->config = config;
966 state->i2c = i2c;
967 state->VCAarg = 0;
968 state->VGAarg = 0;
969 state->bandselectarg = 0;
970 state->pllarg = 0;
971 state->currentfreq = 0;
972 state->currentsymbolrate = 0;
973
974 /* check if the demod is there */
975 ret = cx24123_readreg(state, 0x00);
976 if ((ret != 0xd1) && (ret != 0xe1)) {
977 printk("Version != d1 or e1\n");
978 goto error;
979 }
980
981 /* create dvb_frontend */
982 memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
983 state->frontend.demodulator_priv = state;
984 return &state->frontend;
985
986 error:
987 kfree(state);
988
989 return NULL;
990 }
991
992 static struct dvb_frontend_ops cx24123_ops = {
993
994 .info = {
995 .name = "Conexant CX24123/CX24109",
996 .type = FE_QPSK,
997 .frequency_min = 950000,
998 .frequency_max = 2150000,
999 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1000 .frequency_tolerance = 5000,
1001 .symbol_rate_min = 1000000,
1002 .symbol_rate_max = 45000000,
1003 .caps = FE_CAN_INVERSION_AUTO |
1004 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1005 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
1006 FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1007 FE_CAN_QPSK | FE_CAN_RECOVER
1008 },
1009
1010 .release = cx24123_release,
1011
1012 .init = cx24123_initfe,
1013 .set_frontend = cx24123_set_frontend,
1014 .get_frontend = cx24123_get_frontend,
1015 .read_status = cx24123_read_status,
1016 .read_ber = cx24123_read_ber,
1017 .read_signal_strength = cx24123_read_signal_strength,
1018 .read_snr = cx24123_read_snr,
1019 .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1020 .diseqc_send_burst = cx24123_diseqc_send_burst,
1021 .set_tone = cx24123_set_tone,
1022 .set_voltage = cx24123_set_voltage,
1023 .tune = cx24123_tune,
1024 .get_frontend_algo = cx24123_get_algo,
1025 };
1026
1027 module_param(debug, int, 0644);
1028 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1029
1030 module_param(force_band, int, 0644);
1031 MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off).");
1032
1033 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
1034 MODULE_AUTHOR("Steven Toth");
1035 MODULE_LICENSE("GPL");
1036
1037 EXPORT_SYMBOL(cx24123_attach);
WRT350N Kernel Patches