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mm/slab.c: proper prototypes
[wrt350n-kernel.git] / drivers / net / ns83820.c
blob6a32338623f18bdeacca68b2ffc9e771cf03bfeb
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/smp_lock.h>
108 #include <linux/workqueue.h>
109 #include <linux/init.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/timer.h>
116 #include <linux/if_vlan.h>
117 #include <linux/rtnetlink.h>
118 #include <linux/jiffies.h>
119
120 #include <asm/io.h>
121 #include <asm/uaccess.h>
122 #include <asm/system.h>
123
124 #define DRV_NAME "ns83820"
125
126 /* Global parameters. See module_param near the bottom. */
127 static int ihr = 2;
128 static int reset_phy = 0;
129 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
130
131 /* Dprintk is used for more interesting debug events */
132 #undef Dprintk
133 #define Dprintk dprintk
134
135 /* tunables */
136 #define RX_BUF_SIZE 1500 /* 8192 */
137 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
138 #define NS83820_VLAN_ACCEL_SUPPORT
139 #endif
140
141 /* Must not exceed ~65000. */
142 #define NR_RX_DESC 64
143 #define NR_TX_DESC 128
144
145 /* not tunable */
146 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
147
148 #define MIN_TX_DESC_FREE 8
149
150 /* register defines */
151 #define CFGCS 0x04
152
153 #define CR_TXE 0x00000001
154 #define CR_TXD 0x00000002
155 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
156 * The Receive engine skips one descriptor and moves
157 * onto the next one!! */
158 #define CR_RXE 0x00000004
159 #define CR_RXD 0x00000008
160 #define CR_TXR 0x00000010
161 #define CR_RXR 0x00000020
162 #define CR_SWI 0x00000080
163 #define CR_RST 0x00000100
164
165 #define PTSCR_EEBIST_FAIL 0x00000001
166 #define PTSCR_EEBIST_EN 0x00000002
167 #define PTSCR_EELOAD_EN 0x00000004
168 #define PTSCR_RBIST_FAIL 0x000001b8
169 #define PTSCR_RBIST_DONE 0x00000200
170 #define PTSCR_RBIST_EN 0x00000400
171 #define PTSCR_RBIST_RST 0x00002000
172
173 #define MEAR_EEDI 0x00000001
174 #define MEAR_EEDO 0x00000002
175 #define MEAR_EECLK 0x00000004
176 #define MEAR_EESEL 0x00000008
177 #define MEAR_MDIO 0x00000010
178 #define MEAR_MDDIR 0x00000020
179 #define MEAR_MDC 0x00000040
180
181 #define ISR_TXDESC3 0x40000000
182 #define ISR_TXDESC2 0x20000000
183 #define ISR_TXDESC1 0x10000000
184 #define ISR_TXDESC0 0x08000000
185 #define ISR_RXDESC3 0x04000000
186 #define ISR_RXDESC2 0x02000000
187 #define ISR_RXDESC1 0x01000000
188 #define ISR_RXDESC0 0x00800000
189 #define ISR_TXRCMP 0x00400000
190 #define ISR_RXRCMP 0x00200000
191 #define ISR_DPERR 0x00100000
192 #define ISR_SSERR 0x00080000
193 #define ISR_RMABT 0x00040000
194 #define ISR_RTABT 0x00020000
195 #define ISR_RXSOVR 0x00010000
196 #define ISR_HIBINT 0x00008000
197 #define ISR_PHY 0x00004000
198 #define ISR_PME 0x00002000
199 #define ISR_SWI 0x00001000
200 #define ISR_MIB 0x00000800
201 #define ISR_TXURN 0x00000400
202 #define ISR_TXIDLE 0x00000200
203 #define ISR_TXERR 0x00000100
204 #define ISR_TXDESC 0x00000080
205 #define ISR_TXOK 0x00000040
206 #define ISR_RXORN 0x00000020
207 #define ISR_RXIDLE 0x00000010
208 #define ISR_RXEARLY 0x00000008
209 #define ISR_RXERR 0x00000004
210 #define ISR_RXDESC 0x00000002
211 #define ISR_RXOK 0x00000001
212
213 #define TXCFG_CSI 0x80000000
214 #define TXCFG_HBI 0x40000000
215 #define TXCFG_MLB 0x20000000
216 #define TXCFG_ATP 0x10000000
217 #define TXCFG_ECRETRY 0x00800000
218 #define TXCFG_BRST_DIS 0x00080000
219 #define TXCFG_MXDMA1024 0x00000000
220 #define TXCFG_MXDMA512 0x00700000
221 #define TXCFG_MXDMA256 0x00600000
222 #define TXCFG_MXDMA128 0x00500000
223 #define TXCFG_MXDMA64 0x00400000
224 #define TXCFG_MXDMA32 0x00300000
225 #define TXCFG_MXDMA16 0x00200000
226 #define TXCFG_MXDMA8 0x00100000
227
228 #define CFG_LNKSTS 0x80000000
229 #define CFG_SPDSTS 0x60000000
230 #define CFG_SPDSTS1 0x40000000
231 #define CFG_SPDSTS0 0x20000000
232 #define CFG_DUPSTS 0x10000000
233 #define CFG_TBI_EN 0x01000000
234 #define CFG_MODE_1000 0x00400000
235 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
236 * Read the Phy response and then configure the MAC accordingly */
237 #define CFG_AUTO_1000 0x00200000
238 #define CFG_PINT_CTL 0x001c0000
239 #define CFG_PINT_DUPSTS 0x00100000
240 #define CFG_PINT_LNKSTS 0x00080000
241 #define CFG_PINT_SPDSTS 0x00040000
242 #define CFG_TMRTEST 0x00020000
243 #define CFG_MRM_DIS 0x00010000
244 #define CFG_MWI_DIS 0x00008000
245 #define CFG_T64ADDR 0x00004000
246 #define CFG_PCI64_DET 0x00002000
247 #define CFG_DATA64_EN 0x00001000
248 #define CFG_M64ADDR 0x00000800
249 #define CFG_PHY_RST 0x00000400
250 #define CFG_PHY_DIS 0x00000200
251 #define CFG_EXTSTS_EN 0x00000100
252 #define CFG_REQALG 0x00000080
253 #define CFG_SB 0x00000040
254 #define CFG_POW 0x00000020
255 #define CFG_EXD 0x00000010
256 #define CFG_PESEL 0x00000008
257 #define CFG_BROM_DIS 0x00000004
258 #define CFG_EXT_125 0x00000002
259 #define CFG_BEM 0x00000001
260
261 #define EXTSTS_UDPPKT 0x00200000
262 #define EXTSTS_TCPPKT 0x00080000
263 #define EXTSTS_IPPKT 0x00020000
264 #define EXTSTS_VPKT 0x00010000
265 #define EXTSTS_VTG_MASK 0x0000ffff
266
267 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
268
269 #define MIBC_MIBS 0x00000008
270 #define MIBC_ACLR 0x00000004
271 #define MIBC_FRZ 0x00000002
272 #define MIBC_WRN 0x00000001
273
274 #define PCR_PSEN (1 << 31)
275 #define PCR_PS_MCAST (1 << 30)
276 #define PCR_PS_DA (1 << 29)
277 #define PCR_STHI_8 (3 << 23)
278 #define PCR_STLO_4 (1 << 23)
279 #define PCR_FFHI_8K (3 << 21)
280 #define PCR_FFLO_4K (1 << 21)
281 #define PCR_PAUSE_CNT 0xFFFE
282
283 #define RXCFG_AEP 0x80000000
284 #define RXCFG_ARP 0x40000000
285 #define RXCFG_STRIPCRC 0x20000000
286 #define RXCFG_RX_FD 0x10000000
287 #define RXCFG_ALP 0x08000000
288 #define RXCFG_AIRL 0x04000000
289 #define RXCFG_MXDMA512 0x00700000
290 #define RXCFG_DRTH 0x0000003e
291 #define RXCFG_DRTH0 0x00000002
292
293 #define RFCR_RFEN 0x80000000
294 #define RFCR_AAB 0x40000000
295 #define RFCR_AAM 0x20000000
296 #define RFCR_AAU 0x10000000
297 #define RFCR_APM 0x08000000
298 #define RFCR_APAT 0x07800000
299 #define RFCR_APAT3 0x04000000
300 #define RFCR_APAT2 0x02000000
301 #define RFCR_APAT1 0x01000000
302 #define RFCR_APAT0 0x00800000
303 #define RFCR_AARP 0x00400000
304 #define RFCR_MHEN 0x00200000
305 #define RFCR_UHEN 0x00100000
306 #define RFCR_ULM 0x00080000
307
308 #define VRCR_RUDPE 0x00000080
309 #define VRCR_RTCPE 0x00000040
310 #define VRCR_RIPE 0x00000020
311 #define VRCR_IPEN 0x00000010
312 #define VRCR_DUTF 0x00000008
313 #define VRCR_DVTF 0x00000004
314 #define VRCR_VTREN 0x00000002
315 #define VRCR_VTDEN 0x00000001
316
317 #define VTCR_PPCHK 0x00000008
318 #define VTCR_GCHK 0x00000004
319 #define VTCR_VPPTI 0x00000002
320 #define VTCR_VGTI 0x00000001
321
322 #define CR 0x00
323 #define CFG 0x04
324 #define MEAR 0x08
325 #define PTSCR 0x0c
326 #define ISR 0x10
327 #define IMR 0x14
328 #define IER 0x18
329 #define IHR 0x1c
330 #define TXDP 0x20
331 #define TXDP_HI 0x24
332 #define TXCFG 0x28
333 #define GPIOR 0x2c
334 #define RXDP 0x30
335 #define RXDP_HI 0x34
336 #define RXCFG 0x38
337 #define PQCR 0x3c
338 #define WCSR 0x40
339 #define PCR 0x44
340 #define RFCR 0x48
341 #define RFDR 0x4c
342
343 #define SRR 0x58
344
345 #define VRCR 0xbc
346 #define VTCR 0xc0
347 #define VDR 0xc4
348 #define CCSR 0xcc
349
350 #define TBICR 0xe0
351 #define TBISR 0xe4
352 #define TANAR 0xe8
353 #define TANLPAR 0xec
354 #define TANER 0xf0
355 #define TESR 0xf4
356
357 #define TBICR_MR_AN_ENABLE 0x00001000
358 #define TBICR_MR_RESTART_AN 0x00000200
359
360 #define TBISR_MR_LINK_STATUS 0x00000020
361 #define TBISR_MR_AN_COMPLETE 0x00000004
362
363 #define TANAR_PS2 0x00000100
364 #define TANAR_PS1 0x00000080
365 #define TANAR_HALF_DUP 0x00000040
366 #define TANAR_FULL_DUP 0x00000020
367
368 #define GPIOR_GP5_OE 0x00000200
369 #define GPIOR_GP4_OE 0x00000100
370 #define GPIOR_GP3_OE 0x00000080
371 #define GPIOR_GP2_OE 0x00000040
372 #define GPIOR_GP1_OE 0x00000020
373 #define GPIOR_GP3_OUT 0x00000004
374 #define GPIOR_GP1_OUT 0x00000001
375
376 #define LINK_AUTONEGOTIATE 0x01
377 #define LINK_DOWN 0x02
378 #define LINK_UP 0x04
379
380 #define HW_ADDR_LEN sizeof(dma_addr_t)
381 #define desc_addr_set(desc, addr) \
382 do { \
383 ((desc)[0] = cpu_to_le32(addr)); \
384 if (HW_ADDR_LEN == 8) \
385 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
386 } while(0)
387 #define desc_addr_get(desc) \
388 (le32_to_cpu((desc)[0]) | \
389 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
390
391 #define DESC_LINK 0
392 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
393 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
394 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
395
396 #define CMDSTS_OWN 0x80000000
397 #define CMDSTS_MORE 0x40000000
398 #define CMDSTS_INTR 0x20000000
399 #define CMDSTS_ERR 0x10000000
400 #define CMDSTS_OK 0x08000000
401 #define CMDSTS_RUNT 0x00200000
402 #define CMDSTS_LEN_MASK 0x0000ffff
403
404 #define CMDSTS_DEST_MASK 0x01800000
405 #define CMDSTS_DEST_SELF 0x00800000
406 #define CMDSTS_DEST_MULTI 0x01000000
407
408 #define DESC_SIZE 8 /* Should be cache line sized */
409
410 struct rx_info {
411 spinlock_t lock;
412 int up;
413 long idle;
414
415 struct sk_buff *skbs[NR_RX_DESC];
416
417 __le32 *next_rx_desc;
418 u16 next_rx, next_empty;
419
420 __le32 *descs;
421 dma_addr_t phy_descs;
422 };
423
424
425 struct ns83820 {
426 struct net_device_stats stats;
427 u8 __iomem *base;
428
429 struct pci_dev *pci_dev;
430 struct net_device *ndev;
431
432 #ifdef NS83820_VLAN_ACCEL_SUPPORT
433 struct vlan_group *vlgrp;
434 #endif
435
436 struct rx_info rx_info;
437 struct tasklet_struct rx_tasklet;
438
439 unsigned ihr;
440 struct work_struct tq_refill;
441
442 /* protects everything below. irqsave when using. */
443 spinlock_t misc_lock;
444
445 u32 CFG_cache;
446
447 u32 MEAR_cache;
448 u32 IMR_cache;
449
450 unsigned linkstate;
451
452 spinlock_t tx_lock;
453
454 u16 tx_done_idx;
455 u16 tx_idx;
456 volatile u16 tx_free_idx; /* idx of free desc chain */
457 u16 tx_intr_idx;
458
459 atomic_t nr_tx_skbs;
460 struct sk_buff *tx_skbs[NR_TX_DESC];
461
462 char pad[16] __attribute__((aligned(16)));
463 __le32 *tx_descs;
464 dma_addr_t tx_phy_descs;
465
466 struct timer_list tx_watchdog;
467 };
468
469 static inline struct ns83820 *PRIV(struct net_device *dev)
470 {
471 return netdev_priv(dev);
472 }
473
474 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475
476 static inline void kick_rx(struct net_device *ndev)
477 {
478 struct ns83820 *dev = PRIV(ndev);
479 dprintk("kick_rx: maybe kicking\n");
480 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
481 dprintk("actually kicking\n");
482 writel(dev->rx_info.phy_descs +
483 (4 * DESC_SIZE * dev->rx_info.next_rx),
484 dev->base + RXDP);
485 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
486 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
487 ndev->name);
488 __kick_rx(dev);
489 }
490 }
491
492 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
493 #define start_tx_okay(dev) \
494 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495
496
497 #ifdef NS83820_VLAN_ACCEL_SUPPORT
498 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
499 {
500 struct ns83820 *dev = PRIV(ndev);
501
502 spin_lock_irq(&dev->misc_lock);
503 spin_lock(&dev->tx_lock);
504
505 dev->vlgrp = grp;
506
507 spin_unlock(&dev->tx_lock);
508 spin_unlock_irq(&dev->misc_lock);
509 }
510
511 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
512 {
513 struct ns83820 *dev = PRIV(ndev);
514
515 spin_lock_irq(&dev->misc_lock);
516 spin_lock(&dev->tx_lock);
517 vlan_group_set_device(dev->vlgrp, vid, NULL);
518 spin_unlock(&dev->tx_lock);
519 spin_unlock_irq(&dev->misc_lock);
520 }
521 #endif
522
523 /* Packet Receiver
524 *
525 * The hardware supports linked lists of receive descriptors for
526 * which ownership is transfered back and forth by means of an
527 * ownership bit. While the hardware does support the use of a
528 * ring for receive descriptors, we only make use of a chain in
529 * an attempt to reduce bus traffic under heavy load scenarios.
530 * This will also make bugs a bit more obvious. The current code
531 * only makes use of a single rx chain; I hope to implement
532 * priority based rx for version 1.0. Goal: even under overload
533 * conditions, still route realtime traffic with as low jitter as
534 * possible.
535 */
536 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
537 {
538 desc_addr_set(desc + DESC_LINK, link);
539 desc_addr_set(desc + DESC_BUFPTR, buf);
540 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
541 mb();
542 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
543 }
544
545 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
546 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
547 {
548 unsigned next_empty;
549 u32 cmdsts;
550 __le32 *sg;
551 dma_addr_t buf;
552
553 next_empty = dev->rx_info.next_empty;
554
555 /* don't overrun last rx marker */
556 if (unlikely(nr_rx_empty(dev) <= 2)) {
557 kfree_skb(skb);
558 return 1;
559 }
560
561 #if 0
562 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
563 dev->rx_info.next_empty,
564 dev->rx_info.nr_used,
565 dev->rx_info.next_rx
566 );
567 #endif
568
569 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
570 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
571 dev->rx_info.skbs[next_empty] = skb;
572
573 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
574 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
575 buf = pci_map_single(dev->pci_dev, skb->data,
576 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
577 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
578 /* update link of previous rx */
579 if (likely(next_empty != dev->rx_info.next_rx))
580 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
581
582 return 0;
583 }
584
585 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
586 {
587 struct ns83820 *dev = PRIV(ndev);
588 unsigned i;
589 unsigned long flags = 0;
590
591 if (unlikely(nr_rx_empty(dev) <= 2))
592 return 0;
593
594 dprintk("rx_refill(%p)\n", ndev);
595 if (gfp == GFP_ATOMIC)
596 spin_lock_irqsave(&dev->rx_info.lock, flags);
597 for (i=0; i<NR_RX_DESC; i++) {
598 struct sk_buff *skb;
599 long res;
600 /* extra 16 bytes for alignment */
601 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
602 if (unlikely(!skb))
603 break;
604
605 res = (long)skb->data & 0xf;
606 res = 0x10 - res;
607 res &= 0xf;
608 skb_reserve(skb, res);
609
610 if (gfp != GFP_ATOMIC)
611 spin_lock_irqsave(&dev->rx_info.lock, flags);
612 res = ns83820_add_rx_skb(dev, skb);
613 if (gfp != GFP_ATOMIC)
614 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
615 if (res) {
616 i = 1;
617 break;
618 }
619 }
620 if (gfp == GFP_ATOMIC)
621 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
622
623 return i ? 0 : -ENOMEM;
624 }
625
626 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
627 static void fastcall rx_refill_atomic(struct net_device *ndev)
628 {
629 rx_refill(ndev, GFP_ATOMIC);
630 }
631
632 /* REFILL */
633 static inline void queue_refill(struct work_struct *work)
634 {
635 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
636 struct net_device *ndev = dev->ndev;
637
638 rx_refill(ndev, GFP_KERNEL);
639 if (dev->rx_info.up)
640 kick_rx(ndev);
641 }
642
643 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
644 {
645 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
646 }
647
648 static void FASTCALL(phy_intr(struct net_device *ndev));
649 static void fastcall phy_intr(struct net_device *ndev)
650 {
651 struct ns83820 *dev = PRIV(ndev);
652 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
653 u32 cfg, new_cfg;
654 u32 tbisr, tanar, tanlpar;
655 int speed, fullduplex, newlinkstate;
656
657 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
658
659 if (dev->CFG_cache & CFG_TBI_EN) {
660 /* we have an optical transceiver */
661 tbisr = readl(dev->base + TBISR);
662 tanar = readl(dev->base + TANAR);
663 tanlpar = readl(dev->base + TANLPAR);
664 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
665 tbisr, tanar, tanlpar);
666
667 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
668 && (tanar & TANAR_FULL_DUP)) ) {
669
670 /* both of us are full duplex */
671 writel(readl(dev->base + TXCFG)
672 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
673 dev->base + TXCFG);
674 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
675 dev->base + RXCFG);
676 /* Light up full duplex LED */
677 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
678 dev->base + GPIOR);
679
680 } else if(((tanlpar & TANAR_HALF_DUP)
681 && (tanar & TANAR_HALF_DUP))
682 || ((tanlpar & TANAR_FULL_DUP)
683 && (tanar & TANAR_HALF_DUP))
684 || ((tanlpar & TANAR_HALF_DUP)
685 && (tanar & TANAR_FULL_DUP))) {
686
687 /* one or both of us are half duplex */
688 writel((readl(dev->base + TXCFG)
689 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
690 dev->base + TXCFG);
691 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
692 dev->base + RXCFG);
693 /* Turn off full duplex LED */
694 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
695 dev->base + GPIOR);
696 }
697
698 speed = 4; /* 1000F */
699
700 } else {
701 /* we have a copper transceiver */
702 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
703
704 if (cfg & CFG_SPDSTS1)
705 new_cfg |= CFG_MODE_1000;
706 else
707 new_cfg &= ~CFG_MODE_1000;
708
709 speed = ((cfg / CFG_SPDSTS0) & 3);
710 fullduplex = (cfg & CFG_DUPSTS);
711
712 if (fullduplex) {
713 new_cfg |= CFG_SB;
714 writel(readl(dev->base + TXCFG)
715 | TXCFG_CSI | TXCFG_HBI,
716 dev->base + TXCFG);
717 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
718 dev->base + RXCFG);
719 } else {
720 writel(readl(dev->base + TXCFG)
721 & ~(TXCFG_CSI | TXCFG_HBI),
722 dev->base + TXCFG);
723 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
724 dev->base + RXCFG);
725 }
726
727 if ((cfg & CFG_LNKSTS) &&
728 ((new_cfg ^ dev->CFG_cache) != 0)) {
729 writel(new_cfg, dev->base + CFG);
730 dev->CFG_cache = new_cfg;
731 }
732
733 dev->CFG_cache &= ~CFG_SPDSTS;
734 dev->CFG_cache |= cfg & CFG_SPDSTS;
735 }
736
737 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
738
739 if (newlinkstate & LINK_UP
740 && dev->linkstate != newlinkstate) {
741 netif_start_queue(ndev);
742 netif_wake_queue(ndev);
743 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
744 ndev->name,
745 speeds[speed],
746 fullduplex ? "full" : "half");
747 } else if (newlinkstate & LINK_DOWN
748 && dev->linkstate != newlinkstate) {
749 netif_stop_queue(ndev);
750 printk(KERN_INFO "%s: link now down.\n", ndev->name);
751 }
752
753 dev->linkstate = newlinkstate;
754 }
755
756 static int ns83820_setup_rx(struct net_device *ndev)
757 {
758 struct ns83820 *dev = PRIV(ndev);
759 unsigned i;
760 int ret;
761
762 dprintk("ns83820_setup_rx(%p)\n", ndev);
763
764 dev->rx_info.idle = 1;
765 dev->rx_info.next_rx = 0;
766 dev->rx_info.next_rx_desc = dev->rx_info.descs;
767 dev->rx_info.next_empty = 0;
768
769 for (i=0; i<NR_RX_DESC; i++)
770 clear_rx_desc(dev, i);
771
772 writel(0, dev->base + RXDP_HI);
773 writel(dev->rx_info.phy_descs, dev->base + RXDP);
774
775 ret = rx_refill(ndev, GFP_KERNEL);
776 if (!ret) {
777 dprintk("starting receiver\n");
778 /* prevent the interrupt handler from stomping on us */
779 spin_lock_irq(&dev->rx_info.lock);
780
781 writel(0x0001, dev->base + CCSR);
782 writel(0, dev->base + RFCR);
783 writel(0x7fc00000, dev->base + RFCR);
784 writel(0xffc00000, dev->base + RFCR);
785
786 dev->rx_info.up = 1;
787
788 phy_intr(ndev);
789
790 /* Okay, let it rip */
791 spin_lock_irq(&dev->misc_lock);
792 dev->IMR_cache |= ISR_PHY;
793 dev->IMR_cache |= ISR_RXRCMP;
794 //dev->IMR_cache |= ISR_RXERR;
795 //dev->IMR_cache |= ISR_RXOK;
796 dev->IMR_cache |= ISR_RXORN;
797 dev->IMR_cache |= ISR_RXSOVR;
798 dev->IMR_cache |= ISR_RXDESC;
799 dev->IMR_cache |= ISR_RXIDLE;
800 dev->IMR_cache |= ISR_TXDESC;
801 dev->IMR_cache |= ISR_TXIDLE;
802
803 writel(dev->IMR_cache, dev->base + IMR);
804 writel(1, dev->base + IER);
805 spin_unlock(&dev->misc_lock);
806
807 kick_rx(ndev);
808
809 spin_unlock_irq(&dev->rx_info.lock);
810 }
811 return ret;
812 }
813
814 static void ns83820_cleanup_rx(struct ns83820 *dev)
815 {
816 unsigned i;
817 unsigned long flags;
818
819 dprintk("ns83820_cleanup_rx(%p)\n", dev);
820
821 /* disable receive interrupts */
822 spin_lock_irqsave(&dev->misc_lock, flags);
823 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
824 writel(dev->IMR_cache, dev->base + IMR);
825 spin_unlock_irqrestore(&dev->misc_lock, flags);
826
827 /* synchronize with the interrupt handler and kill it */
828 dev->rx_info.up = 0;
829 synchronize_irq(dev->pci_dev->irq);
830
831 /* touch the pci bus... */
832 readl(dev->base + IMR);
833
834 /* assumes the transmitter is already disabled and reset */
835 writel(0, dev->base + RXDP_HI);
836 writel(0, dev->base + RXDP);
837
838 for (i=0; i<NR_RX_DESC; i++) {
839 struct sk_buff *skb = dev->rx_info.skbs[i];
840 dev->rx_info.skbs[i] = NULL;
841 clear_rx_desc(dev, i);
842 if (skb)
843 kfree_skb(skb);
844 }
845 }
846
847 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
848 static void fastcall ns83820_rx_kick(struct net_device *ndev)
849 {
850 struct ns83820 *dev = PRIV(ndev);
851 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
852 if (dev->rx_info.up) {
853 rx_refill_atomic(ndev);
854 kick_rx(ndev);
855 }
856 }
857
858 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
859 schedule_work(&dev->tq_refill);
860 else
861 kick_rx(ndev);
862 if (dev->rx_info.idle)
863 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
864 }
865
866 /* rx_irq
867 *
868 */
869 static void FASTCALL(rx_irq(struct net_device *ndev));
870 static void fastcall rx_irq(struct net_device *ndev)
871 {
872 struct ns83820 *dev = PRIV(ndev);
873 struct rx_info *info = &dev->rx_info;
874 unsigned next_rx;
875 int rx_rc, len;
876 u32 cmdsts;
877 __le32 *desc;
878 unsigned long flags;
879 int nr = 0;
880
881 dprintk("rx_irq(%p)\n", ndev);
882 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
883 readl(dev->base + RXDP),
884 (long)(dev->rx_info.phy_descs),
885 (int)dev->rx_info.next_rx,
886 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
887 (int)dev->rx_info.next_empty,
888 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
889 );
890
891 spin_lock_irqsave(&info->lock, flags);
892 if (!info->up)
893 goto out;
894
895 dprintk("walking descs\n");
896 next_rx = info->next_rx;
897 desc = info->next_rx_desc;
898 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
899 (cmdsts != CMDSTS_OWN)) {
900 struct sk_buff *skb;
901 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
902 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
903
904 dprintk("cmdsts: %08x\n", cmdsts);
905 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
906 dprintk("extsts: %08x\n", extsts);
907
908 skb = info->skbs[next_rx];
909 info->skbs[next_rx] = NULL;
910 info->next_rx = (next_rx + 1) % NR_RX_DESC;
911
912 mb();
913 clear_rx_desc(dev, next_rx);
914
915 pci_unmap_single(dev->pci_dev, bufptr,
916 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
917 len = cmdsts & CMDSTS_LEN_MASK;
918 #ifdef NS83820_VLAN_ACCEL_SUPPORT
919 /* NH: As was mentioned below, this chip is kinda
920 * brain dead about vlan tag stripping. Frames
921 * that are 64 bytes with a vlan header appended
922 * like arp frames, or pings, are flagged as Runts
923 * when the tag is stripped and hardware. This
924 * also means that the OK bit in the descriptor
925 * is cleared when the frame comes in so we have
926 * to do a specific length check here to make sure
927 * the frame would have been ok, had we not stripped
928 * the tag.
929 */
930 if (likely((CMDSTS_OK & cmdsts) ||
931 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
932 #else
933 if (likely(CMDSTS_OK & cmdsts)) {
934 #endif
935 skb_put(skb, len);
936 if (unlikely(!skb))
937 goto netdev_mangle_me_harder_failed;
938 if (cmdsts & CMDSTS_DEST_MULTI)
939 dev->stats.multicast ++;
940 dev->stats.rx_packets ++;
941 dev->stats.rx_bytes += len;
942 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 } else {
945 skb->ip_summed = CHECKSUM_NONE;
946 }
947 skb->protocol = eth_type_trans(skb, ndev);
948 #ifdef NS83820_VLAN_ACCEL_SUPPORT
949 if(extsts & EXTSTS_VPKT) {
950 unsigned short tag;
951 tag = ntohs(extsts & EXTSTS_VTG_MASK);
952 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
953 } else {
954 rx_rc = netif_rx(skb);
955 }
956 #else
957 rx_rc = netif_rx(skb);
958 #endif
959 if (NET_RX_DROP == rx_rc) {
960 netdev_mangle_me_harder_failed:
961 dev->stats.rx_dropped ++;
962 }
963 } else {
964 kfree_skb(skb);
965 }
966
967 nr++;
968 next_rx = info->next_rx;
969 desc = info->descs + (DESC_SIZE * next_rx);
970 }
971 info->next_rx = next_rx;
972 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
973
974 out:
975 if (0 && !nr) {
976 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
977 }
978
979 spin_unlock_irqrestore(&info->lock, flags);
980 }
981
982 static void rx_action(unsigned long _dev)
983 {
984 struct net_device *ndev = (void *)_dev;
985 struct ns83820 *dev = PRIV(ndev);
986 rx_irq(ndev);
987 writel(ihr, dev->base + IHR);
988
989 spin_lock_irq(&dev->misc_lock);
990 dev->IMR_cache |= ISR_RXDESC;
991 writel(dev->IMR_cache, dev->base + IMR);
992 spin_unlock_irq(&dev->misc_lock);
993
994 rx_irq(ndev);
995 ns83820_rx_kick(ndev);
996 }
997
998 /* Packet Transmit code
999 */
1000 static inline void kick_tx(struct ns83820 *dev)
1001 {
1002 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1003 dev, dev->tx_idx, dev->tx_free_idx);
1004 writel(CR_TXE, dev->base + CR);
1005 }
1006
1007 /* No spinlock needed on the transmit irq path as the interrupt handler is
1008 * serialized.
1009 */
1010 static void do_tx_done(struct net_device *ndev)
1011 {
1012 struct ns83820 *dev = PRIV(ndev);
1013 u32 cmdsts, tx_done_idx;
1014 __le32 *desc;
1015
1016 dprintk("do_tx_done(%p)\n", ndev);
1017 tx_done_idx = dev->tx_done_idx;
1018 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1019
1020 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1021 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1022 while ((tx_done_idx != dev->tx_free_idx) &&
1023 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1024 struct sk_buff *skb;
1025 unsigned len;
1026 dma_addr_t addr;
1027
1028 if (cmdsts & CMDSTS_ERR)
1029 dev->stats.tx_errors ++;
1030 if (cmdsts & CMDSTS_OK)
1031 dev->stats.tx_packets ++;
1032 if (cmdsts & CMDSTS_OK)
1033 dev->stats.tx_bytes += cmdsts & 0xffff;
1034
1035 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1036 tx_done_idx, dev->tx_free_idx, cmdsts);
1037 skb = dev->tx_skbs[tx_done_idx];
1038 dev->tx_skbs[tx_done_idx] = NULL;
1039 dprintk("done(%p)\n", skb);
1040
1041 len = cmdsts & CMDSTS_LEN_MASK;
1042 addr = desc_addr_get(desc + DESC_BUFPTR);
1043 if (skb) {
1044 pci_unmap_single(dev->pci_dev,
1045 addr,
1046 len,
1047 PCI_DMA_TODEVICE);
1048 dev_kfree_skb_irq(skb);
1049 atomic_dec(&dev->nr_tx_skbs);
1050 } else
1051 pci_unmap_page(dev->pci_dev,
1052 addr,
1053 len,
1054 PCI_DMA_TODEVICE);
1055
1056 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1057 dev->tx_done_idx = tx_done_idx;
1058 desc[DESC_CMDSTS] = cpu_to_le32(0);
1059 mb();
1060 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1061 }
1062
1063 /* Allow network stack to resume queueing packets after we've
1064 * finished transmitting at least 1/4 of the packets in the queue.
1065 */
1066 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1067 dprintk("start_queue(%p)\n", ndev);
1068 netif_start_queue(ndev);
1069 netif_wake_queue(ndev);
1070 }
1071 }
1072
1073 static void ns83820_cleanup_tx(struct ns83820 *dev)
1074 {
1075 unsigned i;
1076
1077 for (i=0; i<NR_TX_DESC; i++) {
1078 struct sk_buff *skb = dev->tx_skbs[i];
1079 dev->tx_skbs[i] = NULL;
1080 if (skb) {
1081 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1082 pci_unmap_single(dev->pci_dev,
1083 desc_addr_get(desc + DESC_BUFPTR),
1084 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1085 PCI_DMA_TODEVICE);
1086 dev_kfree_skb_irq(skb);
1087 atomic_dec(&dev->nr_tx_skbs);
1088 }
1089 }
1090
1091 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1092 }
1093
1094 /* transmit routine. This code relies on the network layer serializing
1095 * its calls in, but will run happily in parallel with the interrupt
1096 * handler. This code currently has provisions for fragmenting tx buffers
1097 * while trying to track down a bug in either the zero copy code or
1098 * the tx fifo (hence the MAX_FRAG_LEN).
1099 */
1100 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1101 {
1102 struct ns83820 *dev = PRIV(ndev);
1103 u32 free_idx, cmdsts, extsts;
1104 int nr_free, nr_frags;
1105 unsigned tx_done_idx, last_idx;
1106 dma_addr_t buf;
1107 unsigned len;
1108 skb_frag_t *frag;
1109 int stopped = 0;
1110 int do_intr = 0;
1111 volatile __le32 *first_desc;
1112
1113 dprintk("ns83820_hard_start_xmit\n");
1114
1115 nr_frags = skb_shinfo(skb)->nr_frags;
1116 again:
1117 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1118 netif_stop_queue(ndev);
1119 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1120 return 1;
1121 netif_start_queue(ndev);
1122 }
1123
1124 last_idx = free_idx = dev->tx_free_idx;
1125 tx_done_idx = dev->tx_done_idx;
1126 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1127 nr_free -= 1;
1128 if (nr_free <= nr_frags) {
1129 dprintk("stop_queue - not enough(%p)\n", ndev);
1130 netif_stop_queue(ndev);
1131
1132 /* Check again: we may have raced with a tx done irq */
1133 if (dev->tx_done_idx != tx_done_idx) {
1134 dprintk("restart queue(%p)\n", ndev);
1135 netif_start_queue(ndev);
1136 goto again;
1137 }
1138 return 1;
1139 }
1140
1141 if (free_idx == dev->tx_intr_idx) {
1142 do_intr = 1;
1143 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1144 }
1145
1146 nr_free -= nr_frags;
1147 if (nr_free < MIN_TX_DESC_FREE) {
1148 dprintk("stop_queue - last entry(%p)\n", ndev);
1149 netif_stop_queue(ndev);
1150 stopped = 1;
1151 }
1152
1153 frag = skb_shinfo(skb)->frags;
1154 if (!nr_frags)
1155 frag = NULL;
1156 extsts = 0;
1157 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1158 extsts |= EXTSTS_IPPKT;
1159 if (IPPROTO_TCP == ip_hdr(skb)->protocol)
1160 extsts |= EXTSTS_TCPPKT;
1161 else if (IPPROTO_UDP == ip_hdr(skb)->protocol)
1162 extsts |= EXTSTS_UDPPKT;
1163 }
1164
1165 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1166 if(vlan_tx_tag_present(skb)) {
1167 /* fetch the vlan tag info out of the
1168 * ancilliary data if the vlan code
1169 * is using hw vlan acceleration
1170 */
1171 short tag = vlan_tx_tag_get(skb);
1172 extsts |= (EXTSTS_VPKT | htons(tag));
1173 }
1174 #endif
1175
1176 len = skb->len;
1177 if (nr_frags)
1178 len -= skb->data_len;
1179 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1180
1181 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1182
1183 for (;;) {
1184 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1185
1186 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1187 (unsigned long long)buf);
1188 last_idx = free_idx;
1189 free_idx = (free_idx + 1) % NR_TX_DESC;
1190 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1191 desc_addr_set(desc + DESC_BUFPTR, buf);
1192 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1193
1194 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1195 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1196 cmdsts |= len;
1197 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1198
1199 if (!nr_frags)
1200 break;
1201
1202 buf = pci_map_page(dev->pci_dev, frag->page,
1203 frag->page_offset,
1204 frag->size, PCI_DMA_TODEVICE);
1205 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1206 (long long)buf, (long) page_to_pfn(frag->page),
1207 frag->page_offset);
1208 len = frag->size;
1209 frag++;
1210 nr_frags--;
1211 }
1212 dprintk("done pkt\n");
1213
1214 spin_lock_irq(&dev->tx_lock);
1215 dev->tx_skbs[last_idx] = skb;
1216 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1217 dev->tx_free_idx = free_idx;
1218 atomic_inc(&dev->nr_tx_skbs);
1219 spin_unlock_irq(&dev->tx_lock);
1220
1221 kick_tx(dev);
1222
1223 /* Check again: we may have raced with a tx done irq */
1224 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1225 netif_start_queue(ndev);
1226
1227 /* set the transmit start time to catch transmit timeouts */
1228 ndev->trans_start = jiffies;
1229 return 0;
1230 }
1231
1232 static void ns83820_update_stats(struct ns83820 *dev)
1233 {
1234 u8 __iomem *base = dev->base;
1235
1236 /* the DP83820 will freeze counters, so we need to read all of them */
1237 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1238 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1239 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1240 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1241 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1242 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1243 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1244 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1245 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1246 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1247 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1248 }
1249
1250 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1251 {
1252 struct ns83820 *dev = PRIV(ndev);
1253
1254 /* somewhat overkill */
1255 spin_lock_irq(&dev->misc_lock);
1256 ns83820_update_stats(dev);
1257 spin_unlock_irq(&dev->misc_lock);
1258
1259 return &dev->stats;
1260 }
1261
1262 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1263 {
1264 struct ns83820 *dev = PRIV(ndev);
1265 strcpy(info->driver, "ns83820");
1266 strcpy(info->version, VERSION);
1267 strcpy(info->bus_info, pci_name(dev->pci_dev));
1268 }
1269
1270 static u32 ns83820_get_link(struct net_device *ndev)
1271 {
1272 struct ns83820 *dev = PRIV(ndev);
1273 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1274 return cfg & CFG_LNKSTS ? 1 : 0;
1275 }
1276
1277 static const struct ethtool_ops ops = {
1278 .get_drvinfo = ns83820_get_drvinfo,
1279 .get_link = ns83820_get_link
1280 };
1281
1282 /* this function is called in irq context from the ISR */
1283 static void ns83820_mib_isr(struct ns83820 *dev)
1284 {
1285 unsigned long flags;
1286 spin_lock_irqsave(&dev->misc_lock, flags);
1287 ns83820_update_stats(dev);
1288 spin_unlock_irqrestore(&dev->misc_lock, flags);
1289 }
1290
1291 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1292 static irqreturn_t ns83820_irq(int foo, void *data)
1293 {
1294 struct net_device *ndev = data;
1295 struct ns83820 *dev = PRIV(ndev);
1296 u32 isr;
1297 dprintk("ns83820_irq(%p)\n", ndev);
1298
1299 dev->ihr = 0;
1300
1301 isr = readl(dev->base + ISR);
1302 dprintk("irq: %08x\n", isr);
1303 ns83820_do_isr(ndev, isr);
1304 return IRQ_HANDLED;
1305 }
1306
1307 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1308 {
1309 struct ns83820 *dev = PRIV(ndev);
1310 unsigned long flags;
1311
1312 #ifdef DEBUG
1313 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1314 Dprintk("odd isr? 0x%08x\n", isr);
1315 #endif
1316
1317 if (ISR_RXIDLE & isr) {
1318 dev->rx_info.idle = 1;
1319 Dprintk("oh dear, we are idle\n");
1320 ns83820_rx_kick(ndev);
1321 }
1322
1323 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1324 prefetch(dev->rx_info.next_rx_desc);
1325
1326 spin_lock_irqsave(&dev->misc_lock, flags);
1327 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1328 writel(dev->IMR_cache, dev->base + IMR);
1329 spin_unlock_irqrestore(&dev->misc_lock, flags);
1330
1331 tasklet_schedule(&dev->rx_tasklet);
1332 //rx_irq(ndev);
1333 //writel(4, dev->base + IHR);
1334 }
1335
1336 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1337 ns83820_rx_kick(ndev);
1338
1339 if (unlikely(ISR_RXSOVR & isr)) {
1340 //printk("overrun: rxsovr\n");
1341 dev->stats.rx_fifo_errors ++;
1342 }
1343
1344 if (unlikely(ISR_RXORN & isr)) {
1345 //printk("overrun: rxorn\n");
1346 dev->stats.rx_fifo_errors ++;
1347 }
1348
1349 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1350 writel(CR_RXE, dev->base + CR);
1351
1352 if (ISR_TXIDLE & isr) {
1353 u32 txdp;
1354 txdp = readl(dev->base + TXDP);
1355 dprintk("txdp: %08x\n", txdp);
1356 txdp -= dev->tx_phy_descs;
1357 dev->tx_idx = txdp / (DESC_SIZE * 4);
1358 if (dev->tx_idx >= NR_TX_DESC) {
1359 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1360 dev->tx_idx = 0;
1361 }
1362 /* The may have been a race between a pci originated read
1363 * and the descriptor update from the cpu. Just in case,
1364 * kick the transmitter if the hardware thinks it is on a
1365 * different descriptor than we are.
1366 */
1367 if (dev->tx_idx != dev->tx_free_idx)
1368 kick_tx(dev);
1369 }
1370
1371 /* Defer tx ring processing until more than a minimum amount of
1372 * work has accumulated
1373 */
1374 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1375 spin_lock_irqsave(&dev->tx_lock, flags);
1376 do_tx_done(ndev);
1377 spin_unlock_irqrestore(&dev->tx_lock, flags);
1378
1379 /* Disable TxOk if there are no outstanding tx packets.
1380 */
1381 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1382 (dev->IMR_cache & ISR_TXOK)) {
1383 spin_lock_irqsave(&dev->misc_lock, flags);
1384 dev->IMR_cache &= ~ISR_TXOK;
1385 writel(dev->IMR_cache, dev->base + IMR);
1386 spin_unlock_irqrestore(&dev->misc_lock, flags);
1387 }
1388 }
1389
1390 /* The TxIdle interrupt can come in before the transmit has
1391 * completed. Normally we reap packets off of the combination
1392 * of TxDesc and TxIdle and leave TxOk disabled (since it
1393 * occurs on every packet), but when no further irqs of this
1394 * nature are expected, we must enable TxOk.
1395 */
1396 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1397 spin_lock_irqsave(&dev->misc_lock, flags);
1398 dev->IMR_cache |= ISR_TXOK;
1399 writel(dev->IMR_cache, dev->base + IMR);
1400 spin_unlock_irqrestore(&dev->misc_lock, flags);
1401 }
1402
1403 /* MIB interrupt: one of the statistics counters is about to overflow */
1404 if (unlikely(ISR_MIB & isr))
1405 ns83820_mib_isr(dev);
1406
1407 /* PHY: Link up/down/negotiation state change */
1408 if (unlikely(ISR_PHY & isr))
1409 phy_intr(ndev);
1410
1411 #if 0 /* Still working on the interrupt mitigation strategy */
1412 if (dev->ihr)
1413 writel(dev->ihr, dev->base + IHR);
1414 #endif
1415 }
1416
1417 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1418 {
1419 Dprintk("resetting chip...\n");
1420 writel(which, dev->base + CR);
1421 do {
1422 schedule();
1423 } while (readl(dev->base + CR) & which);
1424 Dprintk("okay!\n");
1425 }
1426
1427 static int ns83820_stop(struct net_device *ndev)
1428 {
1429 struct ns83820 *dev = PRIV(ndev);
1430
1431 /* FIXME: protect against interrupt handler? */
1432 del_timer_sync(&dev->tx_watchdog);
1433
1434 /* disable interrupts */
1435 writel(0, dev->base + IMR);
1436 writel(0, dev->base + IER);
1437 readl(dev->base + IER);
1438
1439 dev->rx_info.up = 0;
1440 synchronize_irq(dev->pci_dev->irq);
1441
1442 ns83820_do_reset(dev, CR_RST);
1443
1444 synchronize_irq(dev->pci_dev->irq);
1445
1446 spin_lock_irq(&dev->misc_lock);
1447 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1448 spin_unlock_irq(&dev->misc_lock);
1449
1450 ns83820_cleanup_rx(dev);
1451 ns83820_cleanup_tx(dev);
1452
1453 return 0;
1454 }
1455
1456 static void ns83820_tx_timeout(struct net_device *ndev)
1457 {
1458 struct ns83820 *dev = PRIV(ndev);
1459 u32 tx_done_idx;
1460 __le32 *desc;
1461 unsigned long flags;
1462
1463 spin_lock_irqsave(&dev->tx_lock, flags);
1464
1465 tx_done_idx = dev->tx_done_idx;
1466 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1467
1468 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1469 ndev->name,
1470 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1471
1472 #if defined(DEBUG)
1473 {
1474 u32 isr;
1475 isr = readl(dev->base + ISR);
1476 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1477 ns83820_do_isr(ndev, isr);
1478 }
1479 #endif
1480
1481 do_tx_done(ndev);
1482
1483 tx_done_idx = dev->tx_done_idx;
1484 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1485
1486 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1487 ndev->name,
1488 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1489
1490 spin_unlock_irqrestore(&dev->tx_lock, flags);
1491 }
1492
1493 static void ns83820_tx_watch(unsigned long data)
1494 {
1495 struct net_device *ndev = (void *)data;
1496 struct ns83820 *dev = PRIV(ndev);
1497
1498 #if defined(DEBUG)
1499 printk("ns83820_tx_watch: %u %u %d\n",
1500 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1501 );
1502 #endif
1503
1504 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1505 dev->tx_done_idx != dev->tx_free_idx) {
1506 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1507 ndev->name,
1508 dev->tx_done_idx, dev->tx_free_idx,
1509 atomic_read(&dev->nr_tx_skbs));
1510 ns83820_tx_timeout(ndev);
1511 }
1512
1513 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1514 }
1515
1516 static int ns83820_open(struct net_device *ndev)
1517 {
1518 struct ns83820 *dev = PRIV(ndev);
1519 unsigned i;
1520 u32 desc;
1521 int ret;
1522
1523 dprintk("ns83820_open\n");
1524
1525 writel(0, dev->base + PQCR);
1526
1527 ret = ns83820_setup_rx(ndev);
1528 if (ret)
1529 goto failed;
1530
1531 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1532 for (i=0; i<NR_TX_DESC; i++) {
1533 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1534 = cpu_to_le32(
1535 dev->tx_phy_descs
1536 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1537 }
1538
1539 dev->tx_idx = 0;
1540 dev->tx_done_idx = 0;
1541 desc = dev->tx_phy_descs;
1542 writel(0, dev->base + TXDP_HI);
1543 writel(desc, dev->base + TXDP);
1544
1545 init_timer(&dev->tx_watchdog);
1546 dev->tx_watchdog.data = (unsigned long)ndev;
1547 dev->tx_watchdog.function = ns83820_tx_watch;
1548 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1549
1550 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1551
1552 return 0;
1553
1554 failed:
1555 ns83820_stop(ndev);
1556 return ret;
1557 }
1558
1559 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1560 {
1561 unsigned i;
1562 for (i=0; i<3; i++) {
1563 u32 data;
1564
1565 /* Read from the perfect match memory: this is loaded by
1566 * the chip from the EEPROM via the EELOAD self test.
1567 */
1568 writel(i*2, dev->base + RFCR);
1569 data = readl(dev->base + RFDR);
1570
1571 *mac++ = data;
1572 *mac++ = data >> 8;
1573 }
1574 }
1575
1576 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1577 {
1578 if (new_mtu > RX_BUF_SIZE)
1579 return -EINVAL;
1580 ndev->mtu = new_mtu;
1581 return 0;
1582 }
1583
1584 static void ns83820_set_multicast(struct net_device *ndev)
1585 {
1586 struct ns83820 *dev = PRIV(ndev);
1587 u8 __iomem *rfcr = dev->base + RFCR;
1588 u32 and_mask = 0xffffffff;
1589 u32 or_mask = 0;
1590 u32 val;
1591
1592 if (ndev->flags & IFF_PROMISC)
1593 or_mask |= RFCR_AAU | RFCR_AAM;
1594 else
1595 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1596
1597 if (ndev->flags & IFF_ALLMULTI)
1598 or_mask |= RFCR_AAM;
1599 else
1600 and_mask &= ~RFCR_AAM;
1601
1602 spin_lock_irq(&dev->misc_lock);
1603 val = (readl(rfcr) & and_mask) | or_mask;
1604 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1605 writel(val & ~RFCR_RFEN, rfcr);
1606 writel(val, rfcr);
1607 spin_unlock_irq(&dev->misc_lock);
1608 }
1609
1610 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1611 {
1612 struct ns83820 *dev = PRIV(ndev);
1613 int timed_out = 0;
1614 unsigned long start;
1615 u32 status;
1616 int loops = 0;
1617
1618 dprintk("%s: start %s\n", ndev->name, name);
1619
1620 start = jiffies;
1621
1622 writel(enable, dev->base + PTSCR);
1623 for (;;) {
1624 loops++;
1625 status = readl(dev->base + PTSCR);
1626 if (!(status & enable))
1627 break;
1628 if (status & done)
1629 break;
1630 if (status & fail)
1631 break;
1632 if (time_after_eq(jiffies, start + HZ)) {
1633 timed_out = 1;
1634 break;
1635 }
1636 schedule_timeout_uninterruptible(1);
1637 }
1638
1639 if (status & fail)
1640 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1641 ndev->name, name, status, fail);
1642 else if (timed_out)
1643 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1644 ndev->name, name, status);
1645
1646 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1647 }
1648
1649 #ifdef PHY_CODE_IS_FINISHED
1650 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1651 {
1652 /* drive MDC low */
1653 dev->MEAR_cache &= ~MEAR_MDC;
1654 writel(dev->MEAR_cache, dev->base + MEAR);
1655 readl(dev->base + MEAR);
1656
1657 /* enable output, set bit */
1658 dev->MEAR_cache |= MEAR_MDDIR;
1659 if (bit)
1660 dev->MEAR_cache |= MEAR_MDIO;
1661 else
1662 dev->MEAR_cache &= ~MEAR_MDIO;
1663
1664 /* set the output bit */
1665 writel(dev->MEAR_cache, dev->base + MEAR);
1666 readl(dev->base + MEAR);
1667
1668 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1669 udelay(1);
1670
1671 /* drive MDC high causing the data bit to be latched */
1672 dev->MEAR_cache |= MEAR_MDC;
1673 writel(dev->MEAR_cache, dev->base + MEAR);
1674 readl(dev->base + MEAR);
1675
1676 /* Wait again... */
1677 udelay(1);
1678 }
1679
1680 static int ns83820_mii_read_bit(struct ns83820 *dev)
1681 {
1682 int bit;
1683
1684 /* drive MDC low, disable output */
1685 dev->MEAR_cache &= ~MEAR_MDC;
1686 dev->MEAR_cache &= ~MEAR_MDDIR;
1687 writel(dev->MEAR_cache, dev->base + MEAR);
1688 readl(dev->base + MEAR);
1689
1690 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1691 udelay(1);
1692
1693 /* drive MDC high causing the data bit to be latched */
1694 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1695 dev->MEAR_cache |= MEAR_MDC;
1696 writel(dev->MEAR_cache, dev->base + MEAR);
1697
1698 /* Wait again... */
1699 udelay(1);
1700
1701 return bit;
1702 }
1703
1704 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1705 {
1706 unsigned data = 0;
1707 int i;
1708
1709 /* read some garbage so that we eventually sync up */
1710 for (i=0; i<64; i++)
1711 ns83820_mii_read_bit(dev);
1712
1713 ns83820_mii_write_bit(dev, 0); /* start */
1714 ns83820_mii_write_bit(dev, 1);
1715 ns83820_mii_write_bit(dev, 1); /* opcode read */
1716 ns83820_mii_write_bit(dev, 0);
1717
1718 /* write out the phy address: 5 bits, msb first */
1719 for (i=0; i<5; i++)
1720 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1721
1722 /* write out the register address, 5 bits, msb first */
1723 for (i=0; i<5; i++)
1724 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1725
1726 ns83820_mii_read_bit(dev); /* turn around cycles */
1727 ns83820_mii_read_bit(dev);
1728
1729 /* read in the register data, 16 bits msb first */
1730 for (i=0; i<16; i++) {
1731 data <<= 1;
1732 data |= ns83820_mii_read_bit(dev);
1733 }
1734
1735 return data;
1736 }
1737
1738 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1739 {
1740 int i;
1741
1742 /* read some garbage so that we eventually sync up */
1743 for (i=0; i<64; i++)
1744 ns83820_mii_read_bit(dev);
1745
1746 ns83820_mii_write_bit(dev, 0); /* start */
1747 ns83820_mii_write_bit(dev, 1);
1748 ns83820_mii_write_bit(dev, 0); /* opcode read */
1749 ns83820_mii_write_bit(dev, 1);
1750
1751 /* write out the phy address: 5 bits, msb first */
1752 for (i=0; i<5; i++)
1753 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1754
1755 /* write out the register address, 5 bits, msb first */
1756 for (i=0; i<5; i++)
1757 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1758
1759 ns83820_mii_read_bit(dev); /* turn around cycles */
1760 ns83820_mii_read_bit(dev);
1761
1762 /* read in the register data, 16 bits msb first */
1763 for (i=0; i<16; i++)
1764 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1765
1766 return data;
1767 }
1768
1769 static void ns83820_probe_phy(struct net_device *ndev)
1770 {
1771 struct ns83820 *dev = PRIV(ndev);
1772 static int first;
1773 int i;
1774 #define MII_PHYIDR1 0x02
1775 #define MII_PHYIDR2 0x03
1776
1777 #if 0
1778 if (!first) {
1779 unsigned tmp;
1780 ns83820_mii_read_reg(dev, 1, 0x09);
1781 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1782
1783 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1784 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1785 udelay(1300);
1786 ns83820_mii_read_reg(dev, 1, 0x09);
1787 }
1788 #endif
1789 first = 1;
1790
1791 for (i=1; i<2; i++) {
1792 int j;
1793 unsigned a, b;
1794 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1795 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1796
1797 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1798 // ndev->name, i, a, b);
1799
1800 for (j=0; j<0x16; j+=4) {
1801 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1802 ndev->name, j,
1803 ns83820_mii_read_reg(dev, i, 0 + j),
1804 ns83820_mii_read_reg(dev, i, 1 + j),
1805 ns83820_mii_read_reg(dev, i, 2 + j),
1806 ns83820_mii_read_reg(dev, i, 3 + j)
1807 );
1808 }
1809 }
1810 {
1811 unsigned a, b;
1812 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1813 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1814 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1815 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1816
1817 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1818 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1819 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1820 dprintk("version: 0x%04x 0x%04x\n", a, b);
1821 }
1822 }
1823 #endif
1824
1825 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1826 {
1827 struct net_device *ndev;
1828 struct ns83820 *dev;
1829 long addr;
1830 int err;
1831 int using_dac = 0;
1832
1833 /* See if we can set the dma mask early on; failure is fatal. */
1834 if (sizeof(dma_addr_t) == 8 &&
1835 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1836 using_dac = 1;
1837 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1838 using_dac = 0;
1839 } else {
1840 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1841 return -ENODEV;
1842 }
1843
1844 ndev = alloc_etherdev(sizeof(struct ns83820));
1845 dev = PRIV(ndev);
1846 dev->ndev = ndev;
1847 err = -ENOMEM;
1848 if (!dev)
1849 goto out;
1850
1851 spin_lock_init(&dev->rx_info.lock);
1852 spin_lock_init(&dev->tx_lock);
1853 spin_lock_init(&dev->misc_lock);
1854 dev->pci_dev = pci_dev;
1855
1856 SET_MODULE_OWNER(ndev);
1857 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1858
1859 INIT_WORK(&dev->tq_refill, queue_refill);
1860 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1861
1862 err = pci_enable_device(pci_dev);
1863 if (err) {
1864 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1865 goto out_free;
1866 }
1867
1868 pci_set_master(pci_dev);
1869 addr = pci_resource_start(pci_dev, 1);
1870 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1871 dev->tx_descs = pci_alloc_consistent(pci_dev,
1872 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1873 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1874 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1875 err = -ENOMEM;
1876 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1877 goto out_disable;
1878
1879 dprintk("%p: %08lx %p: %08lx\n",
1880 dev->tx_descs, (long)dev->tx_phy_descs,
1881 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1882
1883 /* disable interrupts */
1884 writel(0, dev->base + IMR);
1885 writel(0, dev->base + IER);
1886 readl(dev->base + IER);
1887
1888 dev->IMR_cache = 0;
1889
1890 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1891 DRV_NAME, ndev);
1892 if (err) {
1893 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1894 pci_dev->irq, err);
1895 goto out_disable;
1896 }
1897
1898 /*
1899 * FIXME: we are holding rtnl_lock() over obscenely long area only
1900 * because some of the setup code uses dev->name. It's Wrong(tm) -
1901 * we should be using driver-specific names for all that stuff.
1902 * For now that will do, but we really need to come back and kill
1903 * most of the dev_alloc_name() users later.
1904 */
1905 rtnl_lock();
1906 err = dev_alloc_name(ndev, ndev->name);
1907 if (err < 0) {
1908 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1909 goto out_free_irq;
1910 }
1911
1912 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1913 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1914 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1915
1916 ndev->open = ns83820_open;
1917 ndev->stop = ns83820_stop;
1918 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1919 ndev->get_stats = ns83820_get_stats;
1920 ndev->change_mtu = ns83820_change_mtu;
1921 ndev->set_multicast_list = ns83820_set_multicast;
1922 SET_ETHTOOL_OPS(ndev, &ops);
1923 ndev->tx_timeout = ns83820_tx_timeout;
1924 ndev->watchdog_timeo = 5 * HZ;
1925 pci_set_drvdata(pci_dev, ndev);
1926
1927 ns83820_do_reset(dev, CR_RST);
1928
1929 /* Must reset the ram bist before running it */
1930 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1931 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1932 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1933 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1934 PTSCR_EEBIST_FAIL);
1935 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1936
1937 /* I love config registers */
1938 dev->CFG_cache = readl(dev->base + CFG);
1939
1940 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1941 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1942 ndev->name);
1943 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1944 if (!(dev->CFG_cache & CFG_DATA64_EN))
1945 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1946 ndev->name);
1947 } else
1948 dev->CFG_cache &= ~(CFG_DATA64_EN);
1949
1950 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1951 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1952 CFG_M64ADDR);
1953 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1954 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1955 dev->CFG_cache |= CFG_REQALG;
1956 dev->CFG_cache |= CFG_POW;
1957 dev->CFG_cache |= CFG_TMRTEST;
1958
1959 /* When compiled with 64 bit addressing, we must always enable
1960 * the 64 bit descriptor format.
1961 */
1962 if (sizeof(dma_addr_t) == 8)
1963 dev->CFG_cache |= CFG_M64ADDR;
1964 if (using_dac)
1965 dev->CFG_cache |= CFG_T64ADDR;
1966
1967 /* Big endian mode does not seem to do what the docs suggest */
1968 dev->CFG_cache &= ~CFG_BEM;
1969
1970 /* setup optical transceiver if we have one */
1971 if (dev->CFG_cache & CFG_TBI_EN) {
1972 printk(KERN_INFO "%s: enabling optical transceiver\n",
1973 ndev->name);
1974 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1975
1976 /* setup auto negotiation feature advertisement */
1977 writel(readl(dev->base + TANAR)
1978 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1979 dev->base + TANAR);
1980
1981 /* start auto negotiation */
1982 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1983 dev->base + TBICR);
1984 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1985 dev->linkstate = LINK_AUTONEGOTIATE;
1986
1987 dev->CFG_cache |= CFG_MODE_1000;
1988 }
1989
1990 writel(dev->CFG_cache, dev->base + CFG);
1991 dprintk("CFG: %08x\n", dev->CFG_cache);
1992
1993 if (reset_phy) {
1994 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1995 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1996 msleep(10);
1997 writel(dev->CFG_cache, dev->base + CFG);
1998 }
1999
2000 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2001 * the PCI layer. FIXME.
2002 */
2003 if (readl(dev->base + SRR))
2004 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2005 #endif
2006
2007 /* Note! The DMA burst size interacts with packet
2008 * transmission, such that the largest packet that
2009 * can be transmitted is 8192 - FLTH - burst size.
2010 * If only the transmit fifo was larger...
2011 */
2012 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2013 * some DELL and COMPAQ SMP systems */
2014 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2015 | ((1600 / 32) * 0x100),
2016 dev->base + TXCFG);
2017
2018 /* Flush the interrupt holdoff timer */
2019 writel(0x000, dev->base + IHR);
2020 writel(0x100, dev->base + IHR);
2021 writel(0x000, dev->base + IHR);
2022
2023 /* Set Rx to full duplex, don't accept runt, errored, long or length
2024 * range errored packets. Use 512 byte DMA.
2025 */
2026 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2027 * some DELL and COMPAQ SMP systems
2028 * Turn on ALP, only we are accpeting Jumbo Packets */
2029 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2030 | RXCFG_STRIPCRC
2031 //| RXCFG_ALP
2032 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2033
2034 /* Disable priority queueing */
2035 writel(0, dev->base + PQCR);
2036
2037 /* Enable IP checksum validation and detetion of VLAN headers.
2038 * Note: do not set the reject options as at least the 0x102
2039 * revision of the chip does not properly accept IP fragments
2040 * at least for UDP.
2041 */
2042 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2043 * the MAC it calculates the packetsize AFTER stripping the VLAN
2044 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2045 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2046 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2047 * it discrards it!. These guys......
2048 * also turn on tag stripping if hardware acceleration is enabled
2049 */
2050 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2051 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2052 #else
2053 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2054 #endif
2055 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2056
2057 /* Enable per-packet TCP/UDP/IP checksumming
2058 * and per packet vlan tag insertion if
2059 * vlan hardware acceleration is enabled
2060 */
2061 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2062 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2063 #else
2064 #define VTCR_INIT_VALUE VTCR_PPCHK
2065 #endif
2066 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2067
2068 /* Ramit : Enable async and sync pause frames */
2069 /* writel(0, dev->base + PCR); */
2070 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2071 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2072 dev->base + PCR);
2073
2074 /* Disable Wake On Lan */
2075 writel(0, dev->base + WCSR);
2076
2077 ns83820_getmac(dev, ndev->dev_addr);
2078
2079 /* Yes, we support dumb IP checksum on transmit */
2080 ndev->features |= NETIF_F_SG;
2081 ndev->features |= NETIF_F_IP_CSUM;
2082
2083 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2084 /* We also support hardware vlan acceleration */
2085 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2086 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2087 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2088 #endif
2089
2090 if (using_dac) {
2091 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2092 ndev->name);
2093 ndev->features |= NETIF_F_HIGHDMA;
2094 }
2095
2096 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2097 ndev->name,
2098 (unsigned)readl(dev->base + SRR) >> 8,
2099 (unsigned)readl(dev->base + SRR) & 0xff,
2100 ndev->dev_addr[0], ndev->dev_addr[1],
2101 ndev->dev_addr[2], ndev->dev_addr[3],
2102 ndev->dev_addr[4], ndev->dev_addr[5],
2103 addr, pci_dev->irq,
2104 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2105 );
2106
2107 #ifdef PHY_CODE_IS_FINISHED
2108 ns83820_probe_phy(ndev);
2109 #endif
2110
2111 err = register_netdevice(ndev);
2112 if (err) {
2113 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2114 goto out_cleanup;
2115 }
2116 rtnl_unlock();
2117
2118 return 0;
2119
2120 out_cleanup:
2121 writel(0, dev->base + IMR); /* paranoia */
2122 writel(0, dev->base + IER);
2123 readl(dev->base + IER);
2124 out_free_irq:
2125 rtnl_unlock();
2126 free_irq(pci_dev->irq, ndev);
2127 out_disable:
2128 if (dev->base)
2129 iounmap(dev->base);
2130 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2131 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2132 pci_disable_device(pci_dev);
2133 out_free:
2134 free_netdev(ndev);
2135 pci_set_drvdata(pci_dev, NULL);
2136 out:
2137 return err;
2138 }
2139
2140 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2141 {
2142 struct net_device *ndev = pci_get_drvdata(pci_dev);
2143 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2144
2145 if (!ndev) /* paranoia */
2146 return;
2147
2148 writel(0, dev->base + IMR); /* paranoia */
2149 writel(0, dev->base + IER);
2150 readl(dev->base + IER);
2151
2152 unregister_netdev(ndev);
2153 free_irq(dev->pci_dev->irq, ndev);
2154 iounmap(dev->base);
2155 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2156 dev->tx_descs, dev->tx_phy_descs);
2157 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2158 dev->rx_info.descs, dev->rx_info.phy_descs);
2159 pci_disable_device(dev->pci_dev);
2160 free_netdev(ndev);
2161 pci_set_drvdata(pci_dev, NULL);
2162 }
2163
2164 static struct pci_device_id ns83820_pci_tbl[] = {
2165 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2166 { 0, },
2167 };
2168
2169 static struct pci_driver driver = {
2170 .name = "ns83820",
2171 .id_table = ns83820_pci_tbl,
2172 .probe = ns83820_init_one,
2173 .remove = __devexit_p(ns83820_remove_one),
2174 #if 0 /* FIXME: implement */
2175 .suspend = ,
2176 .resume = ,
2177 #endif
2178 };
2179
2180
2181 static int __init ns83820_init(void)
2182 {
2183 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2184 return pci_register_driver(&driver);
2185 }
2186
2187 static void __exit ns83820_exit(void)
2188 {
2189 pci_unregister_driver(&driver);
2190 }
2191
2192 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2193 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2194 MODULE_LICENSE("GPL");
2195
2196 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2197
2198 module_param(lnksts, int, 0);
2199 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2200
2201 module_param(ihr, int, 0);
2202 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2203
2204 module_param(reset_phy, int, 0);
2205 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2206
2207 module_init(ns83820_init);
2208 module_exit(ns83820_exit);
WRT350N Kernel Patches