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mm/slab.c: proper prototypes
[wrt350n-kernel.git] / drivers / net / skge.c
blob21afe108d3cb3908efd888650104a09a0b3b4d46
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
59 #define BLINK_MS 250
60 #define LINK_HZ (HZ/2)
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
110
111 static int skge_get_regs_len(struct net_device *dev)
112 {
113 return 0x4000;
114 }
115
116 /*
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
120 */
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123 {
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
126
127 regs->version = 1;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
130
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
133 }
134
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32 wol_supported(const struct skge_hw *hw)
137 {
138 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
139 return WAKE_MAGIC | WAKE_PHY;
140 else
141 return 0;
142 }
143
144 static u32 pci_wake_enabled(struct pci_dev *dev)
145 {
146 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
147 u16 value;
148
149 /* If device doesn't support PM Capabilities, but request is to disable
150 * wake events, it's a nop; otherwise fail */
151 if (!pm)
152 return 0;
153
154 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
155
156 value &= PCI_PM_CAP_PME_MASK;
157 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
158
159 return value != 0;
160 }
161
162 static void skge_wol_init(struct skge_port *skge)
163 {
164 struct skge_hw *hw = skge->hw;
165 int port = skge->port;
166 u16 ctrl;
167
168 skge_write16(hw, B0_CTST, CS_RST_CLR);
169 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
170
171 /* Turn on Vaux */
172 skge_write8(hw, B0_POWER_CTRL,
173 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
174
175 /* WA code for COMA mode -- clear PHY reset */
176 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
177 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
178 u32 reg = skge_read32(hw, B2_GP_IO);
179 reg |= GP_DIR_9;
180 reg &= ~GP_IO_9;
181 skge_write32(hw, B2_GP_IO, reg);
182 }
183
184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
185 GPC_DIS_SLEEP |
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_SET);
188
189 skge_write32(hw, SK_REG(port, GPHY_CTRL),
190 GPC_DIS_SLEEP |
191 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
192 GPC_ANEG_1 | GPC_RST_CLR);
193
194 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
195
196 /* Force to 10/100 skge_reset will re-enable on resume */
197 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
198 PHY_AN_100FULL | PHY_AN_100HALF |
199 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
200 /* no 1000 HD/FD */
201 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
202 gm_phy_write(hw, port, PHY_MARV_CTRL,
203 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
204 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
205
206
207 /* Set GMAC to no flow control and auto update for speed/duplex */
208 gma_write16(hw, port, GM_GP_CTRL,
209 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
210 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
211
212 /* Set WOL address */
213 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
214 skge->netdev->dev_addr, ETH_ALEN);
215
216 /* Turn on appropriate WOL control bits */
217 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
218 ctrl = 0;
219 if (skge->wol & WAKE_PHY)
220 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
221 else
222 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
223
224 if (skge->wol & WAKE_MAGIC)
225 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
226 else
227 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
228
229 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
230 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
231
232 /* block receiver */
233 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
234 }
235
236 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
237 {
238 struct skge_port *skge = netdev_priv(dev);
239
240 wol->supported = wol_supported(skge->hw);
241 wol->wolopts = skge->wol;
242 }
243
244 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
245 {
246 struct skge_port *skge = netdev_priv(dev);
247 struct skge_hw *hw = skge->hw;
248
249 if (wol->wolopts & ~wol_supported(hw))
250 return -EOPNOTSUPP;
251
252 skge->wol = wol->wolopts;
253 return 0;
254 }
255
256 /* Determine supported/advertised modes based on hardware.
257 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
258 */
259 static u32 skge_supported_modes(const struct skge_hw *hw)
260 {
261 u32 supported;
262
263 if (hw->copper) {
264 supported = SUPPORTED_10baseT_Half
265 | SUPPORTED_10baseT_Full
266 | SUPPORTED_100baseT_Half
267 | SUPPORTED_100baseT_Full
268 | SUPPORTED_1000baseT_Half
269 | SUPPORTED_1000baseT_Full
270 | SUPPORTED_Autoneg| SUPPORTED_TP;
271
272 if (hw->chip_id == CHIP_ID_GENESIS)
273 supported &= ~(SUPPORTED_10baseT_Half
274 | SUPPORTED_10baseT_Full
275 | SUPPORTED_100baseT_Half
276 | SUPPORTED_100baseT_Full);
277
278 else if (hw->chip_id == CHIP_ID_YUKON)
279 supported &= ~SUPPORTED_1000baseT_Half;
280 } else
281 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
282 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
283
284 return supported;
285 }
286
287 static int skge_get_settings(struct net_device *dev,
288 struct ethtool_cmd *ecmd)
289 {
290 struct skge_port *skge = netdev_priv(dev);
291 struct skge_hw *hw = skge->hw;
292
293 ecmd->transceiver = XCVR_INTERNAL;
294 ecmd->supported = skge_supported_modes(hw);
295
296 if (hw->copper) {
297 ecmd->port = PORT_TP;
298 ecmd->phy_address = hw->phy_addr;
299 } else
300 ecmd->port = PORT_FIBRE;
301
302 ecmd->advertising = skge->advertising;
303 ecmd->autoneg = skge->autoneg;
304 ecmd->speed = skge->speed;
305 ecmd->duplex = skge->duplex;
306 return 0;
307 }
308
309 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
310 {
311 struct skge_port *skge = netdev_priv(dev);
312 const struct skge_hw *hw = skge->hw;
313 u32 supported = skge_supported_modes(hw);
314
315 if (ecmd->autoneg == AUTONEG_ENABLE) {
316 ecmd->advertising = supported;
317 skge->duplex = -1;
318 skge->speed = -1;
319 } else {
320 u32 setting;
321
322 switch (ecmd->speed) {
323 case SPEED_1000:
324 if (ecmd->duplex == DUPLEX_FULL)
325 setting = SUPPORTED_1000baseT_Full;
326 else if (ecmd->duplex == DUPLEX_HALF)
327 setting = SUPPORTED_1000baseT_Half;
328 else
329 return -EINVAL;
330 break;
331 case SPEED_100:
332 if (ecmd->duplex == DUPLEX_FULL)
333 setting = SUPPORTED_100baseT_Full;
334 else if (ecmd->duplex == DUPLEX_HALF)
335 setting = SUPPORTED_100baseT_Half;
336 else
337 return -EINVAL;
338 break;
339
340 case SPEED_10:
341 if (ecmd->duplex == DUPLEX_FULL)
342 setting = SUPPORTED_10baseT_Full;
343 else if (ecmd->duplex == DUPLEX_HALF)
344 setting = SUPPORTED_10baseT_Half;
345 else
346 return -EINVAL;
347 break;
348 default:
349 return -EINVAL;
350 }
351
352 if ((setting & supported) == 0)
353 return -EINVAL;
354
355 skge->speed = ecmd->speed;
356 skge->duplex = ecmd->duplex;
357 }
358
359 skge->autoneg = ecmd->autoneg;
360 skge->advertising = ecmd->advertising;
361
362 if (netif_running(dev))
363 skge_phy_reset(skge);
364
365 return (0);
366 }
367
368 static void skge_get_drvinfo(struct net_device *dev,
369 struct ethtool_drvinfo *info)
370 {
371 struct skge_port *skge = netdev_priv(dev);
372
373 strcpy(info->driver, DRV_NAME);
374 strcpy(info->version, DRV_VERSION);
375 strcpy(info->fw_version, "N/A");
376 strcpy(info->bus_info, pci_name(skge->hw->pdev));
377 }
378
379 static const struct skge_stat {
380 char name[ETH_GSTRING_LEN];
381 u16 xmac_offset;
382 u16 gma_offset;
383 } skge_stats[] = {
384 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
385 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
386
387 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
388 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
389 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
390 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
391 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
392 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
393 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
394 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
395
396 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
397 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
398 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
399 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
400 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
401 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
402
403 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
404 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
405 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
406 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
408 };
409
410 static int skge_get_stats_count(struct net_device *dev)
411 {
412 return ARRAY_SIZE(skge_stats);
413 }
414
415 static void skge_get_ethtool_stats(struct net_device *dev,
416 struct ethtool_stats *stats, u64 *data)
417 {
418 struct skge_port *skge = netdev_priv(dev);
419
420 if (skge->hw->chip_id == CHIP_ID_GENESIS)
421 genesis_get_stats(skge, data);
422 else
423 yukon_get_stats(skge, data);
424 }
425
426 /* Use hardware MIB variables for critical path statistics and
427 * transmit feedback not reported at interrupt.
428 * Other errors are accounted for in interrupt handler.
429 */
430 static struct net_device_stats *skge_get_stats(struct net_device *dev)
431 {
432 struct skge_port *skge = netdev_priv(dev);
433 u64 data[ARRAY_SIZE(skge_stats)];
434
435 if (skge->hw->chip_id == CHIP_ID_GENESIS)
436 genesis_get_stats(skge, data);
437 else
438 yukon_get_stats(skge, data);
439
440 skge->net_stats.tx_bytes = data[0];
441 skge->net_stats.rx_bytes = data[1];
442 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
443 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
444 skge->net_stats.multicast = data[3] + data[5];
445 skge->net_stats.collisions = data[10];
446 skge->net_stats.tx_aborted_errors = data[12];
447
448 return &skge->net_stats;
449 }
450
451 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
452 {
453 int i;
454
455 switch (stringset) {
456 case ETH_SS_STATS:
457 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
458 memcpy(data + i * ETH_GSTRING_LEN,
459 skge_stats[i].name, ETH_GSTRING_LEN);
460 break;
461 }
462 }
463
464 static void skge_get_ring_param(struct net_device *dev,
465 struct ethtool_ringparam *p)
466 {
467 struct skge_port *skge = netdev_priv(dev);
468
469 p->rx_max_pending = MAX_RX_RING_SIZE;
470 p->tx_max_pending = MAX_TX_RING_SIZE;
471 p->rx_mini_max_pending = 0;
472 p->rx_jumbo_max_pending = 0;
473
474 p->rx_pending = skge->rx_ring.count;
475 p->tx_pending = skge->tx_ring.count;
476 p->rx_mini_pending = 0;
477 p->rx_jumbo_pending = 0;
478 }
479
480 static int skge_set_ring_param(struct net_device *dev,
481 struct ethtool_ringparam *p)
482 {
483 struct skge_port *skge = netdev_priv(dev);
484 int err;
485
486 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
487 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
488 return -EINVAL;
489
490 skge->rx_ring.count = p->rx_pending;
491 skge->tx_ring.count = p->tx_pending;
492
493 if (netif_running(dev)) {
494 skge_down(dev);
495 err = skge_up(dev);
496 if (err)
497 dev_close(dev);
498 }
499
500 return 0;
501 }
502
503 static u32 skge_get_msglevel(struct net_device *netdev)
504 {
505 struct skge_port *skge = netdev_priv(netdev);
506 return skge->msg_enable;
507 }
508
509 static void skge_set_msglevel(struct net_device *netdev, u32 value)
510 {
511 struct skge_port *skge = netdev_priv(netdev);
512 skge->msg_enable = value;
513 }
514
515 static int skge_nway_reset(struct net_device *dev)
516 {
517 struct skge_port *skge = netdev_priv(dev);
518
519 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
520 return -EINVAL;
521
522 skge_phy_reset(skge);
523 return 0;
524 }
525
526 static int skge_set_sg(struct net_device *dev, u32 data)
527 {
528 struct skge_port *skge = netdev_priv(dev);
529 struct skge_hw *hw = skge->hw;
530
531 if (hw->chip_id == CHIP_ID_GENESIS && data)
532 return -EOPNOTSUPP;
533 return ethtool_op_set_sg(dev, data);
534 }
535
536 static int skge_set_tx_csum(struct net_device *dev, u32 data)
537 {
538 struct skge_port *skge = netdev_priv(dev);
539 struct skge_hw *hw = skge->hw;
540
541 if (hw->chip_id == CHIP_ID_GENESIS && data)
542 return -EOPNOTSUPP;
543
544 return ethtool_op_set_tx_csum(dev, data);
545 }
546
547 static u32 skge_get_rx_csum(struct net_device *dev)
548 {
549 struct skge_port *skge = netdev_priv(dev);
550
551 return skge->rx_csum;
552 }
553
554 /* Only Yukon supports checksum offload. */
555 static int skge_set_rx_csum(struct net_device *dev, u32 data)
556 {
557 struct skge_port *skge = netdev_priv(dev);
558
559 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
560 return -EOPNOTSUPP;
561
562 skge->rx_csum = data;
563 return 0;
564 }
565
566 static void skge_get_pauseparam(struct net_device *dev,
567 struct ethtool_pauseparam *ecmd)
568 {
569 struct skge_port *skge = netdev_priv(dev);
570
571 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
572 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
573 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
574
575 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
576 }
577
578 static int skge_set_pauseparam(struct net_device *dev,
579 struct ethtool_pauseparam *ecmd)
580 {
581 struct skge_port *skge = netdev_priv(dev);
582 struct ethtool_pauseparam old;
583
584 skge_get_pauseparam(dev, &old);
585
586 if (ecmd->autoneg != old.autoneg)
587 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
588 else {
589 if (ecmd->rx_pause && ecmd->tx_pause)
590 skge->flow_control = FLOW_MODE_SYMMETRIC;
591 else if (ecmd->rx_pause && !ecmd->tx_pause)
592 skge->flow_control = FLOW_MODE_SYM_OR_REM;
593 else if (!ecmd->rx_pause && ecmd->tx_pause)
594 skge->flow_control = FLOW_MODE_LOC_SEND;
595 else
596 skge->flow_control = FLOW_MODE_NONE;
597 }
598
599 if (netif_running(dev))
600 skge_phy_reset(skge);
601
602 return 0;
603 }
604
605 /* Chip internal frequency for clock calculations */
606 static inline u32 hwkhz(const struct skge_hw *hw)
607 {
608 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
609 }
610
611 /* Chip HZ to microseconds */
612 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
613 {
614 return (ticks * 1000) / hwkhz(hw);
615 }
616
617 /* Microseconds to chip HZ */
618 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
619 {
620 return hwkhz(hw) * usec / 1000;
621 }
622
623 static int skge_get_coalesce(struct net_device *dev,
624 struct ethtool_coalesce *ecmd)
625 {
626 struct skge_port *skge = netdev_priv(dev);
627 struct skge_hw *hw = skge->hw;
628 int port = skge->port;
629
630 ecmd->rx_coalesce_usecs = 0;
631 ecmd->tx_coalesce_usecs = 0;
632
633 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
634 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
635 u32 msk = skge_read32(hw, B2_IRQM_MSK);
636
637 if (msk & rxirqmask[port])
638 ecmd->rx_coalesce_usecs = delay;
639 if (msk & txirqmask[port])
640 ecmd->tx_coalesce_usecs = delay;
641 }
642
643 return 0;
644 }
645
646 /* Note: interrupt timer is per board, but can turn on/off per port */
647 static int skge_set_coalesce(struct net_device *dev,
648 struct ethtool_coalesce *ecmd)
649 {
650 struct skge_port *skge = netdev_priv(dev);
651 struct skge_hw *hw = skge->hw;
652 int port = skge->port;
653 u32 msk = skge_read32(hw, B2_IRQM_MSK);
654 u32 delay = 25;
655
656 if (ecmd->rx_coalesce_usecs == 0)
657 msk &= ~rxirqmask[port];
658 else if (ecmd->rx_coalesce_usecs < 25 ||
659 ecmd->rx_coalesce_usecs > 33333)
660 return -EINVAL;
661 else {
662 msk |= rxirqmask[port];
663 delay = ecmd->rx_coalesce_usecs;
664 }
665
666 if (ecmd->tx_coalesce_usecs == 0)
667 msk &= ~txirqmask[port];
668 else if (ecmd->tx_coalesce_usecs < 25 ||
669 ecmd->tx_coalesce_usecs > 33333)
670 return -EINVAL;
671 else {
672 msk |= txirqmask[port];
673 delay = min(delay, ecmd->rx_coalesce_usecs);
674 }
675
676 skge_write32(hw, B2_IRQM_MSK, msk);
677 if (msk == 0)
678 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
679 else {
680 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
681 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
682 }
683 return 0;
684 }
685
686 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
687 static void skge_led(struct skge_port *skge, enum led_mode mode)
688 {
689 struct skge_hw *hw = skge->hw;
690 int port = skge->port;
691
692 spin_lock_bh(&hw->phy_lock);
693 if (hw->chip_id == CHIP_ID_GENESIS) {
694 switch (mode) {
695 case LED_MODE_OFF:
696 if (hw->phy_type == SK_PHY_BCOM)
697 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
698 else {
699 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
700 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
701 }
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
703 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
705 break;
706
707 case LED_MODE_ON:
708 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
709 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
710
711 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
712 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
713
714 break;
715
716 case LED_MODE_TST:
717 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
718 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
719 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
720
721 if (hw->phy_type == SK_PHY_BCOM)
722 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
723 else {
724 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
725 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
726 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
727 }
728
729 }
730 } else {
731 switch (mode) {
732 case LED_MODE_OFF:
733 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
734 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
735 PHY_M_LED_MO_DUP(MO_LED_OFF) |
736 PHY_M_LED_MO_10(MO_LED_OFF) |
737 PHY_M_LED_MO_100(MO_LED_OFF) |
738 PHY_M_LED_MO_1000(MO_LED_OFF) |
739 PHY_M_LED_MO_RX(MO_LED_OFF));
740 break;
741 case LED_MODE_ON:
742 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
743 PHY_M_LED_PULS_DUR(PULS_170MS) |
744 PHY_M_LED_BLINK_RT(BLINK_84MS) |
745 PHY_M_LEDC_TX_CTRL |
746 PHY_M_LEDC_DP_CTRL);
747
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
749 PHY_M_LED_MO_RX(MO_LED_OFF) |
750 (skge->speed == SPEED_100 ?
751 PHY_M_LED_MO_100(MO_LED_ON) : 0));
752 break;
753 case LED_MODE_TST:
754 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
755 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
756 PHY_M_LED_MO_DUP(MO_LED_ON) |
757 PHY_M_LED_MO_10(MO_LED_ON) |
758 PHY_M_LED_MO_100(MO_LED_ON) |
759 PHY_M_LED_MO_1000(MO_LED_ON) |
760 PHY_M_LED_MO_RX(MO_LED_ON));
761 }
762 }
763 spin_unlock_bh(&hw->phy_lock);
764 }
765
766 /* blink LED's for finding board */
767 static int skge_phys_id(struct net_device *dev, u32 data)
768 {
769 struct skge_port *skge = netdev_priv(dev);
770 unsigned long ms;
771 enum led_mode mode = LED_MODE_TST;
772
773 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
774 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
775 else
776 ms = data * 1000;
777
778 while (ms > 0) {
779 skge_led(skge, mode);
780 mode ^= LED_MODE_TST;
781
782 if (msleep_interruptible(BLINK_MS))
783 break;
784 ms -= BLINK_MS;
785 }
786
787 /* back to regular LED state */
788 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
789
790 return 0;
791 }
792
793 static const struct ethtool_ops skge_ethtool_ops = {
794 .get_settings = skge_get_settings,
795 .set_settings = skge_set_settings,
796 .get_drvinfo = skge_get_drvinfo,
797 .get_regs_len = skge_get_regs_len,
798 .get_regs = skge_get_regs,
799 .get_wol = skge_get_wol,
800 .set_wol = skge_set_wol,
801 .get_msglevel = skge_get_msglevel,
802 .set_msglevel = skge_set_msglevel,
803 .nway_reset = skge_nway_reset,
804 .get_link = ethtool_op_get_link,
805 .get_ringparam = skge_get_ring_param,
806 .set_ringparam = skge_set_ring_param,
807 .get_pauseparam = skge_get_pauseparam,
808 .set_pauseparam = skge_set_pauseparam,
809 .get_coalesce = skge_get_coalesce,
810 .set_coalesce = skge_set_coalesce,
811 .get_sg = ethtool_op_get_sg,
812 .set_sg = skge_set_sg,
813 .get_tx_csum = ethtool_op_get_tx_csum,
814 .set_tx_csum = skge_set_tx_csum,
815 .get_rx_csum = skge_get_rx_csum,
816 .set_rx_csum = skge_set_rx_csum,
817 .get_strings = skge_get_strings,
818 .phys_id = skge_phys_id,
819 .get_stats_count = skge_get_stats_count,
820 .get_ethtool_stats = skge_get_ethtool_stats,
821 .get_perm_addr = ethtool_op_get_perm_addr,
822 };
823
824 /*
825 * Allocate ring elements and chain them together
826 * One-to-one association of board descriptors with ring elements
827 */
828 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
829 {
830 struct skge_tx_desc *d;
831 struct skge_element *e;
832 int i;
833
834 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
835 if (!ring->start)
836 return -ENOMEM;
837
838 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
839 e->desc = d;
840 if (i == ring->count - 1) {
841 e->next = ring->start;
842 d->next_offset = base;
843 } else {
844 e->next = e + 1;
845 d->next_offset = base + (i+1) * sizeof(*d);
846 }
847 }
848 ring->to_use = ring->to_clean = ring->start;
849
850 return 0;
851 }
852
853 /* Allocate and setup a new buffer for receiving */
854 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
855 struct sk_buff *skb, unsigned int bufsize)
856 {
857 struct skge_rx_desc *rd = e->desc;
858 u64 map;
859
860 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
861 PCI_DMA_FROMDEVICE);
862
863 rd->dma_lo = map;
864 rd->dma_hi = map >> 32;
865 e->skb = skb;
866 rd->csum1_start = ETH_HLEN;
867 rd->csum2_start = ETH_HLEN;
868 rd->csum1 = 0;
869 rd->csum2 = 0;
870
871 wmb();
872
873 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
874 pci_unmap_addr_set(e, mapaddr, map);
875 pci_unmap_len_set(e, maplen, bufsize);
876 }
877
878 /* Resume receiving using existing skb,
879 * Note: DMA address is not changed by chip.
880 * MTU not changed while receiver active.
881 */
882 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
883 {
884 struct skge_rx_desc *rd = e->desc;
885
886 rd->csum2 = 0;
887 rd->csum2_start = ETH_HLEN;
888
889 wmb();
890
891 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
892 }
893
894
895 /* Free all buffers in receive ring, assumes receiver stopped */
896 static void skge_rx_clean(struct skge_port *skge)
897 {
898 struct skge_hw *hw = skge->hw;
899 struct skge_ring *ring = &skge->rx_ring;
900 struct skge_element *e;
901
902 e = ring->start;
903 do {
904 struct skge_rx_desc *rd = e->desc;
905 rd->control = 0;
906 if (e->skb) {
907 pci_unmap_single(hw->pdev,
908 pci_unmap_addr(e, mapaddr),
909 pci_unmap_len(e, maplen),
910 PCI_DMA_FROMDEVICE);
911 dev_kfree_skb(e->skb);
912 e->skb = NULL;
913 }
914 } while ((e = e->next) != ring->start);
915 }
916
917
918 /* Allocate buffers for receive ring
919 * For receive: to_clean is next received frame.
920 */
921 static int skge_rx_fill(struct net_device *dev)
922 {
923 struct skge_port *skge = netdev_priv(dev);
924 struct skge_ring *ring = &skge->rx_ring;
925 struct skge_element *e;
926
927 e = ring->start;
928 do {
929 struct sk_buff *skb;
930
931 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
932 GFP_KERNEL);
933 if (!skb)
934 return -ENOMEM;
935
936 skb_reserve(skb, NET_IP_ALIGN);
937 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
938 } while ( (e = e->next) != ring->start);
939
940 ring->to_clean = ring->start;
941 return 0;
942 }
943
944 static const char *skge_pause(enum pause_status status)
945 {
946 switch(status) {
947 case FLOW_STAT_NONE:
948 return "none";
949 case FLOW_STAT_REM_SEND:
950 return "rx only";
951 case FLOW_STAT_LOC_SEND:
952 return "tx_only";
953 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
954 return "both";
955 default:
956 return "indeterminated";
957 }
958 }
959
960
961 static void skge_link_up(struct skge_port *skge)
962 {
963 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
964 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
965
966 netif_carrier_on(skge->netdev);
967 netif_wake_queue(skge->netdev);
968
969 if (netif_msg_link(skge)) {
970 printk(KERN_INFO PFX
971 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
972 skge->netdev->name, skge->speed,
973 skge->duplex == DUPLEX_FULL ? "full" : "half",
974 skge_pause(skge->flow_status));
975 }
976 }
977
978 static void skge_link_down(struct skge_port *skge)
979 {
980 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
981 netif_carrier_off(skge->netdev);
982 netif_stop_queue(skge->netdev);
983
984 if (netif_msg_link(skge))
985 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
986 }
987
988
989 static void xm_link_down(struct skge_hw *hw, int port)
990 {
991 struct net_device *dev = hw->dev[port];
992 struct skge_port *skge = netdev_priv(dev);
993 u16 cmd, msk;
994
995 if (hw->phy_type == SK_PHY_XMAC) {
996 msk = xm_read16(hw, port, XM_IMSK);
997 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
998 xm_write16(hw, port, XM_IMSK, msk);
999 }
1000
1001 cmd = xm_read16(hw, port, XM_MMU_CMD);
1002 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1003 xm_write16(hw, port, XM_MMU_CMD, cmd);
1004 /* dummy read to ensure writing */
1005 (void) xm_read16(hw, port, XM_MMU_CMD);
1006
1007 if (netif_carrier_ok(dev))
1008 skge_link_down(skge);
1009 }
1010
1011 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1012 {
1013 int i;
1014
1015 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1016 *val = xm_read16(hw, port, XM_PHY_DATA);
1017
1018 if (hw->phy_type == SK_PHY_XMAC)
1019 goto ready;
1020
1021 for (i = 0; i < PHY_RETRIES; i++) {
1022 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1023 goto ready;
1024 udelay(1);
1025 }
1026
1027 return -ETIMEDOUT;
1028 ready:
1029 *val = xm_read16(hw, port, XM_PHY_DATA);
1030
1031 return 0;
1032 }
1033
1034 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1035 {
1036 u16 v = 0;
1037 if (__xm_phy_read(hw, port, reg, &v))
1038 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1039 hw->dev[port]->name);
1040 return v;
1041 }
1042
1043 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1044 {
1045 int i;
1046
1047 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1048 for (i = 0; i < PHY_RETRIES; i++) {
1049 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1050 goto ready;
1051 udelay(1);
1052 }
1053 return -EIO;
1054
1055 ready:
1056 xm_write16(hw, port, XM_PHY_DATA, val);
1057 for (i = 0; i < PHY_RETRIES; i++) {
1058 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1059 return 0;
1060 udelay(1);
1061 }
1062 return -ETIMEDOUT;
1063 }
1064
1065 static void genesis_init(struct skge_hw *hw)
1066 {
1067 /* set blink source counter */
1068 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1069 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1070
1071 /* configure mac arbiter */
1072 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1073
1074 /* configure mac arbiter timeout values */
1075 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1076 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1077 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1078 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1079
1080 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1081 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1082 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1083 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1084
1085 /* configure packet arbiter timeout */
1086 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1087 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1088 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1089 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1090 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1091 }
1092
1093 static void genesis_reset(struct skge_hw *hw, int port)
1094 {
1095 const u8 zero[8] = { 0 };
1096
1097 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1098
1099 /* reset the statistics module */
1100 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1101 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1102 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1103 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1104 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1105
1106 /* disable Broadcom PHY IRQ */
1107 if (hw->phy_type == SK_PHY_BCOM)
1108 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1109
1110 xm_outhash(hw, port, XM_HSM, zero);
1111 }
1112
1113
1114 /* Convert mode to MII values */
1115 static const u16 phy_pause_map[] = {
1116 [FLOW_MODE_NONE] = 0,
1117 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1118 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1119 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1120 };
1121
1122 /* special defines for FIBER (88E1011S only) */
1123 static const u16 fiber_pause_map[] = {
1124 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1125 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1126 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1127 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1128 };
1129
1130
1131 /* Check status of Broadcom phy link */
1132 static void bcom_check_link(struct skge_hw *hw, int port)
1133 {
1134 struct net_device *dev = hw->dev[port];
1135 struct skge_port *skge = netdev_priv(dev);
1136 u16 status;
1137
1138 /* read twice because of latch */
1139 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1140 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1141
1142 if ((status & PHY_ST_LSYNC) == 0) {
1143 xm_link_down(hw, port);
1144 return;
1145 }
1146
1147 if (skge->autoneg == AUTONEG_ENABLE) {
1148 u16 lpa, aux;
1149
1150 if (!(status & PHY_ST_AN_OVER))
1151 return;
1152
1153 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1154 if (lpa & PHY_B_AN_RF) {
1155 printk(KERN_NOTICE PFX "%s: remote fault\n",
1156 dev->name);
1157 return;
1158 }
1159
1160 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1161
1162 /* Check Duplex mismatch */
1163 switch (aux & PHY_B_AS_AN_RES_MSK) {
1164 case PHY_B_RES_1000FD:
1165 skge->duplex = DUPLEX_FULL;
1166 break;
1167 case PHY_B_RES_1000HD:
1168 skge->duplex = DUPLEX_HALF;
1169 break;
1170 default:
1171 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1172 dev->name);
1173 return;
1174 }
1175
1176 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1177 switch (aux & PHY_B_AS_PAUSE_MSK) {
1178 case PHY_B_AS_PAUSE_MSK:
1179 skge->flow_status = FLOW_STAT_SYMMETRIC;
1180 break;
1181 case PHY_B_AS_PRR:
1182 skge->flow_status = FLOW_STAT_REM_SEND;
1183 break;
1184 case PHY_B_AS_PRT:
1185 skge->flow_status = FLOW_STAT_LOC_SEND;
1186 break;
1187 default:
1188 skge->flow_status = FLOW_STAT_NONE;
1189 }
1190 skge->speed = SPEED_1000;
1191 }
1192
1193 if (!netif_carrier_ok(dev))
1194 genesis_link_up(skge);
1195 }
1196
1197 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1198 * Phy on for 100 or 10Mbit operation
1199 */
1200 static void bcom_phy_init(struct skge_port *skge)
1201 {
1202 struct skge_hw *hw = skge->hw;
1203 int port = skge->port;
1204 int i;
1205 u16 id1, r, ext, ctl;
1206
1207 /* magic workaround patterns for Broadcom */
1208 static const struct {
1209 u16 reg;
1210 u16 val;
1211 } A1hack[] = {
1212 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1213 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1214 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1215 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1216 }, C0hack[] = {
1217 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1218 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1219 };
1220
1221 /* read Id from external PHY (all have the same address) */
1222 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1223
1224 /* Optimize MDIO transfer by suppressing preamble. */
1225 r = xm_read16(hw, port, XM_MMU_CMD);
1226 r |= XM_MMU_NO_PRE;
1227 xm_write16(hw, port, XM_MMU_CMD,r);
1228
1229 switch (id1) {
1230 case PHY_BCOM_ID1_C0:
1231 /*
1232 * Workaround BCOM Errata for the C0 type.
1233 * Write magic patterns to reserved registers.
1234 */
1235 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1236 xm_phy_write(hw, port,
1237 C0hack[i].reg, C0hack[i].val);
1238
1239 break;
1240 case PHY_BCOM_ID1_A1:
1241 /*
1242 * Workaround BCOM Errata for the A1 type.
1243 * Write magic patterns to reserved registers.
1244 */
1245 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1246 xm_phy_write(hw, port,
1247 A1hack[i].reg, A1hack[i].val);
1248 break;
1249 }
1250
1251 /*
1252 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1253 * Disable Power Management after reset.
1254 */
1255 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1256 r |= PHY_B_AC_DIS_PM;
1257 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1258
1259 /* Dummy read */
1260 xm_read16(hw, port, XM_ISRC);
1261
1262 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1263 ctl = PHY_CT_SP1000; /* always 1000mbit */
1264
1265 if (skge->autoneg == AUTONEG_ENABLE) {
1266 /*
1267 * Workaround BCOM Errata #1 for the C5 type.
1268 * 1000Base-T Link Acquisition Failure in Slave Mode
1269 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1270 */
1271 u16 adv = PHY_B_1000C_RD;
1272 if (skge->advertising & ADVERTISED_1000baseT_Half)
1273 adv |= PHY_B_1000C_AHD;
1274 if (skge->advertising & ADVERTISED_1000baseT_Full)
1275 adv |= PHY_B_1000C_AFD;
1276 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1277
1278 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1279 } else {
1280 if (skge->duplex == DUPLEX_FULL)
1281 ctl |= PHY_CT_DUP_MD;
1282 /* Force to slave */
1283 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1284 }
1285
1286 /* Set autonegotiation pause parameters */
1287 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1288 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1289
1290 /* Handle Jumbo frames */
1291 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1292 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1293 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1294
1295 ext |= PHY_B_PEC_HIGH_LA;
1296
1297 }
1298
1299 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1300 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1301
1302 /* Use link status change interrupt */
1303 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1304 }
1305
1306 static void xm_phy_init(struct skge_port *skge)
1307 {
1308 struct skge_hw *hw = skge->hw;
1309 int port = skge->port;
1310 u16 ctrl = 0;
1311
1312 if (skge->autoneg == AUTONEG_ENABLE) {
1313 if (skge->advertising & ADVERTISED_1000baseT_Half)
1314 ctrl |= PHY_X_AN_HD;
1315 if (skge->advertising & ADVERTISED_1000baseT_Full)
1316 ctrl |= PHY_X_AN_FD;
1317
1318 ctrl |= fiber_pause_map[skge->flow_control];
1319
1320 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1321
1322 /* Restart Auto-negotiation */
1323 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1324 } else {
1325 /* Set DuplexMode in Config register */
1326 if (skge->duplex == DUPLEX_FULL)
1327 ctrl |= PHY_CT_DUP_MD;
1328 /*
1329 * Do NOT enable Auto-negotiation here. This would hold
1330 * the link down because no IDLEs are transmitted
1331 */
1332 }
1333
1334 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1335
1336 /* Poll PHY for status changes */
1337 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1338 }
1339
1340 static void xm_check_link(struct net_device *dev)
1341 {
1342 struct skge_port *skge = netdev_priv(dev);
1343 struct skge_hw *hw = skge->hw;
1344 int port = skge->port;
1345 u16 status;
1346
1347 /* read twice because of latch */
1348 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1349 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1350
1351 if ((status & PHY_ST_LSYNC) == 0) {
1352 xm_link_down(hw, port);
1353 return;
1354 }
1355
1356 if (skge->autoneg == AUTONEG_ENABLE) {
1357 u16 lpa, res;
1358
1359 if (!(status & PHY_ST_AN_OVER))
1360 return;
1361
1362 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1363 if (lpa & PHY_B_AN_RF) {
1364 printk(KERN_NOTICE PFX "%s: remote fault\n",
1365 dev->name);
1366 return;
1367 }
1368
1369 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1370
1371 /* Check Duplex mismatch */
1372 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1373 case PHY_X_RS_FD:
1374 skge->duplex = DUPLEX_FULL;
1375 break;
1376 case PHY_X_RS_HD:
1377 skge->duplex = DUPLEX_HALF;
1378 break;
1379 default:
1380 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1381 dev->name);
1382 return;
1383 }
1384
1385 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1386 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1387 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1388 (lpa & PHY_X_P_SYM_MD))
1389 skge->flow_status = FLOW_STAT_SYMMETRIC;
1390 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1391 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1392 /* Enable PAUSE receive, disable PAUSE transmit */
1393 skge->flow_status = FLOW_STAT_REM_SEND;
1394 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1395 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1396 /* Disable PAUSE receive, enable PAUSE transmit */
1397 skge->flow_status = FLOW_STAT_LOC_SEND;
1398 else
1399 skge->flow_status = FLOW_STAT_NONE;
1400
1401 skge->speed = SPEED_1000;
1402 }
1403
1404 if (!netif_carrier_ok(dev))
1405 genesis_link_up(skge);
1406 }
1407
1408 /* Poll to check for link coming up.
1409 * Since internal PHY is wired to a level triggered pin, can't
1410 * get an interrupt when carrier is detected.
1411 */
1412 static void xm_link_timer(unsigned long arg)
1413 {
1414 struct skge_port *skge = (struct skge_port *) arg;
1415 struct net_device *dev = skge->netdev;
1416 struct skge_hw *hw = skge->hw;
1417 int port = skge->port;
1418
1419 if (!netif_running(dev))
1420 return;
1421
1422 if (netif_carrier_ok(dev)) {
1423 xm_read16(hw, port, XM_ISRC);
1424 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1425 goto nochange;
1426 } else {
1427 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1428 goto nochange;
1429 xm_read16(hw, port, XM_ISRC);
1430 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1431 goto nochange;
1432 }
1433
1434 spin_lock(&hw->phy_lock);
1435 xm_check_link(dev);
1436 spin_unlock(&hw->phy_lock);
1437
1438 nochange:
1439 if (netif_running(dev))
1440 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1441 }
1442
1443 static void genesis_mac_init(struct skge_hw *hw, int port)
1444 {
1445 struct net_device *dev = hw->dev[port];
1446 struct skge_port *skge = netdev_priv(dev);
1447 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1448 int i;
1449 u32 r;
1450 const u8 zero[6] = { 0 };
1451
1452 for (i = 0; i < 10; i++) {
1453 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1454 MFF_SET_MAC_RST);
1455 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1456 goto reset_ok;
1457 udelay(1);
1458 }
1459
1460 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1461
1462 reset_ok:
1463 /* Unreset the XMAC. */
1464 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1465
1466 /*
1467 * Perform additional initialization for external PHYs,
1468 * namely for the 1000baseTX cards that use the XMAC's
1469 * GMII mode.
1470 */
1471 if (hw->phy_type != SK_PHY_XMAC) {
1472 /* Take external Phy out of reset */
1473 r = skge_read32(hw, B2_GP_IO);
1474 if (port == 0)
1475 r |= GP_DIR_0|GP_IO_0;
1476 else
1477 r |= GP_DIR_2|GP_IO_2;
1478
1479 skge_write32(hw, B2_GP_IO, r);
1480
1481 /* Enable GMII interface */
1482 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1483 }
1484
1485
1486 switch(hw->phy_type) {
1487 case SK_PHY_XMAC:
1488 xm_phy_init(skge);
1489 break;
1490 case SK_PHY_BCOM:
1491 bcom_phy_init(skge);
1492 bcom_check_link(hw, port);
1493 }
1494
1495 /* Set Station Address */
1496 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1497
1498 /* We don't use match addresses so clear */
1499 for (i = 1; i < 16; i++)
1500 xm_outaddr(hw, port, XM_EXM(i), zero);
1501
1502 /* Clear MIB counters */
1503 xm_write16(hw, port, XM_STAT_CMD,
1504 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1505 /* Clear two times according to Errata #3 */
1506 xm_write16(hw, port, XM_STAT_CMD,
1507 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1508
1509 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1510 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1511
1512 /* We don't need the FCS appended to the packet. */
1513 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1514 if (jumbo)
1515 r |= XM_RX_BIG_PK_OK;
1516
1517 if (skge->duplex == DUPLEX_HALF) {
1518 /*
1519 * If in manual half duplex mode the other side might be in
1520 * full duplex mode, so ignore if a carrier extension is not seen
1521 * on frames received
1522 */
1523 r |= XM_RX_DIS_CEXT;
1524 }
1525 xm_write16(hw, port, XM_RX_CMD, r);
1526
1527
1528 /* We want short frames padded to 60 bytes. */
1529 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1530
1531 /*
1532 * Bump up the transmit threshold. This helps hold off transmit
1533 * underruns when we're blasting traffic from both ports at once.
1534 */
1535 xm_write16(hw, port, XM_TX_THR, 512);
1536
1537 /*
1538 * Enable the reception of all error frames. This is is
1539 * a necessary evil due to the design of the XMAC. The
1540 * XMAC's receive FIFO is only 8K in size, however jumbo
1541 * frames can be up to 9000 bytes in length. When bad
1542 * frame filtering is enabled, the XMAC's RX FIFO operates
1543 * in 'store and forward' mode. For this to work, the
1544 * entire frame has to fit into the FIFO, but that means
1545 * that jumbo frames larger than 8192 bytes will be
1546 * truncated. Disabling all bad frame filtering causes
1547 * the RX FIFO to operate in streaming mode, in which
1548 * case the XMAC will start transferring frames out of the
1549 * RX FIFO as soon as the FIFO threshold is reached.
1550 */
1551 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1552
1553
1554 /*
1555 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1556 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1557 * and 'Octets Rx OK Hi Cnt Ov'.
1558 */
1559 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1560
1561 /*
1562 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1563 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1564 * and 'Octets Tx OK Hi Cnt Ov'.
1565 */
1566 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1567
1568 /* Configure MAC arbiter */
1569 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1570
1571 /* configure timeout values */
1572 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1573 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1574 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1575 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1576
1577 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1578 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1579 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1580 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1581
1582 /* Configure Rx MAC FIFO */
1583 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1584 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1585 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1586
1587 /* Configure Tx MAC FIFO */
1588 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1589 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1590 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1591
1592 if (jumbo) {
1593 /* Enable frame flushing if jumbo frames used */
1594 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1595 } else {
1596 /* enable timeout timers if normal frames */
1597 skge_write16(hw, B3_PA_CTRL,
1598 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1599 }
1600 }
1601
1602 static void genesis_stop(struct skge_port *skge)
1603 {
1604 struct skge_hw *hw = skge->hw;
1605 int port = skge->port;
1606 u32 reg;
1607
1608 genesis_reset(hw, port);
1609
1610 /* Clear Tx packet arbiter timeout IRQ */
1611 skge_write16(hw, B3_PA_CTRL,
1612 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1613
1614 /*
1615 * If the transfer sticks at the MAC the STOP command will not
1616 * terminate if we don't flush the XMAC's transmit FIFO !
1617 */
1618 xm_write32(hw, port, XM_MODE,
1619 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1620
1621
1622 /* Reset the MAC */
1623 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1624
1625 /* For external PHYs there must be special handling */
1626 if (hw->phy_type != SK_PHY_XMAC) {
1627 reg = skge_read32(hw, B2_GP_IO);
1628 if (port == 0) {
1629 reg |= GP_DIR_0;
1630 reg &= ~GP_IO_0;
1631 } else {
1632 reg |= GP_DIR_2;
1633 reg &= ~GP_IO_2;
1634 }
1635 skge_write32(hw, B2_GP_IO, reg);
1636 skge_read32(hw, B2_GP_IO);
1637 }
1638
1639 xm_write16(hw, port, XM_MMU_CMD,
1640 xm_read16(hw, port, XM_MMU_CMD)
1641 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1642
1643 xm_read16(hw, port, XM_MMU_CMD);
1644 }
1645
1646
1647 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1648 {
1649 struct skge_hw *hw = skge->hw;
1650 int port = skge->port;
1651 int i;
1652 unsigned long timeout = jiffies + HZ;
1653
1654 xm_write16(hw, port,
1655 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1656
1657 /* wait for update to complete */
1658 while (xm_read16(hw, port, XM_STAT_CMD)
1659 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1660 if (time_after(jiffies, timeout))
1661 break;
1662 udelay(10);
1663 }
1664
1665 /* special case for 64 bit octet counter */
1666 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1667 | xm_read32(hw, port, XM_TXO_OK_LO);
1668 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1669 | xm_read32(hw, port, XM_RXO_OK_LO);
1670
1671 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1672 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1673 }
1674
1675 static void genesis_mac_intr(struct skge_hw *hw, int port)
1676 {
1677 struct skge_port *skge = netdev_priv(hw->dev[port]);
1678 u16 status = xm_read16(hw, port, XM_ISRC);
1679
1680 if (netif_msg_intr(skge))
1681 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1682 skge->netdev->name, status);
1683
1684 if (hw->phy_type == SK_PHY_XMAC &&
1685 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1686 xm_link_down(hw, port);
1687
1688 if (status & XM_IS_TXF_UR) {
1689 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1690 ++skge->net_stats.tx_fifo_errors;
1691 }
1692 if (status & XM_IS_RXF_OV) {
1693 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1694 ++skge->net_stats.rx_fifo_errors;
1695 }
1696 }
1697
1698 static void genesis_link_up(struct skge_port *skge)
1699 {
1700 struct skge_hw *hw = skge->hw;
1701 int port = skge->port;
1702 u16 cmd, msk;
1703 u32 mode;
1704
1705 cmd = xm_read16(hw, port, XM_MMU_CMD);
1706
1707 /*
1708 * enabling pause frame reception is required for 1000BT
1709 * because the XMAC is not reset if the link is going down
1710 */
1711 if (skge->flow_status == FLOW_STAT_NONE ||
1712 skge->flow_status == FLOW_STAT_LOC_SEND)
1713 /* Disable Pause Frame Reception */
1714 cmd |= XM_MMU_IGN_PF;
1715 else
1716 /* Enable Pause Frame Reception */
1717 cmd &= ~XM_MMU_IGN_PF;
1718
1719 xm_write16(hw, port, XM_MMU_CMD, cmd);
1720
1721 mode = xm_read32(hw, port, XM_MODE);
1722 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1723 skge->flow_status == FLOW_STAT_LOC_SEND) {
1724 /*
1725 * Configure Pause Frame Generation
1726 * Use internal and external Pause Frame Generation.
1727 * Sending pause frames is edge triggered.
1728 * Send a Pause frame with the maximum pause time if
1729 * internal oder external FIFO full condition occurs.
1730 * Send a zero pause time frame to re-start transmission.
1731 */
1732 /* XM_PAUSE_DA = '010000C28001' (default) */
1733 /* XM_MAC_PTIME = 0xffff (maximum) */
1734 /* remember this value is defined in big endian (!) */
1735 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1736
1737 mode |= XM_PAUSE_MODE;
1738 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1739 } else {
1740 /*
1741 * disable pause frame generation is required for 1000BT
1742 * because the XMAC is not reset if the link is going down
1743 */
1744 /* Disable Pause Mode in Mode Register */
1745 mode &= ~XM_PAUSE_MODE;
1746
1747 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1748 }
1749
1750 xm_write32(hw, port, XM_MODE, mode);
1751 msk = XM_DEF_MSK;
1752 if (hw->phy_type != SK_PHY_XMAC)
1753 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1754
1755 xm_write16(hw, port, XM_IMSK, msk);
1756 xm_read16(hw, port, XM_ISRC);
1757
1758 /* get MMU Command Reg. */
1759 cmd = xm_read16(hw, port, XM_MMU_CMD);
1760 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1761 cmd |= XM_MMU_GMII_FD;
1762
1763 /*
1764 * Workaround BCOM Errata (#10523) for all BCom Phys
1765 * Enable Power Management after link up
1766 */
1767 if (hw->phy_type == SK_PHY_BCOM) {
1768 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1769 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1770 & ~PHY_B_AC_DIS_PM);
1771 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1772 }
1773
1774 /* enable Rx/Tx */
1775 xm_write16(hw, port, XM_MMU_CMD,
1776 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1777 skge_link_up(skge);
1778 }
1779
1780
1781 static inline void bcom_phy_intr(struct skge_port *skge)
1782 {
1783 struct skge_hw *hw = skge->hw;
1784 int port = skge->port;
1785 u16 isrc;
1786
1787 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1788 if (netif_msg_intr(skge))
1789 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1790 skge->netdev->name, isrc);
1791
1792 if (isrc & PHY_B_IS_PSE)
1793 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1794 hw->dev[port]->name);
1795
1796 /* Workaround BCom Errata:
1797 * enable and disable loopback mode if "NO HCD" occurs.
1798 */
1799 if (isrc & PHY_B_IS_NO_HDCL) {
1800 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1801 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1802 ctrl | PHY_CT_LOOP);
1803 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1804 ctrl & ~PHY_CT_LOOP);
1805 }
1806
1807 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1808 bcom_check_link(hw, port);
1809
1810 }
1811
1812 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1813 {
1814 int i;
1815
1816 gma_write16(hw, port, GM_SMI_DATA, val);
1817 gma_write16(hw, port, GM_SMI_CTRL,
1818 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1819 for (i = 0; i < PHY_RETRIES; i++) {
1820 udelay(1);
1821
1822 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1823 return 0;
1824 }
1825
1826 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1827 hw->dev[port]->name);
1828 return -EIO;
1829 }
1830
1831 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1832 {
1833 int i;
1834
1835 gma_write16(hw, port, GM_SMI_CTRL,
1836 GM_SMI_CT_PHY_AD(hw->phy_addr)
1837 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1838
1839 for (i = 0; i < PHY_RETRIES; i++) {
1840 udelay(1);
1841 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1842 goto ready;
1843 }
1844
1845 return -ETIMEDOUT;
1846 ready:
1847 *val = gma_read16(hw, port, GM_SMI_DATA);
1848 return 0;
1849 }
1850
1851 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1852 {
1853 u16 v = 0;
1854 if (__gm_phy_read(hw, port, reg, &v))
1855 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1856 hw->dev[port]->name);
1857 return v;
1858 }
1859
1860 /* Marvell Phy Initialization */
1861 static void yukon_init(struct skge_hw *hw, int port)
1862 {
1863 struct skge_port *skge = netdev_priv(hw->dev[port]);
1864 u16 ctrl, ct1000, adv;
1865
1866 if (skge->autoneg == AUTONEG_ENABLE) {
1867 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1868
1869 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1870 PHY_M_EC_MAC_S_MSK);
1871 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1872
1873 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1874
1875 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1876 }
1877
1878 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1879 if (skge->autoneg == AUTONEG_DISABLE)
1880 ctrl &= ~PHY_CT_ANE;
1881
1882 ctrl |= PHY_CT_RESET;
1883 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1884
1885 ctrl = 0;
1886 ct1000 = 0;
1887 adv = PHY_AN_CSMA;
1888
1889 if (skge->autoneg == AUTONEG_ENABLE) {
1890 if (hw->copper) {
1891 if (skge->advertising & ADVERTISED_1000baseT_Full)
1892 ct1000 |= PHY_M_1000C_AFD;
1893 if (skge->advertising & ADVERTISED_1000baseT_Half)
1894 ct1000 |= PHY_M_1000C_AHD;
1895 if (skge->advertising & ADVERTISED_100baseT_Full)
1896 adv |= PHY_M_AN_100_FD;
1897 if (skge->advertising & ADVERTISED_100baseT_Half)
1898 adv |= PHY_M_AN_100_HD;
1899 if (skge->advertising & ADVERTISED_10baseT_Full)
1900 adv |= PHY_M_AN_10_FD;
1901 if (skge->advertising & ADVERTISED_10baseT_Half)
1902 adv |= PHY_M_AN_10_HD;
1903
1904 /* Set Flow-control capabilities */
1905 adv |= phy_pause_map[skge->flow_control];
1906 } else {
1907 if (skge->advertising & ADVERTISED_1000baseT_Full)
1908 adv |= PHY_M_AN_1000X_AFD;
1909 if (skge->advertising & ADVERTISED_1000baseT_Half)
1910 adv |= PHY_M_AN_1000X_AHD;
1911
1912 adv |= fiber_pause_map[skge->flow_control];
1913 }
1914
1915 /* Restart Auto-negotiation */
1916 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1917 } else {
1918 /* forced speed/duplex settings */
1919 ct1000 = PHY_M_1000C_MSE;
1920
1921 if (skge->duplex == DUPLEX_FULL)
1922 ctrl |= PHY_CT_DUP_MD;
1923
1924 switch (skge->speed) {
1925 case SPEED_1000:
1926 ctrl |= PHY_CT_SP1000;
1927 break;
1928 case SPEED_100:
1929 ctrl |= PHY_CT_SP100;
1930 break;
1931 }
1932
1933 ctrl |= PHY_CT_RESET;
1934 }
1935
1936 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1937
1938 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1939 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1940
1941 /* Enable phy interrupt on autonegotiation complete (or link up) */
1942 if (skge->autoneg == AUTONEG_ENABLE)
1943 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1944 else
1945 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1946 }
1947
1948 static void yukon_reset(struct skge_hw *hw, int port)
1949 {
1950 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1951 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1952 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1953 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1954 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1955
1956 gma_write16(hw, port, GM_RX_CTRL,
1957 gma_read16(hw, port, GM_RX_CTRL)
1958 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1959 }
1960
1961 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1962 static int is_yukon_lite_a0(struct skge_hw *hw)
1963 {
1964 u32 reg;
1965 int ret;
1966
1967 if (hw->chip_id != CHIP_ID_YUKON)
1968 return 0;
1969
1970 reg = skge_read32(hw, B2_FAR);
1971 skge_write8(hw, B2_FAR + 3, 0xff);
1972 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1973 skge_write32(hw, B2_FAR, reg);
1974 return ret;
1975 }
1976
1977 static void yukon_mac_init(struct skge_hw *hw, int port)
1978 {
1979 struct skge_port *skge = netdev_priv(hw->dev[port]);
1980 int i;
1981 u32 reg;
1982 const u8 *addr = hw->dev[port]->dev_addr;
1983
1984 /* WA code for COMA mode -- set PHY reset */
1985 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1986 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1987 reg = skge_read32(hw, B2_GP_IO);
1988 reg |= GP_DIR_9 | GP_IO_9;
1989 skge_write32(hw, B2_GP_IO, reg);
1990 }
1991
1992 /* hard reset */
1993 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1994 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1995
1996 /* WA code for COMA mode -- clear PHY reset */
1997 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1998 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1999 reg = skge_read32(hw, B2_GP_IO);
2000 reg |= GP_DIR_9;
2001 reg &= ~GP_IO_9;
2002 skge_write32(hw, B2_GP_IO, reg);
2003 }
2004
2005 /* Set hardware config mode */
2006 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2007 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2008 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2009
2010 /* Clear GMC reset */
2011 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2012 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2013 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2014
2015 if (skge->autoneg == AUTONEG_DISABLE) {
2016 reg = GM_GPCR_AU_ALL_DIS;
2017 gma_write16(hw, port, GM_GP_CTRL,
2018 gma_read16(hw, port, GM_GP_CTRL) | reg);
2019
2020 switch (skge->speed) {
2021 case SPEED_1000:
2022 reg &= ~GM_GPCR_SPEED_100;
2023 reg |= GM_GPCR_SPEED_1000;
2024 break;
2025 case SPEED_100:
2026 reg &= ~GM_GPCR_SPEED_1000;
2027 reg |= GM_GPCR_SPEED_100;
2028 break;
2029 case SPEED_10:
2030 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2031 break;
2032 }
2033
2034 if (skge->duplex == DUPLEX_FULL)
2035 reg |= GM_GPCR_DUP_FULL;
2036 } else
2037 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2038
2039 switch (skge->flow_control) {
2040 case FLOW_MODE_NONE:
2041 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2042 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2043 break;
2044 case FLOW_MODE_LOC_SEND:
2045 /* disable Rx flow-control */
2046 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2047 break;
2048 case FLOW_MODE_SYMMETRIC:
2049 case FLOW_MODE_SYM_OR_REM:
2050 /* enable Tx & Rx flow-control */
2051 break;
2052 }
2053
2054 gma_write16(hw, port, GM_GP_CTRL, reg);
2055 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2056
2057 yukon_init(hw, port);
2058
2059 /* MIB clear */
2060 reg = gma_read16(hw, port, GM_PHY_ADDR);
2061 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2062
2063 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2064 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2065 gma_write16(hw, port, GM_PHY_ADDR, reg);
2066
2067 /* transmit control */
2068 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2069
2070 /* receive control reg: unicast + multicast + no FCS */
2071 gma_write16(hw, port, GM_RX_CTRL,
2072 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2073
2074 /* transmit flow control */
2075 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2076
2077 /* transmit parameter */
2078 gma_write16(hw, port, GM_TX_PARAM,
2079 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2080 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2081 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2082
2083 /* serial mode register */
2084 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2085 if (hw->dev[port]->mtu > 1500)
2086 reg |= GM_SMOD_JUMBO_ENA;
2087
2088 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2089
2090 /* physical address: used for pause frames */
2091 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2092 /* virtual address for data */
2093 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2094
2095 /* enable interrupt mask for counter overflows */
2096 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2097 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2098 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2099
2100 /* Initialize Mac Fifo */
2101
2102 /* Configure Rx MAC FIFO */
2103 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2104 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2105
2106 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2107 if (is_yukon_lite_a0(hw))
2108 reg &= ~GMF_RX_F_FL_ON;
2109
2110 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2111 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2112 /*
2113 * because Pause Packet Truncation in GMAC is not working
2114 * we have to increase the Flush Threshold to 64 bytes
2115 * in order to flush pause packets in Rx FIFO on Yukon-1
2116 */
2117 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2118
2119 /* Configure Tx MAC FIFO */
2120 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2121 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2122 }
2123
2124 /* Go into power down mode */
2125 static void yukon_suspend(struct skge_hw *hw, int port)
2126 {
2127 u16 ctrl;
2128
2129 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2130 ctrl |= PHY_M_PC_POL_R_DIS;
2131 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2132
2133 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2134 ctrl |= PHY_CT_RESET;
2135 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2136
2137 /* switch IEEE compatible power down mode on */
2138 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2139 ctrl |= PHY_CT_PDOWN;
2140 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2141 }
2142
2143 static void yukon_stop(struct skge_port *skge)
2144 {
2145 struct skge_hw *hw = skge->hw;
2146 int port = skge->port;
2147
2148 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2149 yukon_reset(hw, port);
2150
2151 gma_write16(hw, port, GM_GP_CTRL,
2152 gma_read16(hw, port, GM_GP_CTRL)
2153 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2154 gma_read16(hw, port, GM_GP_CTRL);
2155
2156 yukon_suspend(hw, port);
2157
2158 /* set GPHY Control reset */
2159 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2160 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2161 }
2162
2163 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2164 {
2165 struct skge_hw *hw = skge->hw;
2166 int port = skge->port;
2167 int i;
2168
2169 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2170 | gma_read32(hw, port, GM_TXO_OK_LO);
2171 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2172 | gma_read32(hw, port, GM_RXO_OK_LO);
2173
2174 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2175 data[i] = gma_read32(hw, port,
2176 skge_stats[i].gma_offset);
2177 }
2178
2179 static void yukon_mac_intr(struct skge_hw *hw, int port)
2180 {
2181 struct net_device *dev = hw->dev[port];
2182 struct skge_port *skge = netdev_priv(dev);
2183 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2184
2185 if (netif_msg_intr(skge))
2186 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2187 dev->name, status);
2188
2189 if (status & GM_IS_RX_FF_OR) {
2190 ++skge->net_stats.rx_fifo_errors;
2191 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2192 }
2193
2194 if (status & GM_IS_TX_FF_UR) {
2195 ++skge->net_stats.tx_fifo_errors;
2196 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2197 }
2198
2199 }
2200
2201 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2202 {
2203 switch (aux & PHY_M_PS_SPEED_MSK) {
2204 case PHY_M_PS_SPEED_1000:
2205 return SPEED_1000;
2206 case PHY_M_PS_SPEED_100:
2207 return SPEED_100;
2208 default:
2209 return SPEED_10;
2210 }
2211 }
2212
2213 static void yukon_link_up(struct skge_port *skge)
2214 {
2215 struct skge_hw *hw = skge->hw;
2216 int port = skge->port;
2217 u16 reg;
2218
2219 /* Enable Transmit FIFO Underrun */
2220 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2221
2222 reg = gma_read16(hw, port, GM_GP_CTRL);
2223 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2224 reg |= GM_GPCR_DUP_FULL;
2225
2226 /* enable Rx/Tx */
2227 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2228 gma_write16(hw, port, GM_GP_CTRL, reg);
2229
2230 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2231 skge_link_up(skge);
2232 }
2233
2234 static void yukon_link_down(struct skge_port *skge)
2235 {
2236 struct skge_hw *hw = skge->hw;
2237 int port = skge->port;
2238 u16 ctrl;
2239
2240 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2241 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2242 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2243
2244 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2245 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2246 ctrl |= PHY_M_AN_ASP;
2247 /* restore Asymmetric Pause bit */
2248 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2249 }
2250
2251 skge_link_down(skge);
2252
2253 yukon_init(hw, port);
2254 }
2255
2256 static void yukon_phy_intr(struct skge_port *skge)
2257 {
2258 struct skge_hw *hw = skge->hw;
2259 int port = skge->port;
2260 const char *reason = NULL;
2261 u16 istatus, phystat;
2262
2263 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2264 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2265
2266 if (netif_msg_intr(skge))
2267 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2268 skge->netdev->name, istatus, phystat);
2269
2270 if (istatus & PHY_M_IS_AN_COMPL) {
2271 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2272 & PHY_M_AN_RF) {
2273 reason = "remote fault";
2274 goto failed;
2275 }
2276
2277 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2278 reason = "master/slave fault";
2279 goto failed;
2280 }
2281
2282 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2283 reason = "speed/duplex";
2284 goto failed;
2285 }
2286
2287 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2288 ? DUPLEX_FULL : DUPLEX_HALF;
2289 skge->speed = yukon_speed(hw, phystat);
2290
2291 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2292 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2293 case PHY_M_PS_PAUSE_MSK:
2294 skge->flow_status = FLOW_STAT_SYMMETRIC;
2295 break;
2296 case PHY_M_PS_RX_P_EN:
2297 skge->flow_status = FLOW_STAT_REM_SEND;
2298 break;
2299 case PHY_M_PS_TX_P_EN:
2300 skge->flow_status = FLOW_STAT_LOC_SEND;
2301 break;
2302 default:
2303 skge->flow_status = FLOW_STAT_NONE;
2304 }
2305
2306 if (skge->flow_status == FLOW_STAT_NONE ||
2307 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2308 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2309 else
2310 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2311 yukon_link_up(skge);
2312 return;
2313 }
2314
2315 if (istatus & PHY_M_IS_LSP_CHANGE)
2316 skge->speed = yukon_speed(hw, phystat);
2317
2318 if (istatus & PHY_M_IS_DUP_CHANGE)
2319 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2320 if (istatus & PHY_M_IS_LST_CHANGE) {
2321 if (phystat & PHY_M_PS_LINK_UP)
2322 yukon_link_up(skge);
2323 else
2324 yukon_link_down(skge);
2325 }
2326 return;
2327 failed:
2328 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2329 skge->netdev->name, reason);
2330
2331 /* XXX restart autonegotiation? */
2332 }
2333
2334 static void skge_phy_reset(struct skge_port *skge)
2335 {
2336 struct skge_hw *hw = skge->hw;
2337 int port = skge->port;
2338 struct net_device *dev = hw->dev[port];
2339
2340 netif_stop_queue(skge->netdev);
2341 netif_carrier_off(skge->netdev);
2342
2343 spin_lock_bh(&hw->phy_lock);
2344 if (hw->chip_id == CHIP_ID_GENESIS) {
2345 genesis_reset(hw, port);
2346 genesis_mac_init(hw, port);
2347 } else {
2348 yukon_reset(hw, port);
2349 yukon_init(hw, port);
2350 }
2351 spin_unlock_bh(&hw->phy_lock);
2352
2353 dev->set_multicast_list(dev);
2354 }
2355
2356 /* Basic MII support */
2357 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2358 {
2359 struct mii_ioctl_data *data = if_mii(ifr);
2360 struct skge_port *skge = netdev_priv(dev);
2361 struct skge_hw *hw = skge->hw;
2362 int err = -EOPNOTSUPP;
2363
2364 if (!netif_running(dev))
2365 return -ENODEV; /* Phy still in reset */
2366
2367 switch(cmd) {
2368 case SIOCGMIIPHY:
2369 data->phy_id = hw->phy_addr;
2370
2371 /* fallthru */
2372 case SIOCGMIIREG: {
2373 u16 val = 0;
2374 spin_lock_bh(&hw->phy_lock);
2375 if (hw->chip_id == CHIP_ID_GENESIS)
2376 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2377 else
2378 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2379 spin_unlock_bh(&hw->phy_lock);
2380 data->val_out = val;
2381 break;
2382 }
2383
2384 case SIOCSMIIREG:
2385 if (!capable(CAP_NET_ADMIN))
2386 return -EPERM;
2387
2388 spin_lock_bh(&hw->phy_lock);
2389 if (hw->chip_id == CHIP_ID_GENESIS)
2390 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2391 data->val_in);
2392 else
2393 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2394 data->val_in);
2395 spin_unlock_bh(&hw->phy_lock);
2396 break;
2397 }
2398 return err;
2399 }
2400
2401 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2402 {
2403 u32 end;
2404
2405 start /= 8;
2406 len /= 8;
2407 end = start + len - 1;
2408
2409 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2410 skge_write32(hw, RB_ADDR(q, RB_START), start);
2411 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2412 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2413 skge_write32(hw, RB_ADDR(q, RB_END), end);
2414
2415 if (q == Q_R1 || q == Q_R2) {
2416 /* Set thresholds on receive queue's */
2417 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2418 start + (2*len)/3);
2419 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2420 start + (len/3));
2421 } else {
2422 /* Enable store & forward on Tx queue's because
2423 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2424 */
2425 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2426 }
2427
2428 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2429 }
2430
2431 /* Setup Bus Memory Interface */
2432 static void skge_qset(struct skge_port *skge, u16 q,
2433 const struct skge_element *e)
2434 {
2435 struct skge_hw *hw = skge->hw;
2436 u32 watermark = 0x600;
2437 u64 base = skge->dma + (e->desc - skge->mem);
2438
2439 /* optimization to reduce window on 32bit/33mhz */
2440 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2441 watermark /= 2;
2442
2443 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2444 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2445 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2446 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2447 }
2448
2449 static int skge_up(struct net_device *dev)
2450 {
2451 struct skge_port *skge = netdev_priv(dev);
2452 struct skge_hw *hw = skge->hw;
2453 int port = skge->port;
2454 u32 chunk, ram_addr;
2455 size_t rx_size, tx_size;
2456 int err;
2457
2458 if (!is_valid_ether_addr(dev->dev_addr))
2459 return -EINVAL;
2460
2461 if (netif_msg_ifup(skge))
2462 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2463
2464 if (dev->mtu > RX_BUF_SIZE)
2465 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2466 else
2467 skge->rx_buf_size = RX_BUF_SIZE;
2468
2469
2470 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2471 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2472 skge->mem_size = tx_size + rx_size;
2473 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2474 if (!skge->mem)
2475 return -ENOMEM;
2476
2477 BUG_ON(skge->dma & 7);
2478
2479 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2480 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2481 err = -EINVAL;
2482 goto free_pci_mem;
2483 }
2484
2485 memset(skge->mem, 0, skge->mem_size);
2486
2487 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2488 if (err)
2489 goto free_pci_mem;
2490
2491 err = skge_rx_fill(dev);
2492 if (err)
2493 goto free_rx_ring;
2494
2495 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2496 skge->dma + rx_size);
2497 if (err)
2498 goto free_rx_ring;
2499
2500 /* Initialize MAC */
2501 spin_lock_bh(&hw->phy_lock);
2502 if (hw->chip_id == CHIP_ID_GENESIS)
2503 genesis_mac_init(hw, port);
2504 else
2505 yukon_mac_init(hw, port);
2506 spin_unlock_bh(&hw->phy_lock);
2507
2508 /* Configure RAMbuffers */
2509 chunk = hw->ram_size / ((hw->ports + 1)*2);
2510 ram_addr = hw->ram_offset + 2 * chunk * port;
2511
2512 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2513 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2514
2515 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2516 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2517 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2518
2519 /* Start receiver BMU */
2520 wmb();
2521 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2522 skge_led(skge, LED_MODE_ON);
2523
2524 spin_lock_irq(&hw->hw_lock);
2525 hw->intr_mask |= portmask[port];
2526 skge_write32(hw, B0_IMSK, hw->intr_mask);
2527 spin_unlock_irq(&hw->hw_lock);
2528
2529 netif_poll_enable(dev);
2530 return 0;
2531
2532 free_rx_ring:
2533 skge_rx_clean(skge);
2534 kfree(skge->rx_ring.start);
2535 free_pci_mem:
2536 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2537 skge->mem = NULL;
2538
2539 return err;
2540 }
2541
2542 static int skge_down(struct net_device *dev)
2543 {
2544 struct skge_port *skge = netdev_priv(dev);
2545 struct skge_hw *hw = skge->hw;
2546 int port = skge->port;
2547
2548 if (skge->mem == NULL)
2549 return 0;
2550
2551 if (netif_msg_ifdown(skge))
2552 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2553
2554 netif_stop_queue(dev);
2555
2556 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2557 del_timer_sync(&skge->link_timer);
2558
2559 netif_poll_disable(dev);
2560 netif_carrier_off(dev);
2561
2562 spin_lock_irq(&hw->hw_lock);
2563 hw->intr_mask &= ~portmask[port];
2564 skge_write32(hw, B0_IMSK, hw->intr_mask);
2565 spin_unlock_irq(&hw->hw_lock);
2566
2567 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2568 if (hw->chip_id == CHIP_ID_GENESIS)
2569 genesis_stop(skge);
2570 else
2571 yukon_stop(skge);
2572
2573 /* Stop transmitter */
2574 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2575 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2576 RB_RST_SET|RB_DIS_OP_MD);
2577
2578
2579 /* Disable Force Sync bit and Enable Alloc bit */
2580 skge_write8(hw, SK_REG(port, TXA_CTRL),
2581 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2582
2583 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2584 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2585 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2586
2587 /* Reset PCI FIFO */
2588 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2589 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2590
2591 /* Reset the RAM Buffer async Tx queue */
2592 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2593 /* stop receiver */
2594 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2595 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2596 RB_RST_SET|RB_DIS_OP_MD);
2597 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2598
2599 if (hw->chip_id == CHIP_ID_GENESIS) {
2600 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2601 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2602 } else {
2603 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2604 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2605 }
2606
2607 skge_led(skge, LED_MODE_OFF);
2608
2609 netif_tx_lock_bh(dev);
2610 skge_tx_clean(dev);
2611 netif_tx_unlock_bh(dev);
2612
2613 skge_rx_clean(skge);
2614
2615 kfree(skge->rx_ring.start);
2616 kfree(skge->tx_ring.start);
2617 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2618 skge->mem = NULL;
2619 return 0;
2620 }
2621
2622 static inline int skge_avail(const struct skge_ring *ring)
2623 {
2624 smp_mb();
2625 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2626 + (ring->to_clean - ring->to_use) - 1;
2627 }
2628
2629 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2630 {
2631 struct skge_port *skge = netdev_priv(dev);
2632 struct skge_hw *hw = skge->hw;
2633 struct skge_element *e;
2634 struct skge_tx_desc *td;
2635 int i;
2636 u32 control, len;
2637 u64 map;
2638
2639 if (skb_padto(skb, ETH_ZLEN))
2640 return NETDEV_TX_OK;
2641
2642 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2643 return NETDEV_TX_BUSY;
2644
2645 e = skge->tx_ring.to_use;
2646 td = e->desc;
2647 BUG_ON(td->control & BMU_OWN);
2648 e->skb = skb;
2649 len = skb_headlen(skb);
2650 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2651 pci_unmap_addr_set(e, mapaddr, map);
2652 pci_unmap_len_set(e, maplen, len);
2653
2654 td->dma_lo = map;
2655 td->dma_hi = map >> 32;
2656
2657 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2658 const int offset = skb_transport_offset(skb);
2659
2660 /* This seems backwards, but it is what the sk98lin
2661 * does. Looks like hardware is wrong?
2662 */
2663 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2664 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2665 control = BMU_TCP_CHECK;
2666 else
2667 control = BMU_UDP_CHECK;
2668
2669 td->csum_offs = 0;
2670 td->csum_start = offset;
2671 td->csum_write = offset + skb->csum_offset;
2672 } else
2673 control = BMU_CHECK;
2674
2675 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2676 control |= BMU_EOF| BMU_IRQ_EOF;
2677 else {
2678 struct skge_tx_desc *tf = td;
2679
2680 control |= BMU_STFWD;
2681 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2682 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2683
2684 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2685 frag->size, PCI_DMA_TODEVICE);
2686
2687 e = e->next;
2688 e->skb = skb;
2689 tf = e->desc;
2690 BUG_ON(tf->control & BMU_OWN);
2691
2692 tf->dma_lo = map;
2693 tf->dma_hi = (u64) map >> 32;
2694 pci_unmap_addr_set(e, mapaddr, map);
2695 pci_unmap_len_set(e, maplen, frag->size);
2696
2697 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2698 }
2699 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2700 }
2701 /* Make sure all the descriptors written */
2702 wmb();
2703 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2704 wmb();
2705
2706 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2707
2708 if (unlikely(netif_msg_tx_queued(skge)))
2709 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2710 dev->name, e - skge->tx_ring.start, skb->len);
2711
2712 skge->tx_ring.to_use = e->next;
2713 smp_wmb();
2714
2715 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2716 pr_debug("%s: transmit queue full\n", dev->name);
2717 netif_stop_queue(dev);
2718 }
2719
2720 dev->trans_start = jiffies;
2721
2722 return NETDEV_TX_OK;
2723 }
2724
2725
2726 /* Free resources associated with this reing element */
2727 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2728 u32 control)
2729 {
2730 struct pci_dev *pdev = skge->hw->pdev;
2731
2732 /* skb header vs. fragment */
2733 if (control & BMU_STF)
2734 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2735 pci_unmap_len(e, maplen),
2736 PCI_DMA_TODEVICE);
2737 else
2738 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2739 pci_unmap_len(e, maplen),
2740 PCI_DMA_TODEVICE);
2741
2742 if (control & BMU_EOF) {
2743 if (unlikely(netif_msg_tx_done(skge)))
2744 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2745 skge->netdev->name, e - skge->tx_ring.start);
2746
2747 dev_kfree_skb(e->skb);
2748 }
2749 }
2750
2751 /* Free all buffers in transmit ring */
2752 static void skge_tx_clean(struct net_device *dev)
2753 {
2754 struct skge_port *skge = netdev_priv(dev);
2755 struct skge_element *e;
2756
2757 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2758 struct skge_tx_desc *td = e->desc;
2759 skge_tx_free(skge, e, td->control);
2760 td->control = 0;
2761 }
2762
2763 skge->tx_ring.to_clean = e;
2764 netif_wake_queue(dev);
2765 }
2766
2767 static void skge_tx_timeout(struct net_device *dev)
2768 {
2769 struct skge_port *skge = netdev_priv(dev);
2770
2771 if (netif_msg_timer(skge))
2772 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2773
2774 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2775 skge_tx_clean(dev);
2776 }
2777
2778 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2779 {
2780 int err;
2781
2782 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2783 return -EINVAL;
2784
2785 if (!netif_running(dev)) {
2786 dev->mtu = new_mtu;
2787 return 0;
2788 }
2789
2790 skge_down(dev);
2791
2792 dev->mtu = new_mtu;
2793
2794 err = skge_up(dev);
2795 if (err)
2796 dev_close(dev);
2797
2798 return err;
2799 }
2800
2801 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2802
2803 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2804 {
2805 u32 crc, bit;
2806
2807 crc = ether_crc_le(ETH_ALEN, addr);
2808 bit = ~crc & 0x3f;
2809 filter[bit/8] |= 1 << (bit%8);
2810 }
2811
2812 static void genesis_set_multicast(struct net_device *dev)
2813 {
2814 struct skge_port *skge = netdev_priv(dev);
2815 struct skge_hw *hw = skge->hw;
2816 int port = skge->port;
2817 int i, count = dev->mc_count;
2818 struct dev_mc_list *list = dev->mc_list;
2819 u32 mode;
2820 u8 filter[8];
2821
2822 mode = xm_read32(hw, port, XM_MODE);
2823 mode |= XM_MD_ENA_HASH;
2824 if (dev->flags & IFF_PROMISC)
2825 mode |= XM_MD_ENA_PROM;
2826 else
2827 mode &= ~XM_MD_ENA_PROM;
2828
2829 if (dev->flags & IFF_ALLMULTI)
2830 memset(filter, 0xff, sizeof(filter));
2831 else {
2832 memset(filter, 0, sizeof(filter));
2833
2834 if (skge->flow_status == FLOW_STAT_REM_SEND
2835 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2836 genesis_add_filter(filter, pause_mc_addr);
2837
2838 for (i = 0; list && i < count; i++, list = list->next)
2839 genesis_add_filter(filter, list->dmi_addr);
2840 }
2841
2842 xm_write32(hw, port, XM_MODE, mode);
2843 xm_outhash(hw, port, XM_HSM, filter);
2844 }
2845
2846 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2847 {
2848 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2849 filter[bit/8] |= 1 << (bit%8);
2850 }
2851
2852 static void yukon_set_multicast(struct net_device *dev)
2853 {
2854 struct skge_port *skge = netdev_priv(dev);
2855 struct skge_hw *hw = skge->hw;
2856 int port = skge->port;
2857 struct dev_mc_list *list = dev->mc_list;
2858 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2859 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2860 u16 reg;
2861 u8 filter[8];
2862
2863 memset(filter, 0, sizeof(filter));
2864
2865 reg = gma_read16(hw, port, GM_RX_CTRL);
2866 reg |= GM_RXCR_UCF_ENA;
2867
2868 if (dev->flags & IFF_PROMISC) /* promiscuous */
2869 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2870 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2871 memset(filter, 0xff, sizeof(filter));
2872 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2873 reg &= ~GM_RXCR_MCF_ENA;
2874 else {
2875 int i;
2876 reg |= GM_RXCR_MCF_ENA;
2877
2878 if (rx_pause)
2879 yukon_add_filter(filter, pause_mc_addr);
2880
2881 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2882 yukon_add_filter(filter, list->dmi_addr);
2883 }
2884
2885
2886 gma_write16(hw, port, GM_MC_ADDR_H1,
2887 (u16)filter[0] | ((u16)filter[1] << 8));
2888 gma_write16(hw, port, GM_MC_ADDR_H2,
2889 (u16)filter[2] | ((u16)filter[3] << 8));
2890 gma_write16(hw, port, GM_MC_ADDR_H3,
2891 (u16)filter[4] | ((u16)filter[5] << 8));
2892 gma_write16(hw, port, GM_MC_ADDR_H4,
2893 (u16)filter[6] | ((u16)filter[7] << 8));
2894
2895 gma_write16(hw, port, GM_RX_CTRL, reg);
2896 }
2897
2898 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2899 {
2900 if (hw->chip_id == CHIP_ID_GENESIS)
2901 return status >> XMR_FS_LEN_SHIFT;
2902 else
2903 return status >> GMR_FS_LEN_SHIFT;
2904 }
2905
2906 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2907 {
2908 if (hw->chip_id == CHIP_ID_GENESIS)
2909 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2910 else
2911 return (status & GMR_FS_ANY_ERR) ||
2912 (status & GMR_FS_RX_OK) == 0;
2913 }
2914
2915
2916 /* Get receive buffer from descriptor.
2917 * Handles copy of small buffers and reallocation failures
2918 */
2919 static struct sk_buff *skge_rx_get(struct net_device *dev,
2920 struct skge_element *e,
2921 u32 control, u32 status, u16 csum)
2922 {
2923 struct skge_port *skge = netdev_priv(dev);
2924 struct sk_buff *skb;
2925 u16 len = control & BMU_BBC;
2926
2927 if (unlikely(netif_msg_rx_status(skge)))
2928 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2929 dev->name, e - skge->rx_ring.start,
2930 status, len);
2931
2932 if (len > skge->rx_buf_size)
2933 goto error;
2934
2935 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2936 goto error;
2937
2938 if (bad_phy_status(skge->hw, status))
2939 goto error;
2940
2941 if (phy_length(skge->hw, status) != len)
2942 goto error;
2943
2944 if (len < RX_COPY_THRESHOLD) {
2945 skb = netdev_alloc_skb(dev, len + 2);
2946 if (!skb)
2947 goto resubmit;
2948
2949 skb_reserve(skb, 2);
2950 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2951 pci_unmap_addr(e, mapaddr),
2952 len, PCI_DMA_FROMDEVICE);
2953 skb_copy_from_linear_data(e->skb, skb->data, len);
2954 pci_dma_sync_single_for_device(skge->hw->pdev,
2955 pci_unmap_addr(e, mapaddr),
2956 len, PCI_DMA_FROMDEVICE);
2957 skge_rx_reuse(e, skge->rx_buf_size);
2958 } else {
2959 struct sk_buff *nskb;
2960 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2961 if (!nskb)
2962 goto resubmit;
2963
2964 skb_reserve(nskb, NET_IP_ALIGN);
2965 pci_unmap_single(skge->hw->pdev,
2966 pci_unmap_addr(e, mapaddr),
2967 pci_unmap_len(e, maplen),
2968 PCI_DMA_FROMDEVICE);
2969 skb = e->skb;
2970 prefetch(skb->data);
2971 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2972 }
2973
2974 skb_put(skb, len);
2975 if (skge->rx_csum) {
2976 skb->csum = csum;
2977 skb->ip_summed = CHECKSUM_COMPLETE;
2978 }
2979
2980 skb->protocol = eth_type_trans(skb, dev);
2981
2982 return skb;
2983 error:
2984
2985 if (netif_msg_rx_err(skge))
2986 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2987 dev->name, e - skge->rx_ring.start,
2988 control, status);
2989
2990 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2991 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2992 skge->net_stats.rx_length_errors++;
2993 if (status & XMR_FS_FRA_ERR)
2994 skge->net_stats.rx_frame_errors++;
2995 if (status & XMR_FS_FCS_ERR)
2996 skge->net_stats.rx_crc_errors++;
2997 } else {
2998 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2999 skge->net_stats.rx_length_errors++;
3000 if (status & GMR_FS_FRAGMENT)
3001 skge->net_stats.rx_frame_errors++;
3002 if (status & GMR_FS_CRC_ERR)
3003 skge->net_stats.rx_crc_errors++;
3004 }
3005
3006 resubmit:
3007 skge_rx_reuse(e, skge->rx_buf_size);
3008 return NULL;
3009 }
3010
3011 /* Free all buffers in Tx ring which are no longer owned by device */
3012 static void skge_tx_done(struct net_device *dev)
3013 {
3014 struct skge_port *skge = netdev_priv(dev);
3015 struct skge_ring *ring = &skge->tx_ring;
3016 struct skge_element *e;
3017
3018 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3019
3020 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3021 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3022
3023 if (control & BMU_OWN)
3024 break;
3025
3026 skge_tx_free(skge, e, control);
3027 }
3028 skge->tx_ring.to_clean = e;
3029
3030 /* Can run lockless until we need to synchronize to restart queue. */
3031 smp_mb();
3032
3033 if (unlikely(netif_queue_stopped(dev) &&
3034 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3035 netif_tx_lock(dev);
3036 if (unlikely(netif_queue_stopped(dev) &&
3037 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3038 netif_wake_queue(dev);
3039
3040 }
3041 netif_tx_unlock(dev);
3042 }
3043 }
3044
3045 static int skge_poll(struct net_device *dev, int *budget)
3046 {
3047 struct skge_port *skge = netdev_priv(dev);
3048 struct skge_hw *hw = skge->hw;
3049 struct skge_ring *ring = &skge->rx_ring;
3050 struct skge_element *e;
3051 unsigned long flags;
3052 int to_do = min(dev->quota, *budget);
3053 int work_done = 0;
3054
3055 skge_tx_done(dev);
3056
3057 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3058
3059 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3060 struct skge_rx_desc *rd = e->desc;
3061 struct sk_buff *skb;
3062 u32 control;
3063
3064 rmb();
3065 control = rd->control;
3066 if (control & BMU_OWN)
3067 break;
3068
3069 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3070 if (likely(skb)) {
3071 dev->last_rx = jiffies;
3072 netif_receive_skb(skb);
3073
3074 ++work_done;
3075 }
3076 }
3077 ring->to_clean = e;
3078
3079 /* restart receiver */
3080 wmb();
3081 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3082
3083 *budget -= work_done;
3084 dev->quota -= work_done;
3085
3086 if (work_done >= to_do)
3087 return 1; /* not done */
3088
3089 spin_lock_irqsave(&hw->hw_lock, flags);
3090 __netif_rx_complete(dev);
3091 hw->intr_mask |= napimask[skge->port];
3092 skge_write32(hw, B0_IMSK, hw->intr_mask);
3093 skge_read32(hw, B0_IMSK);
3094 spin_unlock_irqrestore(&hw->hw_lock, flags);
3095
3096 return 0;
3097 }
3098
3099 /* Parity errors seem to happen when Genesis is connected to a switch
3100 * with no other ports present. Heartbeat error??
3101 */
3102 static void skge_mac_parity(struct skge_hw *hw, int port)
3103 {
3104 struct net_device *dev = hw->dev[port];
3105
3106 if (dev) {
3107 struct skge_port *skge = netdev_priv(dev);
3108 ++skge->net_stats.tx_heartbeat_errors;
3109 }
3110
3111 if (hw->chip_id == CHIP_ID_GENESIS)
3112 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3113 MFF_CLR_PERR);
3114 else
3115 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3116 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3117 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3118 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3119 }
3120
3121 static void skge_mac_intr(struct skge_hw *hw, int port)
3122 {
3123 if (hw->chip_id == CHIP_ID_GENESIS)
3124 genesis_mac_intr(hw, port);
3125 else
3126 yukon_mac_intr(hw, port);
3127 }
3128
3129 /* Handle device specific framing and timeout interrupts */
3130 static void skge_error_irq(struct skge_hw *hw)
3131 {
3132 struct pci_dev *pdev = hw->pdev;
3133 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3134
3135 if (hw->chip_id == CHIP_ID_GENESIS) {
3136 /* clear xmac errors */
3137 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3138 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3139 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3140 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3141 } else {
3142 /* Timestamp (unused) overflow */
3143 if (hwstatus & IS_IRQ_TIST_OV)
3144 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3145 }
3146
3147 if (hwstatus & IS_RAM_RD_PAR) {
3148 dev_err(&pdev->dev, "Ram read data parity error\n");
3149 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3150 }
3151
3152 if (hwstatus & IS_RAM_WR_PAR) {
3153 dev_err(&pdev->dev, "Ram write data parity error\n");
3154 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3155 }
3156
3157 if (hwstatus & IS_M1_PAR_ERR)
3158 skge_mac_parity(hw, 0);
3159
3160 if (hwstatus & IS_M2_PAR_ERR)
3161 skge_mac_parity(hw, 1);
3162
3163 if (hwstatus & IS_R1_PAR_ERR) {
3164 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3165 hw->dev[0]->name);
3166 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3167 }
3168
3169 if (hwstatus & IS_R2_PAR_ERR) {
3170 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3171 hw->dev[1]->name);
3172 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3173 }
3174
3175 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3176 u16 pci_status, pci_cmd;
3177
3178 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3179 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3180
3181 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3182 pci_cmd, pci_status);
3183
3184 /* Write the error bits back to clear them. */
3185 pci_status &= PCI_STATUS_ERROR_BITS;
3186 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3187 pci_write_config_word(pdev, PCI_COMMAND,
3188 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3189 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3190 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3191
3192 /* if error still set then just ignore it */
3193 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3194 if (hwstatus & IS_IRQ_STAT) {
3195 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3196 hw->intr_mask &= ~IS_HW_ERR;
3197 }
3198 }
3199 }
3200
3201 /*
3202 * Interrupt from PHY are handled in tasklet (softirq)
3203 * because accessing phy registers requires spin wait which might
3204 * cause excess interrupt latency.
3205 */
3206 static void skge_extirq(unsigned long arg)
3207 {
3208 struct skge_hw *hw = (struct skge_hw *) arg;
3209 int port;
3210
3211 for (port = 0; port < hw->ports; port++) {
3212 struct net_device *dev = hw->dev[port];
3213
3214 if (netif_running(dev)) {
3215 struct skge_port *skge = netdev_priv(dev);
3216
3217 spin_lock(&hw->phy_lock);
3218 if (hw->chip_id != CHIP_ID_GENESIS)
3219 yukon_phy_intr(skge);
3220 else if (hw->phy_type == SK_PHY_BCOM)
3221 bcom_phy_intr(skge);
3222 spin_unlock(&hw->phy_lock);
3223 }
3224 }
3225
3226 spin_lock_irq(&hw->hw_lock);
3227 hw->intr_mask |= IS_EXT_REG;
3228 skge_write32(hw, B0_IMSK, hw->intr_mask);
3229 skge_read32(hw, B0_IMSK);
3230 spin_unlock_irq(&hw->hw_lock);
3231 }
3232
3233 static irqreturn_t skge_intr(int irq, void *dev_id)
3234 {
3235 struct skge_hw *hw = dev_id;
3236 u32 status;
3237 int handled = 0;
3238
3239 spin_lock(&hw->hw_lock);
3240 /* Reading this register masks IRQ */
3241 status = skge_read32(hw, B0_SP_ISRC);
3242 if (status == 0 || status == ~0)
3243 goto out;
3244
3245 handled = 1;
3246 status &= hw->intr_mask;
3247 if (status & IS_EXT_REG) {
3248 hw->intr_mask &= ~IS_EXT_REG;
3249 tasklet_schedule(&hw->phy_task);
3250 }
3251
3252 if (status & (IS_XA1_F|IS_R1_F)) {
3253 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3254 netif_rx_schedule(hw->dev[0]);
3255 }
3256
3257 if (status & IS_PA_TO_TX1)
3258 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3259
3260 if (status & IS_PA_TO_RX1) {
3261 struct skge_port *skge = netdev_priv(hw->dev[0]);
3262
3263 ++skge->net_stats.rx_over_errors;
3264 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3265 }
3266
3267
3268 if (status & IS_MAC1)
3269 skge_mac_intr(hw, 0);
3270
3271 if (hw->dev[1]) {
3272 if (status & (IS_XA2_F|IS_R2_F)) {
3273 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3274 netif_rx_schedule(hw->dev[1]);
3275 }
3276
3277 if (status & IS_PA_TO_RX2) {
3278 struct skge_port *skge = netdev_priv(hw->dev[1]);
3279 ++skge->net_stats.rx_over_errors;
3280 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3281 }
3282
3283 if (status & IS_PA_TO_TX2)
3284 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3285
3286 if (status & IS_MAC2)
3287 skge_mac_intr(hw, 1);
3288 }
3289
3290 if (status & IS_HW_ERR)
3291 skge_error_irq(hw);
3292
3293 skge_write32(hw, B0_IMSK, hw->intr_mask);
3294 skge_read32(hw, B0_IMSK);
3295 out:
3296 spin_unlock(&hw->hw_lock);
3297
3298 return IRQ_RETVAL(handled);
3299 }
3300
3301 #ifdef CONFIG_NET_POLL_CONTROLLER
3302 static void skge_netpoll(struct net_device *dev)
3303 {
3304 struct skge_port *skge = netdev_priv(dev);
3305
3306 disable_irq(dev->irq);
3307 skge_intr(dev->irq, skge->hw);
3308 enable_irq(dev->irq);
3309 }
3310 #endif
3311
3312 static int skge_set_mac_address(struct net_device *dev, void *p)
3313 {
3314 struct skge_port *skge = netdev_priv(dev);
3315 struct skge_hw *hw = skge->hw;
3316 unsigned port = skge->port;
3317 const struct sockaddr *addr = p;
3318 u16 ctrl;
3319
3320 if (!is_valid_ether_addr(addr->sa_data))
3321 return -EADDRNOTAVAIL;
3322
3323 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3324
3325 if (!netif_running(dev)) {
3326 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3327 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3328 } else {
3329 /* disable Rx */
3330 spin_lock_bh(&hw->phy_lock);
3331 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3332 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3333
3334 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3335 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3336
3337 if (hw->chip_id == CHIP_ID_GENESIS)
3338 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3339 else {
3340 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3341 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3342 }
3343
3344 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3345 spin_unlock_bh(&hw->phy_lock);
3346 }
3347
3348 return 0;
3349 }
3350
3351 static const struct {
3352 u8 id;
3353 const char *name;
3354 } skge_chips[] = {
3355 { CHIP_ID_GENESIS, "Genesis" },
3356 { CHIP_ID_YUKON, "Yukon" },
3357 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3358 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3359 };
3360
3361 static const char *skge_board_name(const struct skge_hw *hw)
3362 {
3363 int i;
3364 static char buf[16];
3365
3366 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3367 if (skge_chips[i].id == hw->chip_id)
3368 return skge_chips[i].name;
3369
3370 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3371 return buf;
3372 }
3373
3374
3375 /*
3376 * Setup the board data structure, but don't bring up
3377 * the port(s)
3378 */
3379 static int skge_reset(struct skge_hw *hw)
3380 {
3381 u32 reg;
3382 u16 ctst, pci_status;
3383 u8 t8, mac_cfg, pmd_type;
3384 int i;
3385
3386 ctst = skge_read16(hw, B0_CTST);
3387
3388 /* do a SW reset */
3389 skge_write8(hw, B0_CTST, CS_RST_SET);
3390 skge_write8(hw, B0_CTST, CS_RST_CLR);
3391
3392 /* clear PCI errors, if any */
3393 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3394 skge_write8(hw, B2_TST_CTRL2, 0);
3395
3396 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3397 pci_write_config_word(hw->pdev, PCI_STATUS,
3398 pci_status | PCI_STATUS_ERROR_BITS);
3399 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3400 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3401
3402 /* restore CLK_RUN bits (for Yukon-Lite) */
3403 skge_write16(hw, B0_CTST,
3404 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3405
3406 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3407 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3408 pmd_type = skge_read8(hw, B2_PMD_TYP);
3409 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3410
3411 switch (hw->chip_id) {
3412 case CHIP_ID_GENESIS:
3413 switch (hw->phy_type) {
3414 case SK_PHY_XMAC:
3415 hw->phy_addr = PHY_ADDR_XMAC;
3416 break;
3417 case SK_PHY_BCOM:
3418 hw->phy_addr = PHY_ADDR_BCOM;
3419 break;
3420 default:
3421 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3422 hw->phy_type);
3423 return -EOPNOTSUPP;
3424 }
3425 break;
3426
3427 case CHIP_ID_YUKON:
3428 case CHIP_ID_YUKON_LITE:
3429 case CHIP_ID_YUKON_LP:
3430 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3431 hw->copper = 1;
3432
3433 hw->phy_addr = PHY_ADDR_MARV;
3434 break;
3435
3436 default:
3437 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3438 hw->chip_id);
3439 return -EOPNOTSUPP;
3440 }
3441
3442 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3443 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3444 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3445
3446 /* read the adapters RAM size */
3447 t8 = skge_read8(hw, B2_E_0);
3448 if (hw->chip_id == CHIP_ID_GENESIS) {
3449 if (t8 == 3) {
3450 /* special case: 4 x 64k x 36, offset = 0x80000 */
3451 hw->ram_size = 0x100000;
3452 hw->ram_offset = 0x80000;
3453 } else
3454 hw->ram_size = t8 * 512;
3455 }
3456 else if (t8 == 0)
3457 hw->ram_size = 0x20000;
3458 else
3459 hw->ram_size = t8 * 4096;
3460
3461 hw->intr_mask = IS_HW_ERR;
3462
3463 /* Use PHY IRQ for all but fiber based Genesis board */
3464 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3465 hw->intr_mask |= IS_EXT_REG;
3466
3467 if (hw->chip_id == CHIP_ID_GENESIS)
3468 genesis_init(hw);
3469 else {
3470 /* switch power to VCC (WA for VAUX problem) */
3471 skge_write8(hw, B0_POWER_CTRL,
3472 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3473
3474 /* avoid boards with stuck Hardware error bits */
3475 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3476 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3477 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3478 hw->intr_mask &= ~IS_HW_ERR;
3479 }
3480
3481 /* Clear PHY COMA */
3482 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3483 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3484 reg &= ~PCI_PHY_COMA;
3485 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3486 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3487
3488
3489 for (i = 0; i < hw->ports; i++) {
3490 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3491 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3492 }
3493 }
3494
3495 /* turn off hardware timer (unused) */
3496 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3497 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3498 skge_write8(hw, B0_LED, LED_STAT_ON);
3499
3500 /* enable the Tx Arbiters */
3501 for (i = 0; i < hw->ports; i++)
3502 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3503
3504 /* Initialize ram interface */
3505 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3506
3507 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3508 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3509 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3510 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3511 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3512 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3513 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3514 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3515 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3516 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3517 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3518 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3519
3520 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3521
3522 /* Set interrupt moderation for Transmit only
3523 * Receive interrupts avoided by NAPI
3524 */
3525 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3526 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3527 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3528
3529 skge_write32(hw, B0_IMSK, hw->intr_mask);
3530
3531 for (i = 0; i < hw->ports; i++) {
3532 if (hw->chip_id == CHIP_ID_GENESIS)
3533 genesis_reset(hw, i);
3534 else
3535 yukon_reset(hw, i);
3536 }
3537
3538 return 0;
3539 }
3540
3541 /* Initialize network device */
3542 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3543 int highmem)
3544 {
3545 struct skge_port *skge;
3546 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3547
3548 if (!dev) {
3549 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3550 return NULL;
3551 }
3552
3553 SET_MODULE_OWNER(dev);
3554 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3555 dev->open = skge_up;
3556 dev->stop = skge_down;
3557 dev->do_ioctl = skge_ioctl;
3558 dev->hard_start_xmit = skge_xmit_frame;
3559 dev->get_stats = skge_get_stats;
3560 if (hw->chip_id == CHIP_ID_GENESIS)
3561 dev->set_multicast_list = genesis_set_multicast;
3562 else
3563 dev->set_multicast_list = yukon_set_multicast;
3564
3565 dev->set_mac_address = skge_set_mac_address;
3566 dev->change_mtu = skge_change_mtu;
3567 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3568 dev->tx_timeout = skge_tx_timeout;
3569 dev->watchdog_timeo = TX_WATCHDOG;
3570 dev->poll = skge_poll;
3571 dev->weight = NAPI_WEIGHT;
3572 #ifdef CONFIG_NET_POLL_CONTROLLER
3573 dev->poll_controller = skge_netpoll;
3574 #endif
3575 dev->irq = hw->pdev->irq;
3576
3577 if (highmem)
3578 dev->features |= NETIF_F_HIGHDMA;
3579
3580 skge = netdev_priv(dev);
3581 skge->netdev = dev;
3582 skge->hw = hw;
3583 skge->msg_enable = netif_msg_init(debug, default_msg);
3584
3585 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3586 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3587
3588 /* Auto speed and flow control */
3589 skge->autoneg = AUTONEG_ENABLE;
3590 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3591 skge->duplex = -1;
3592 skge->speed = -1;
3593 skge->advertising = skge_supported_modes(hw);
3594 skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
3595
3596 hw->dev[port] = dev;
3597
3598 skge->port = port;
3599
3600 /* Only used for Genesis XMAC */
3601 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3602
3603 if (hw->chip_id != CHIP_ID_GENESIS) {
3604 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3605 skge->rx_csum = 1;
3606 }
3607
3608 /* read the mac address */
3609 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3610 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3611
3612 /* device is off until link detection */
3613 netif_carrier_off(dev);
3614 netif_stop_queue(dev);
3615
3616 return dev;
3617 }
3618
3619 static void __devinit skge_show_addr(struct net_device *dev)
3620 {
3621 const struct skge_port *skge = netdev_priv(dev);
3622
3623 if (netif_msg_probe(skge))
3624 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3625 dev->name,
3626 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3627 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3628 }
3629
3630 static int __devinit skge_probe(struct pci_dev *pdev,
3631 const struct pci_device_id *ent)
3632 {
3633 struct net_device *dev, *dev1;
3634 struct skge_hw *hw;
3635 int err, using_dac = 0;
3636
3637 err = pci_enable_device(pdev);
3638 if (err) {
3639 dev_err(&pdev->dev, "cannot enable PCI device\n");
3640 goto err_out;
3641 }
3642
3643 err = pci_request_regions(pdev, DRV_NAME);
3644 if (err) {
3645 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3646 goto err_out_disable_pdev;
3647 }
3648
3649 pci_set_master(pdev);
3650
3651 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3652 using_dac = 1;
3653 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3654 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3655 using_dac = 0;
3656 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3657 }
3658
3659 if (err) {
3660 dev_err(&pdev->dev, "no usable DMA configuration\n");
3661 goto err_out_free_regions;
3662 }
3663
3664 #ifdef __BIG_ENDIAN
3665 /* byte swap descriptors in hardware */
3666 {
3667 u32 reg;
3668
3669 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3670 reg |= PCI_REV_DESC;
3671 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3672 }
3673 #endif
3674
3675 err = -ENOMEM;
3676 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3677 if (!hw) {
3678 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3679 goto err_out_free_regions;
3680 }
3681
3682 hw->pdev = pdev;
3683 spin_lock_init(&hw->hw_lock);
3684 spin_lock_init(&hw->phy_lock);
3685 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3686
3687 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3688 if (!hw->regs) {
3689 dev_err(&pdev->dev, "cannot map device registers\n");
3690 goto err_out_free_hw;
3691 }
3692
3693 err = skge_reset(hw);
3694 if (err)
3695 goto err_out_iounmap;
3696
3697 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3698 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3699 skge_board_name(hw), hw->chip_rev);
3700
3701 dev = skge_devinit(hw, 0, using_dac);
3702 if (!dev)
3703 goto err_out_led_off;
3704
3705 /* Some motherboards are broken and has zero in ROM. */
3706 if (!is_valid_ether_addr(dev->dev_addr))
3707 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3708
3709 err = register_netdev(dev);
3710 if (err) {
3711 dev_err(&pdev->dev, "cannot register net device\n");
3712 goto err_out_free_netdev;
3713 }
3714
3715 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3716 if (err) {
3717 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3718 dev->name, pdev->irq);
3719 goto err_out_unregister;
3720 }
3721 skge_show_addr(dev);
3722
3723 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3724 if (register_netdev(dev1) == 0)
3725 skge_show_addr(dev1);
3726 else {
3727 /* Failure to register second port need not be fatal */
3728 dev_warn(&pdev->dev, "register of second port failed\n");
3729 hw->dev[1] = NULL;
3730 free_netdev(dev1);
3731 }
3732 }
3733 pci_set_drvdata(pdev, hw);
3734
3735 return 0;
3736
3737 err_out_unregister:
3738 unregister_netdev(dev);
3739 err_out_free_netdev:
3740 free_netdev(dev);
3741 err_out_led_off:
3742 skge_write16(hw, B0_LED, LED_STAT_OFF);
3743 err_out_iounmap:
3744 iounmap(hw->regs);
3745 err_out_free_hw:
3746 kfree(hw);
3747 err_out_free_regions:
3748 pci_release_regions(pdev);
3749 err_out_disable_pdev:
3750 pci_disable_device(pdev);
3751 pci_set_drvdata(pdev, NULL);
3752 err_out:
3753 return err;
3754 }
3755
3756 static void __devexit skge_remove(struct pci_dev *pdev)
3757 {
3758 struct skge_hw *hw = pci_get_drvdata(pdev);
3759 struct net_device *dev0, *dev1;
3760
3761 if (!hw)
3762 return;
3763
3764 flush_scheduled_work();
3765
3766 if ((dev1 = hw->dev[1]))
3767 unregister_netdev(dev1);
3768 dev0 = hw->dev[0];
3769 unregister_netdev(dev0);
3770
3771 tasklet_disable(&hw->phy_task);
3772
3773 spin_lock_irq(&hw->hw_lock);
3774 hw->intr_mask = 0;
3775 skge_write32(hw, B0_IMSK, 0);
3776 skge_read32(hw, B0_IMSK);
3777 spin_unlock_irq(&hw->hw_lock);
3778
3779 skge_write16(hw, B0_LED, LED_STAT_OFF);
3780 skge_write8(hw, B0_CTST, CS_RST_SET);
3781
3782 free_irq(pdev->irq, hw);
3783 pci_release_regions(pdev);
3784 pci_disable_device(pdev);
3785 if (dev1)
3786 free_netdev(dev1);
3787 free_netdev(dev0);
3788
3789 iounmap(hw->regs);
3790 kfree(hw);
3791 pci_set_drvdata(pdev, NULL);
3792 }
3793
3794 #ifdef CONFIG_PM
3795 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3796 {
3797 struct skge_hw *hw = pci_get_drvdata(pdev);
3798 int i, err, wol = 0;
3799
3800 err = pci_save_state(pdev);
3801 if (err)
3802 return err;
3803
3804 for (i = 0; i < hw->ports; i++) {
3805 struct net_device *dev = hw->dev[i];
3806 struct skge_port *skge = netdev_priv(dev);
3807
3808 if (netif_running(dev))
3809 skge_down(dev);
3810 if (skge->wol)
3811 skge_wol_init(skge);
3812
3813 wol |= skge->wol;
3814 }
3815
3816 skge_write32(hw, B0_IMSK, 0);
3817 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3818 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3819
3820 return 0;
3821 }
3822
3823 static int skge_resume(struct pci_dev *pdev)
3824 {
3825 struct skge_hw *hw = pci_get_drvdata(pdev);
3826 int i, err;
3827
3828 err = pci_set_power_state(pdev, PCI_D0);
3829 if (err)
3830 goto out;
3831
3832 err = pci_restore_state(pdev);
3833 if (err)
3834 goto out;
3835
3836 pci_enable_wake(pdev, PCI_D0, 0);
3837
3838 err = skge_reset(hw);
3839 if (err)
3840 goto out;
3841
3842 for (i = 0; i < hw->ports; i++) {
3843 struct net_device *dev = hw->dev[i];
3844
3845 if (netif_running(dev)) {
3846 err = skge_up(dev);
3847
3848 if (err) {
3849 printk(KERN_ERR PFX "%s: could not up: %d\n",
3850 dev->name, err);
3851 dev_close(dev);
3852 goto out;
3853 }
3854 }
3855 }
3856 out:
3857 return err;
3858 }
3859 #endif
3860
3861 static void skge_shutdown(struct pci_dev *pdev)
3862 {
3863 struct skge_hw *hw = pci_get_drvdata(pdev);
3864 int i, wol = 0;
3865
3866 for (i = 0; i < hw->ports; i++) {
3867 struct net_device *dev = hw->dev[i];
3868 struct skge_port *skge = netdev_priv(dev);
3869
3870 if (skge->wol)
3871 skge_wol_init(skge);
3872 wol |= skge->wol;
3873 }
3874
3875 pci_enable_wake(pdev, PCI_D3hot, wol);
3876 pci_enable_wake(pdev, PCI_D3cold, wol);
3877
3878 pci_disable_device(pdev);
3879 pci_set_power_state(pdev, PCI_D3hot);
3880
3881 }
3882
3883 static struct pci_driver skge_driver = {
3884 .name = DRV_NAME,
3885 .id_table = skge_id_table,
3886 .probe = skge_probe,
3887 .remove = __devexit_p(skge_remove),
3888 #ifdef CONFIG_PM
3889 .suspend = skge_suspend,
3890 .resume = skge_resume,
3891 #endif
3892 .shutdown = skge_shutdown,
3893 };
3894
3895 static int __init skge_init_module(void)
3896 {
3897 return pci_register_driver(&skge_driver);
3898 }
3899
3900 static void __exit skge_cleanup_module(void)
3901 {
3902 pci_unregister_driver(&skge_driver);
3903 }
3904
3905 module_init(skge_init_module);
3906 module_exit(skge_cleanup_module);
WRT350N Kernel Patches