drivers/char/rocket_int.h

   1 /*
   2  * rocket_int.h --- internal header file for rocket.c
   3  *
   4  * Written by Theodore Ts'o, Copyright 1997.
   5  * Copyright 1997 Comtrol Corporation.
   6  *
   7  */
   8
   9 /*
  10  * Definition of the types in rcktpt_type
  11  */
  12 #define ROCKET_TYPE_NORMAL      0
  13 #define ROCKET_TYPE_MODEM       1
  14 #define ROCKET_TYPE_MODEMII     2
  15 #define ROCKET_TYPE_MODEMIII    3
  16 #define ROCKET_TYPE_PC104       4
  17
  18 #include <linux/mutex.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/byteorder.h>
  22
  23 typedef unsigned char Byte_t;
  24 typedef unsigned int ByteIO_t;
  25
  26 typedef unsigned int Word_t;
  27 typedef unsigned int WordIO_t;
  28
  29 typedef unsigned long DWord_t;
  30 typedef unsigned int DWordIO_t;
  31
  32 /*
  33  * Note!  Normally the Linux I/O macros already take care of
  34  * byte-swapping the I/O instructions.  However, all accesses using
  35  * sOutDW aren't really 32-bit accesses, but should be handled in byte
  36  * order.  Hence the use of the cpu_to_le32() macro to byte-swap
  37  * things to no-op the byte swapping done by the big-endian outl()
  38  * instruction.
  39  */
  40
  41 #ifdef ROCKET_DEBUG_IO
  42 static inline void sOutB(unsigned short port, unsigned char value)
  43 {
  44 #ifdef ROCKET_DEBUG_IO
  45         printk("sOutB(%x, %x)...", port, value);
  46 #endif
  47         outb_p(value, port);
  48 }
  49
  50 static inline void sOutW(unsigned short port, unsigned short value)
  51 {
  52 #ifdef ROCKET_DEBUG_IO
  53         printk("sOutW(%x, %x)...", port, value);
  54 #endif
  55         outw_p(value, port);
  56 }
  57
  58 static inline void sOutDW(unsigned short port, unsigned long value)
  59 {
  60 #ifdef ROCKET_DEBUG_IO
  61         printk("sOutDW(%x, %lx)...", port, value);
  62 #endif
  63         outl_p(cpu_to_le32(value), port);
  64 }
  65
  66 static inline unsigned char sInB(unsigned short port)
  67 {
  68         return inb_p(port);
  69 }
  70
  71 static inline unsigned short sInW(unsigned short port)
  72 {
  73         return inw_p(port);
  74 }
  75
  76 #else                           /* !ROCKET_DEBUG_IO */
  77 #define sOutB(a, b) outb_p(b, a)
  78 #define sOutW(a, b) outw_p(b, a)
  79 #define sOutDW(port, value) outl_p(cpu_to_le32(value), port)
  80 #define sInB(a) (inb_p(a))
  81 #define sInW(a) (inw_p(a))
  82 #endif                          /* ROCKET_DEBUG_IO */
  83
  84 /* This is used to move arrays of bytes so byte swapping isn't appropriate. */
  85 #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count)
  86 #define sInStrW(port, addr, count) if (count) insw(port, addr, count)
  87
  88 #define CTL_SIZE 8
  89 #define AIOP_CTL_SIZE 4
  90 #define CHAN_AIOP_SIZE 8
  91 #define MAX_PORTS_PER_AIOP 8
  92 #define MAX_AIOPS_PER_BOARD 4
  93 #define MAX_PORTS_PER_BOARD 32
  94
  95 /* Bus type ID */
  96 #define isISA   0
  97 #define isPCI   1
  98 #define isMC    2
  99
 100 /* Controller ID numbers */
 101 #define CTLID_NULL  -1          /* no controller exists */
 102 #define CTLID_0001  0x0001      /* controller release 1 */
 103
 104 /* AIOP ID numbers, identifies AIOP type implementing channel */
 105 #define AIOPID_NULL -1          /* no AIOP or channel exists */
 106 #define AIOPID_0001 0x0001      /* AIOP release 1 */
 107
 108 #define NULLDEV -1              /* identifies non-existant device */
 109 #define NULLCTL -1              /* identifies non-existant controller */
 110 #define NULLCTLPTR (CONTROLLER_T *)0    /* identifies non-existant controller */
 111 #define NULLAIOP -1             /* identifies non-existant AIOP */
 112 #define NULLCHAN -1             /* identifies non-existant channel */
 113
 114 /************************************************************************
 115  Global Register Offsets - Direct Access - Fixed values
 116 ************************************************************************/
 117
 118 #define _CMD_REG   0x38         /* Command Register            8    Write */
 119 #define _INT_CHAN  0x39         /* Interrupt Channel Register  8    Read */
 120 #define _INT_MASK  0x3A         /* Interrupt Mask Register     8    Read / Write */
 121 #define _UNUSED    0x3B         /* Unused                      8 */
 122 #define _INDX_ADDR 0x3C         /* Index Register Address      16   Write */
 123 #define _INDX_DATA 0x3E         /* Index Register Data         8/16 Read / Write */
 124
 125 /************************************************************************
 126  Channel Register Offsets for 1st channel in AIOP - Direct Access
 127 ************************************************************************/
 128 #define _TD0       0x00         /* Transmit Data               16   Write */
 129 #define _RD0       0x00         /* Receive Data                16   Read */
 130 #define _CHN_STAT0 0x20         /* Channel Status              8/16 Read / Write */
 131 #define _FIFO_CNT0 0x10         /* Transmit/Receive FIFO Count 16   Read */
 132 #define _INT_ID0   0x30         /* Interrupt Identification    8    Read */
 133
 134 /************************************************************************
 135  Tx Control Register Offsets - Indexed - External - Fixed
 136 ************************************************************************/
 137 #define _TX_ENBLS  0x980        /* Tx Processor Enables Register 8 Read / Write */
 138 #define _TXCMP1    0x988        /* Transmit Compare Value #1     8 Read / Write */
 139 #define _TXCMP2    0x989        /* Transmit Compare Value #2     8 Read / Write */
 140 #define _TXREP1B1  0x98A        /* Tx Replace Value #1 - Byte 1  8 Read / Write */
 141 #define _TXREP1B2  0x98B        /* Tx Replace Value #1 - Byte 2  8 Read / Write */
 142 #define _TXREP2    0x98C        /* Transmit Replace Value #2     8 Read / Write */
 143
 144 /************************************************************************
 145 Memory Controller Register Offsets - Indexed - External - Fixed
 146 ************************************************************************/
 147 #define _RX_FIFO    0x000       /* Rx FIFO */
 148 #define _TX_FIFO    0x800       /* Tx FIFO */
 149 #define _RXF_OUTP   0x990       /* Rx FIFO OUT pointer        16 Read / Write */
 150 #define _RXF_INP    0x992       /* Rx FIFO IN pointer         16 Read / Write */
 151 #define _TXF_OUTP   0x994       /* Tx FIFO OUT pointer        8  Read / Write */
 152 #define _TXF_INP    0x995       /* Tx FIFO IN pointer         8  Read / Write */
 153 #define _TXP_CNT    0x996       /* Tx Priority Count          8  Read / Write */
 154 #define _TXP_PNTR   0x997       /* Tx Priority Pointer        8  Read / Write */
 155
 156 #define PRI_PEND    0x80        /* Priority data pending (bit7, Tx pri cnt) */
 157 #define TXFIFO_SIZE 255         /* size of Tx FIFO */
 158 #define RXFIFO_SIZE 1023        /* size of Rx FIFO */
 159
 160 /************************************************************************
 161 Tx Priority Buffer - Indexed - External - Fixed
 162 ************************************************************************/
 163 #define _TXP_BUF    0x9C0       /* Tx Priority Buffer  32  Bytes   Read / Write */
 164 #define TXP_SIZE    0x20        /* 32 bytes */
 165
 166 /************************************************************************
 167 Channel Register Offsets - Indexed - Internal - Fixed
 168 ************************************************************************/
 169
 170 #define _TX_CTRL    0xFF0       /* Transmit Control               16  Write */
 171 #define _RX_CTRL    0xFF2       /* Receive Control                 8  Write */
 172 #define _BAUD       0xFF4       /* Baud Rate                      16  Write */
 173 #define _CLK_PRE    0xFF6       /* Clock Prescaler                 8  Write */
 174
 175 #define STMBREAK   0x08         /* BREAK */
 176 #define STMFRAME   0x04         /* framing error */
 177 #define STMRCVROVR 0x02         /* receiver over run error */
 178 #define STMPARITY  0x01         /* parity error */
 179 #define STMERROR   (STMBREAK | STMFRAME | STMPARITY)
 180 #define STMBREAKH   0x800       /* BREAK */
 181 #define STMFRAMEH   0x400       /* framing error */
 182 #define STMRCVROVRH 0x200       /* receiver over run error */
 183 #define STMPARITYH  0x100       /* parity error */
 184 #define STMERRORH   (STMBREAKH | STMFRAMEH | STMPARITYH)
 185
 186 #define CTS_ACT   0x20          /* CTS input asserted */
 187 #define DSR_ACT   0x10          /* DSR input asserted */
 188 #define CD_ACT    0x08          /* CD input asserted */
 189 #define TXFIFOMT  0x04          /* Tx FIFO is empty */
 190 #define TXSHRMT   0x02          /* Tx shift register is empty */
 191 #define RDA       0x01          /* Rx data available */
 192 #define DRAINED (TXFIFOMT | TXSHRMT)    /* indicates Tx is drained */
 193
 194 #define STATMODE  0x8000        /* status mode enable bit */
 195 #define RXFOVERFL 0x2000        /* receive FIFO overflow */
 196 #define RX2MATCH  0x1000        /* receive compare byte 2 match */
 197 #define RX1MATCH  0x0800        /* receive compare byte 1 match */
 198 #define RXBREAK   0x0400        /* received BREAK */
 199 #define RXFRAME   0x0200        /* received framing error */
 200 #define RXPARITY  0x0100        /* received parity error */
 201 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
 202
 203 #define CTSFC_EN  0x80          /* CTS flow control enable bit */
 204 #define RTSTOG_EN 0x40          /* RTS toggle enable bit */
 205 #define TXINT_EN  0x10          /* transmit interrupt enable */
 206 #define STOP2     0x08          /* enable 2 stop bits (0 = 1 stop) */
 207 #define PARITY_EN 0x04          /* enable parity (0 = no parity) */
 208 #define EVEN_PAR  0x02          /* even parity (0 = odd parity) */
 209 #define DATA8BIT  0x01          /* 8 bit data (0 = 7 bit data) */
 210
 211 #define SETBREAK  0x10          /* send break condition (must clear) */
 212 #define LOCALLOOP 0x08          /* local loopback set for test */
 213 #define SET_DTR   0x04          /* assert DTR */
 214 #define SET_RTS   0x02          /* assert RTS */
 215 #define TX_ENABLE 0x01          /* enable transmitter */
 216
 217 #define RTSFC_EN  0x40          /* RTS flow control enable */
 218 #define RXPROC_EN 0x20          /* receive processor enable */
 219 #define TRIG_NO   0x00          /* Rx FIFO trigger level 0 (no trigger) */
 220 #define TRIG_1    0x08          /* trigger level 1 char */
 221 #define TRIG_1_2  0x10          /* trigger level 1/2 */
 222 #define TRIG_7_8  0x18          /* trigger level 7/8 */
 223 #define TRIG_MASK 0x18          /* trigger level mask */
 224 #define SRCINT_EN 0x04          /* special Rx condition interrupt enable */
 225 #define RXINT_EN  0x02          /* Rx interrupt enable */
 226 #define MCINT_EN  0x01          /* modem change interrupt enable */
 227
 228 #define RXF_TRIG  0x20          /* Rx FIFO trigger level interrupt */
 229 #define TXFIFO_MT 0x10          /* Tx FIFO empty interrupt */
 230 #define SRC_INT   0x08          /* special receive condition interrupt */
 231 #define DELTA_CD  0x04          /* CD change interrupt */
 232 #define DELTA_CTS 0x02          /* CTS change interrupt */
 233 #define DELTA_DSR 0x01          /* DSR change interrupt */
 234
 235 #define REP1W2_EN 0x10          /* replace byte 1 with 2 bytes enable */
 236 #define IGN2_EN   0x08          /* ignore byte 2 enable */
 237 #define IGN1_EN   0x04          /* ignore byte 1 enable */
 238 #define COMP2_EN  0x02          /* compare byte 2 enable */
 239 #define COMP1_EN  0x01          /* compare byte 1 enable */
 240
 241 #define RESET_ALL 0x80          /* reset AIOP (all channels) */
 242 #define TXOVERIDE 0x40          /* Transmit software off override */
 243 #define RESETUART 0x20          /* reset channel's UART */
 244 #define RESTXFCNT 0x10          /* reset channel's Tx FIFO count register */
 245 #define RESRXFCNT 0x08          /* reset channel's Rx FIFO count register */
 246
 247 #define INTSTAT0  0x01          /* AIOP 0 interrupt status */
 248 #define INTSTAT1  0x02          /* AIOP 1 interrupt status */
 249 #define INTSTAT2  0x04          /* AIOP 2 interrupt status */
 250 #define INTSTAT3  0x08          /* AIOP 3 interrupt status */
 251
 252 #define INTR_EN   0x08          /* allow interrupts to host */
 253 #define INT_STROB 0x04          /* strobe and clear interrupt line (EOI) */
 254
 255 /**************************************************************************
 256  MUDBAC remapped for PCI
 257 **************************************************************************/
 258
 259 #define _CFG_INT_PCI  0x40
 260 #define _PCI_INT_FUNC 0x3A
 261
 262 #define PCI_STROB 0x2000        /* bit 13 of int aiop register */
 263 #define INTR_EN_PCI   0x0010    /* allow interrupts to host */
 264
 265 /*
 266  * Definitions for Universal PCI board registers
 267  */
 268 #define _PCI_9030_INT_CTRL      0x4c          /* Offsets from BAR1 */
 269 #define _PCI_9030_GPIO_CTRL     0x54
 270 #define PCI_INT_CTRL_AIOP       0x0001
 271 #define PCI_GPIO_CTRL_8PORT     0x4000
 272 #define _PCI_9030_RING_IND      0xc0          /* Offsets from BAR1 */
 273
 274 #define CHAN3_EN  0x08          /* enable AIOP 3 */
 275 #define CHAN2_EN  0x04          /* enable AIOP 2 */
 276 #define CHAN1_EN  0x02          /* enable AIOP 1 */
 277 #define CHAN0_EN  0x01          /* enable AIOP 0 */
 278 #define FREQ_DIS  0x00
 279 #define FREQ_274HZ 0x60
 280 #define FREQ_137HZ 0x50
 281 #define FREQ_69HZ  0x40
 282 #define FREQ_34HZ  0x30
 283 #define FREQ_17HZ  0x20
 284 #define FREQ_9HZ   0x10
 285 #define PERIODIC_ONLY 0x80      /* only PERIODIC interrupt */
 286
 287 #define CHANINT_EN 0x0100       /* flags to enable/disable channel ints */
 288
 289 #define RDATASIZE 72
 290 #define RREGDATASIZE 52
 291
 292 /*
 293  * AIOP interrupt bits for ISA/PCI boards and UPCI boards.
 294  */
 295 #define AIOP_INTR_BIT_0         0x0001
 296 #define AIOP_INTR_BIT_1         0x0002
 297 #define AIOP_INTR_BIT_2         0x0004
 298 #define AIOP_INTR_BIT_3         0x0008
 299
 300 #define AIOP_INTR_BITS ( \
 301         AIOP_INTR_BIT_0 \
 302         | AIOP_INTR_BIT_1 \
 303         | AIOP_INTR_BIT_2 \
 304         | AIOP_INTR_BIT_3)
 305
 306 #define UPCI_AIOP_INTR_BIT_0    0x0004
 307 #define UPCI_AIOP_INTR_BIT_1    0x0020
 308 #define UPCI_AIOP_INTR_BIT_2    0x0100
 309 #define UPCI_AIOP_INTR_BIT_3    0x0800
 310
 311 #define UPCI_AIOP_INTR_BITS ( \
 312         UPCI_AIOP_INTR_BIT_0 \
 313         | UPCI_AIOP_INTR_BIT_1 \
 314         | UPCI_AIOP_INTR_BIT_2 \
 315         | UPCI_AIOP_INTR_BIT_3)
 316
 317 /* Controller level information structure */
 318 typedef struct {
 319         int CtlID;
 320         int CtlNum;
 321         int BusType;
 322         int boardType;
 323         int isUPCI;
 324         WordIO_t PCIIO;
 325         WordIO_t PCIIO2;
 326         ByteIO_t MBaseIO;
 327         ByteIO_t MReg1IO;
 328         ByteIO_t MReg2IO;
 329         ByteIO_t MReg3IO;
 330         Byte_t MReg2;
 331         Byte_t MReg3;
 332         int NumAiop;
 333         int AltChanRingIndicator;
 334         ByteIO_t UPCIRingInd;
 335         WordIO_t AiopIO[AIOP_CTL_SIZE];
 336         ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
 337         int AiopID[AIOP_CTL_SIZE];
 338         int AiopNumChan[AIOP_CTL_SIZE];
 339         Word_t *AiopIntrBits;
 340 } CONTROLLER_T;
 341
 342 typedef CONTROLLER_T CONTROLLER_t;
 343
 344 /* Channel level information structure */
 345 typedef struct {
 346         CONTROLLER_T *CtlP;
 347         int AiopNum;
 348         int ChanID;
 349         int ChanNum;
 350         int rtsToggle;
 351
 352         ByteIO_t Cmd;
 353         ByteIO_t IntChan;
 354         ByteIO_t IntMask;
 355         DWordIO_t IndexAddr;
 356         WordIO_t IndexData;
 357
 358         WordIO_t TxRxData;
 359         WordIO_t ChanStat;
 360         WordIO_t TxRxCount;
 361         ByteIO_t IntID;
 362
 363         Word_t TxFIFO;
 364         Word_t TxFIFOPtrs;
 365         Word_t RxFIFO;
 366         Word_t RxFIFOPtrs;
 367         Word_t TxPrioCnt;
 368         Word_t TxPrioPtr;
 369         Word_t TxPrioBuf;
 370
 371         Byte_t R[RREGDATASIZE];
 372
 373         Byte_t BaudDiv[4];
 374         Byte_t TxControl[4];
 375         Byte_t RxControl[4];
 376         Byte_t TxEnables[4];
 377         Byte_t TxCompare[4];
 378         Byte_t TxReplace1[4];
 379         Byte_t TxReplace2[4];
 380 } CHANNEL_T;
 381
 382 typedef CHANNEL_T CHANNEL_t;
 383 typedef CHANNEL_T *CHANPTR_T;
 384
 385 #define InterfaceModeRS232  0x00
 386 #define InterfaceModeRS422  0x08
 387 #define InterfaceModeRS485  0x10
 388 #define InterfaceModeRS232T 0x18
 389
 390 /***************************************************************************
 391 Function: sClrBreak
 392 Purpose:  Stop sending a transmit BREAK signal
 393 Call:     sClrBreak(ChP)
 394           CHANNEL_T *ChP; Ptr to channel structure
 395 */
 396 #define sClrBreak(ChP) \
 397 do { \
 398    (ChP)->TxControl[3] &= ~SETBREAK; \
 399    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 400 } while (0)
 401
 402 /***************************************************************************
 403 Function: sClrDTR
 404 Purpose:  Clr the DTR output
 405 Call:     sClrDTR(ChP)
 406           CHANNEL_T *ChP; Ptr to channel structure
 407 */
 408 #define sClrDTR(ChP) \
 409 do { \
 410    (ChP)->TxControl[3] &= ~SET_DTR; \
 411    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 412 } while (0)
 413
 414 /***************************************************************************
 415 Function: sClrRTS
 416 Purpose:  Clr the RTS output
 417 Call:     sClrRTS(ChP)
 418           CHANNEL_T *ChP; Ptr to channel structure
 419 */
 420 #define sClrRTS(ChP) \
 421 do { \
 422    if ((ChP)->rtsToggle) break; \
 423    (ChP)->TxControl[3] &= ~SET_RTS; \
 424    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 425 } while (0)
 426
 427 /***************************************************************************
 428 Function: sClrTxXOFF
 429 Purpose:  Clear any existing transmit software flow control off condition
 430 Call:     sClrTxXOFF(ChP)
 431           CHANNEL_T *ChP; Ptr to channel structure
 432 */
 433 #define sClrTxXOFF(ChP) \
 434 do { \
 435    sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
 436    sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
 437 } while (0)
 438
 439 /***************************************************************************
 440 Function: sCtlNumToCtlPtr
 441 Purpose:  Convert a controller number to controller structure pointer
 442 Call:     sCtlNumToCtlPtr(CtlNum)
 443           int CtlNum; Controller number
 444 Return:   CONTROLLER_T *: Ptr to controller structure
 445 */
 446 #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
 447
 448 /***************************************************************************
 449 Function: sControllerEOI
 450 Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
 451 Call:     sControllerEOI(CtlP)
 452           CONTROLLER_T *CtlP; Ptr to controller structure
 453 */
 454 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
 455
 456 /***************************************************************************
 457 Function: sPCIControllerEOI
 458 Purpose:  Strobe the PCI End Of Interrupt bit.
 459           For the UPCI boards, toggle the AIOP interrupt enable bit
 460           (this was taken from the Windows driver).
 461 Call:     sPCIControllerEOI(CtlP)
 462           CONTROLLER_T *CtlP; Ptr to controller structure
 463 */
 464 #define sPCIControllerEOI(CTLP) \
 465 do { \
 466     if ((CTLP)->isUPCI) { \
 467         Word_t w = sInW((CTLP)->PCIIO); \
 468         sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
 469         sOutW((CTLP)->PCIIO, w); \
 470     } \
 471     else { \
 472         sOutW((CTLP)->PCIIO, PCI_STROB); \
 473     } \
 474 } while (0)
 475
 476 /***************************************************************************
 477 Function: sDisAiop
 478 Purpose:  Disable I/O access to an AIOP
 479 Call:     sDisAiop(CltP)
 480           CONTROLLER_T *CtlP; Ptr to controller structure
 481           int AiopNum; Number of AIOP on controller
 482 */
 483 #define sDisAiop(CTLP,AIOPNUM) \
 484 do { \
 485    (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
 486    sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
 487 } while (0)
 488
 489 /***************************************************************************
 490 Function: sDisCTSFlowCtl
 491 Purpose:  Disable output flow control using CTS
 492 Call:     sDisCTSFlowCtl(ChP)
 493           CHANNEL_T *ChP; Ptr to channel structure
 494 */
 495 #define sDisCTSFlowCtl(ChP) \
 496 do { \
 497    (ChP)->TxControl[2] &= ~CTSFC_EN; \
 498    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 499 } while (0)
 500
 501 /***************************************************************************
 502 Function: sDisIXANY
 503 Purpose:  Disable IXANY Software Flow Control
 504 Call:     sDisIXANY(ChP)
 505           CHANNEL_T *ChP; Ptr to channel structure
 506 */
 507 #define sDisIXANY(ChP) \
 508 do { \
 509    (ChP)->R[0x0e] = 0x86; \
 510    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
 511 } while (0)
 512
 513 /***************************************************************************
 514 Function: DisParity
 515 Purpose:  Disable parity
 516 Call:     sDisParity(ChP)
 517           CHANNEL_T *ChP; Ptr to channel structure
 518 Comments: Function sSetParity() can be used in place of functions sEnParity(),
 519           sDisParity(), sSetOddParity(), and sSetEvenParity().
 520 */
 521 #define sDisParity(ChP) \
 522 do { \
 523    (ChP)->TxControl[2] &= ~PARITY_EN; \
 524    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 525 } while (0)
 526
 527 /***************************************************************************
 528 Function: sDisRTSToggle
 529 Purpose:  Disable RTS toggle
 530 Call:     sDisRTSToggle(ChP)
 531           CHANNEL_T *ChP; Ptr to channel structure
 532 */
 533 #define sDisRTSToggle(ChP) \
 534 do { \
 535    (ChP)->TxControl[2] &= ~RTSTOG_EN; \
 536    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 537    (ChP)->rtsToggle = 0; \
 538 } while (0)
 539
 540 /***************************************************************************
 541 Function: sDisRxFIFO
 542 Purpose:  Disable Rx FIFO
 543 Call:     sDisRxFIFO(ChP)
 544           CHANNEL_T *ChP; Ptr to channel structure
 545 */
 546 #define sDisRxFIFO(ChP) \
 547 do { \
 548    (ChP)->R[0x32] = 0x0a; \
 549    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
 550 } while (0)
 551
 552 /***************************************************************************
 553 Function: sDisRxStatusMode
 554 Purpose:  Disable the Rx status mode
 555 Call:     sDisRxStatusMode(ChP)
 556           CHANNEL_T *ChP; Ptr to channel structure
 557 Comments: This takes the channel out of the receive status mode.  All
 558           subsequent reads of receive data using sReadRxWord() will return
 559           two data bytes.
 560 */
 561 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
 562
 563 /***************************************************************************
 564 Function: sDisTransmit
 565 Purpose:  Disable transmit
 566 Call:     sDisTransmit(ChP)
 567           CHANNEL_T *ChP; Ptr to channel structure
 568           This disables movement of Tx data from the Tx FIFO into the 1 byte
 569           Tx buffer.  Therefore there could be up to a 2 byte latency
 570           between the time sDisTransmit() is called and the transmit buffer
 571           and transmit shift register going completely empty.
 572 */
 573 #define sDisTransmit(ChP) \
 574 do { \
 575    (ChP)->TxControl[3] &= ~TX_ENABLE; \
 576    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 577 } while (0)
 578
 579 /***************************************************************************
 580 Function: sDisTxSoftFlowCtl
 581 Purpose:  Disable Tx Software Flow Control
 582 Call:     sDisTxSoftFlowCtl(ChP)
 583           CHANNEL_T *ChP; Ptr to channel structure
 584 */
 585 #define sDisTxSoftFlowCtl(ChP) \
 586 do { \
 587    (ChP)->R[0x06] = 0x8a; \
 588    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
 589 } while (0)
 590
 591 /***************************************************************************
 592 Function: sEnAiop
 593 Purpose:  Enable I/O access to an AIOP
 594 Call:     sEnAiop(CltP)
 595           CONTROLLER_T *CtlP; Ptr to controller structure
 596           int AiopNum; Number of AIOP on controller
 597 */
 598 #define sEnAiop(CTLP,AIOPNUM) \
 599 do { \
 600    (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
 601    sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
 602 } while (0)
 603
 604 /***************************************************************************
 605 Function: sEnCTSFlowCtl
 606 Purpose:  Enable output flow control using CTS
 607 Call:     sEnCTSFlowCtl(ChP)
 608           CHANNEL_T *ChP; Ptr to channel structure
 609 */
 610 #define sEnCTSFlowCtl(ChP) \
 611 do { \
 612    (ChP)->TxControl[2] |= CTSFC_EN; \
 613    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 614 } while (0)
 615
 616 /***************************************************************************
 617 Function: sEnIXANY
 618 Purpose:  Enable IXANY Software Flow Control
 619 Call:     sEnIXANY(ChP)
 620           CHANNEL_T *ChP; Ptr to channel structure
 621 */
 622 #define sEnIXANY(ChP) \
 623 do { \
 624    (ChP)->R[0x0e] = 0x21; \
 625    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \
 626 } while (0)
 627
 628 /***************************************************************************
 629 Function: EnParity
 630 Purpose:  Enable parity
 631 Call:     sEnParity(ChP)
 632           CHANNEL_T *ChP; Ptr to channel structure
 633 Comments: Function sSetParity() can be used in place of functions sEnParity(),
 634           sDisParity(), sSetOddParity(), and sSetEvenParity().
 635
 636 Warnings: Before enabling parity odd or even parity should be chosen using
 637           functions sSetOddParity() or sSetEvenParity().
 638 */
 639 #define sEnParity(ChP) \
 640 do { \
 641    (ChP)->TxControl[2] |= PARITY_EN; \
 642    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 643 } while (0)
 644
 645 /***************************************************************************
 646 Function: sEnRTSToggle
 647 Purpose:  Enable RTS toggle
 648 Call:     sEnRTSToggle(ChP)
 649           CHANNEL_T *ChP; Ptr to channel structure
 650 Comments: This function will disable RTS flow control and clear the RTS
 651           line to allow operation of RTS toggle.
 652 */
 653 #define sEnRTSToggle(ChP) \
 654 do { \
 655    (ChP)->RxControl[2] &= ~RTSFC_EN; \
 656    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
 657    (ChP)->TxControl[2] |= RTSTOG_EN; \
 658    (ChP)->TxControl[3] &= ~SET_RTS; \
 659    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 660    (ChP)->rtsToggle = 1; \
 661 } while (0)
 662
 663 /***************************************************************************
 664 Function: sEnRxFIFO
 665 Purpose:  Enable Rx FIFO
 666 Call:     sEnRxFIFO(ChP)
 667           CHANNEL_T *ChP; Ptr to channel structure
 668 */
 669 #define sEnRxFIFO(ChP) \
 670 do { \
 671    (ChP)->R[0x32] = 0x08; \
 672    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
 673 } while (0)
 674
 675 /***************************************************************************
 676 Function: sEnRxProcessor
 677 Purpose:  Enable the receive processor
 678 Call:     sEnRxProcessor(ChP)
 679           CHANNEL_T *ChP; Ptr to channel structure
 680 Comments: This function is used to start the receive processor.  When
 681           the channel is in the reset state the receive processor is not
 682           running.  This is done to prevent the receive processor from
 683           executing invalid microcode instructions prior to the
 684           downloading of the microcode.
 685
 686 Warnings: This function must be called after valid microcode has been
 687           downloaded to the AIOP, and it must not be called before the
 688           microcode has been downloaded.
 689 */
 690 #define sEnRxProcessor(ChP) \
 691 do { \
 692    (ChP)->RxControl[2] |= RXPROC_EN; \
 693    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
 694 } while (0)
 695
 696 /***************************************************************************
 697 Function: sEnRxStatusMode
 698 Purpose:  Enable the Rx status mode
 699 Call:     sEnRxStatusMode(ChP)
 700           CHANNEL_T *ChP; Ptr to channel structure
 701 Comments: This places the channel in the receive status mode.  All subsequent
 702           reads of receive data using sReadRxWord() will return a data byte
 703           in the low word and a status byte in the high word.
 704
 705 */
 706 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
 707
 708 /***************************************************************************
 709 Function: sEnTransmit
 710 Purpose:  Enable transmit
 711 Call:     sEnTransmit(ChP)
 712           CHANNEL_T *ChP; Ptr to channel structure
 713 */
 714 #define sEnTransmit(ChP) \
 715 do { \
 716    (ChP)->TxControl[3] |= TX_ENABLE; \
 717    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 718 } while (0)
 719
 720 /***************************************************************************
 721 Function: sEnTxSoftFlowCtl
 722 Purpose:  Enable Tx Software Flow Control
 723 Call:     sEnTxSoftFlowCtl(ChP)
 724           CHANNEL_T *ChP; Ptr to channel structure
 725 */
 726 #define sEnTxSoftFlowCtl(ChP) \
 727 do { \
 728    (ChP)->R[0x06] = 0xc5; \
 729    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
 730 } while (0)
 731
 732 /***************************************************************************
 733 Function: sGetAiopIntStatus
 734 Purpose:  Get the AIOP interrupt status
 735 Call:     sGetAiopIntStatus(CtlP,AiopNum)
 736           CONTROLLER_T *CtlP; Ptr to controller structure
 737           int AiopNum; AIOP number
 738 Return:   Byte_t: The AIOP interrupt status.  Bits 0 through 7
 739                          represent channels 0 through 7 respectively.  If a
 740                          bit is set that channel is interrupting.
 741 */
 742 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
 743
 744 /***************************************************************************
 745 Function: sGetAiopNumChan
 746 Purpose:  Get the number of channels supported by an AIOP
 747 Call:     sGetAiopNumChan(CtlP,AiopNum)
 748           CONTROLLER_T *CtlP; Ptr to controller structure
 749           int AiopNum; AIOP number
 750 Return:   int: The number of channels supported by the AIOP
 751 */
 752 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
 753
 754 /***************************************************************************
 755 Function: sGetChanIntID
 756 Purpose:  Get a channel's interrupt identification byte
 757 Call:     sGetChanIntID(ChP)
 758           CHANNEL_T *ChP; Ptr to channel structure
 759 Return:   Byte_t: The channel interrupt ID.  Can be any
 760              combination of the following flags:
 761                 RXF_TRIG:     Rx FIFO trigger level interrupt
 762                 TXFIFO_MT:    Tx FIFO empty interrupt
 763                 SRC_INT:      Special receive condition interrupt
 764                 DELTA_CD:     CD change interrupt
 765                 DELTA_CTS:    CTS change interrupt
 766                 DELTA_DSR:    DSR change interrupt
 767 */
 768 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
 769
 770 /***************************************************************************
 771 Function: sGetChanNum
 772 Purpose:  Get the number of a channel within an AIOP
 773 Call:     sGetChanNum(ChP)
 774           CHANNEL_T *ChP; Ptr to channel structure
 775 Return:   int: Channel number within AIOP, or NULLCHAN if channel does
 776                not exist.
 777 */
 778 #define sGetChanNum(ChP) (ChP)->ChanNum
 779
 780 /***************************************************************************
 781 Function: sGetChanStatus
 782 Purpose:  Get the channel status
 783 Call:     sGetChanStatus(ChP)
 784           CHANNEL_T *ChP; Ptr to channel structure
 785 Return:   Word_t: The channel status.  Can be any combination of
 786              the following flags:
 787                 LOW BYTE FLAGS
 788                 CTS_ACT:      CTS input asserted
 789                 DSR_ACT:      DSR input asserted
 790                 CD_ACT:       CD input asserted
 791                 TXFIFOMT:     Tx FIFO is empty
 792                 TXSHRMT:      Tx shift register is empty
 793                 RDA:          Rx data available
 794
 795                 HIGH BYTE FLAGS
 796                 STATMODE:     status mode enable bit
 797                 RXFOVERFL:    receive FIFO overflow
 798                 RX2MATCH:     receive compare byte 2 match
 799                 RX1MATCH:     receive compare byte 1 match
 800                 RXBREAK:      received BREAK
 801                 RXFRAME:      received framing error
 802                 RXPARITY:     received parity error
 803 Warnings: This function will clear the high byte flags in the Channel
 804           Status Register.
 805 */
 806 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
 807
 808 /***************************************************************************
 809 Function: sGetChanStatusLo
 810 Purpose:  Get the low byte only of the channel status
 811 Call:     sGetChanStatusLo(ChP)
 812           CHANNEL_T *ChP; Ptr to channel structure
 813 Return:   Byte_t: The channel status low byte.  Can be any combination
 814              of the following flags:
 815                 CTS_ACT:      CTS input asserted
 816                 DSR_ACT:      DSR input asserted
 817                 CD_ACT:       CD input asserted
 818                 TXFIFOMT:     Tx FIFO is empty
 819                 TXSHRMT:      Tx shift register is empty
 820                 RDA:          Rx data available
 821 */
 822 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
 823
 824 /**********************************************************************
 825  * Get RI status of channel
 826  * Defined as a function in rocket.c   -aes
 827  */
 828 #if 0
 829 #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
 830                           (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
 831                             (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
 832                                (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
 833                              0))
 834 #endif
 835
 836 /***************************************************************************
 837 Function: sGetControllerIntStatus
 838 Purpose:  Get the controller interrupt status
 839 Call:     sGetControllerIntStatus(CtlP)
 840           CONTROLLER_T *CtlP; Ptr to controller structure
 841 Return:   Byte_t: The controller interrupt status in the lower 4
 842                          bits.  Bits 0 through 3 represent AIOP's 0
 843                          through 3 respectively.  If a bit is set that
 844                          AIOP is interrupting.  Bits 4 through 7 will
 845                          always be cleared.
 846 */
 847 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
 848
 849 /***************************************************************************
 850 Function: sPCIGetControllerIntStatus
 851 Purpose:  Get the controller interrupt status
 852 Call:     sPCIGetControllerIntStatus(CtlP)
 853           CONTROLLER_T *CtlP; Ptr to controller structure
 854 Return:   unsigned char: The controller interrupt status in the lower 4
 855                          bits and bit 4.  Bits 0 through 3 represent AIOP's 0
 856                          through 3 respectively. Bit 4 is set if the int
 857                          was generated from periodic. If a bit is set the
 858                          AIOP is interrupting.
 859 */
 860 #define sPCIGetControllerIntStatus(CTLP) \
 861         ((CTLP)->isUPCI ? \
 862           (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
 863           ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
 864
 865 /***************************************************************************
 866
 867 Function: sGetRxCnt
 868 Purpose:  Get the number of data bytes in the Rx FIFO
 869 Call:     sGetRxCnt(ChP)
 870           CHANNEL_T *ChP; Ptr to channel structure
 871 Return:   int: The number of data bytes in the Rx FIFO.
 872 Comments: Byte read of count register is required to obtain Rx count.
 873
 874 */
 875 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
 876
 877 /***************************************************************************
 878 Function: sGetTxCnt
 879 Purpose:  Get the number of data bytes in the Tx FIFO
 880 Call:     sGetTxCnt(ChP)
 881           CHANNEL_T *ChP; Ptr to channel structure
 882 Return:   Byte_t: The number of data bytes in the Tx FIFO.
 883 Comments: Byte read of count register is required to obtain Tx count.
 884
 885 */
 886 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
 887
 888 /*****************************************************************************
 889 Function: sGetTxRxDataIO
 890 Purpose:  Get the I/O address of a channel's TxRx Data register
 891 Call:     sGetTxRxDataIO(ChP)
 892           CHANNEL_T *ChP; Ptr to channel structure
 893 Return:   WordIO_t: I/O address of a channel's TxRx Data register
 894 */
 895 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
 896
 897 /***************************************************************************
 898 Function: sInitChanDefaults
 899 Purpose:  Initialize a channel structure to it's default state.
 900 Call:     sInitChanDefaults(ChP)
 901           CHANNEL_T *ChP; Ptr to the channel structure
 902 Comments: This function must be called once for every channel structure
 903           that exists before any other SSCI calls can be made.
 904
 905 */
 906 #define sInitChanDefaults(ChP) \
 907 do { \
 908    (ChP)->CtlP = NULLCTLPTR; \
 909    (ChP)->AiopNum = NULLAIOP; \
 910    (ChP)->ChanID = AIOPID_NULL; \
 911    (ChP)->ChanNum = NULLCHAN; \
 912 } while (0)
 913
 914 /***************************************************************************
 915 Function: sResetAiopByNum
 916 Purpose:  Reset the AIOP by number
 917 Call:     sResetAiopByNum(CTLP,AIOPNUM)
 918         CONTROLLER_T CTLP; Ptr to controller structure
 919         AIOPNUM; AIOP index
 920 */
 921 #define sResetAiopByNum(CTLP,AIOPNUM) \
 922 do { \
 923    sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
 924    sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
 925 } while (0)
 926
 927 /***************************************************************************
 928 Function: sSendBreak
 929 Purpose:  Send a transmit BREAK signal
 930 Call:     sSendBreak(ChP)
 931           CHANNEL_T *ChP; Ptr to channel structure
 932 */
 933 #define sSendBreak(ChP) \
 934 do { \
 935    (ChP)->TxControl[3] |= SETBREAK; \
 936    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 937 } while (0)
 938
 939 /***************************************************************************
 940 Function: sSetBaud
 941 Purpose:  Set baud rate
 942 Call:     sSetBaud(ChP,Divisor)
 943           CHANNEL_T *ChP; Ptr to channel structure
 944           Word_t Divisor; 16 bit baud rate divisor for channel
 945 */
 946 #define sSetBaud(ChP,DIVISOR) \
 947 do { \
 948    (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
 949    (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
 950    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
 951 } while (0)
 952
 953 /***************************************************************************
 954 Function: sSetData7
 955 Purpose:  Set data bits to 7
 956 Call:     sSetData7(ChP)
 957           CHANNEL_T *ChP; Ptr to channel structure
 958 */
 959 #define sSetData7(ChP) \
 960 do { \
 961    (ChP)->TxControl[2] &= ~DATA8BIT; \
 962    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 963 } while (0)
 964
 965 /***************************************************************************
 966 Function: sSetData8
 967 Purpose:  Set data bits to 8
 968 Call:     sSetData8(ChP)
 969           CHANNEL_T *ChP; Ptr to channel structure
 970 */
 971 #define sSetData8(ChP) \
 972 do { \
 973    (ChP)->TxControl[2] |= DATA8BIT; \
 974    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 975 } while (0)
 976
 977 /***************************************************************************
 978 Function: sSetDTR
 979 Purpose:  Set the DTR output
 980 Call:     sSetDTR(ChP)
 981           CHANNEL_T *ChP; Ptr to channel structure
 982 */
 983 #define sSetDTR(ChP) \
 984 do { \
 985    (ChP)->TxControl[3] |= SET_DTR; \
 986    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
 987 } while (0)
 988
 989 /***************************************************************************
 990 Function: sSetEvenParity
 991 Purpose:  Set even parity
 992 Call:     sSetEvenParity(ChP)
 993           CHANNEL_T *ChP; Ptr to channel structure
 994 Comments: Function sSetParity() can be used in place of functions sEnParity(),
 995           sDisParity(), sSetOddParity(), and sSetEvenParity().
 996
 997 Warnings: This function has no effect unless parity is enabled with function
 998           sEnParity().
 999 */
1000 #define sSetEvenParity(ChP) \
1001 do { \
1002    (ChP)->TxControl[2] |= EVEN_PAR; \
1003    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1004 } while (0)
1005
1006 /***************************************************************************
1007 Function: sSetOddParity
1008 Purpose:  Set odd parity
1009 Call:     sSetOddParity(ChP)
1010           CHANNEL_T *ChP; Ptr to channel structure
1011 Comments: Function sSetParity() can be used in place of functions sEnParity(),
1012           sDisParity(), sSetOddParity(), and sSetEvenParity().
1013
1014 Warnings: This function has no effect unless parity is enabled with function
1015           sEnParity().
1016 */
1017 #define sSetOddParity(ChP) \
1018 do { \
1019    (ChP)->TxControl[2] &= ~EVEN_PAR; \
1020    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1021 } while (0)
1022
1023 /***************************************************************************
1024 Function: sSetRTS
1025 Purpose:  Set the RTS output
1026 Call:     sSetRTS(ChP)
1027           CHANNEL_T *ChP; Ptr to channel structure
1028 */
1029 #define sSetRTS(ChP) \
1030 do { \
1031    if ((ChP)->rtsToggle) break; \
1032    (ChP)->TxControl[3] |= SET_RTS; \
1033    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1034 } while (0)
1035
1036 /***************************************************************************
1037 Function: sSetRxTrigger
1038 Purpose:  Set the Rx FIFO trigger level
1039 Call:     sSetRxProcessor(ChP,Level)
1040           CHANNEL_T *ChP; Ptr to channel structure
1041           Byte_t Level; Number of characters in Rx FIFO at which the
1042              interrupt will be generated.  Can be any of the following flags:
1043
1044              TRIG_NO:   no trigger
1045              TRIG_1:    1 character in FIFO
1046              TRIG_1_2:  FIFO 1/2 full
1047              TRIG_7_8:  FIFO 7/8 full
1048 Comments: An interrupt will be generated when the trigger level is reached
1049           only if function sEnInterrupt() has been called with flag
1050           RXINT_EN set.  The RXF_TRIG flag in the Interrupt Idenfification
1051           register will be set whenever the trigger level is reached
1052           regardless of the setting of RXINT_EN.
1053
1054 */
1055 #define sSetRxTrigger(ChP,LEVEL) \
1056 do { \
1057    (ChP)->RxControl[2] &= ~TRIG_MASK; \
1058    (ChP)->RxControl[2] |= LEVEL; \
1059    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
1060 } while (0)
1061
1062 /***************************************************************************
1063 Function: sSetStop1
1064 Purpose:  Set stop bits to 1
1065 Call:     sSetStop1(ChP)
1066           CHANNEL_T *ChP; Ptr to channel structure
1067 */
1068 #define sSetStop1(ChP) \
1069 do { \
1070    (ChP)->TxControl[2] &= ~STOP2; \
1071    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1072 } while (0)
1073
1074 /***************************************************************************
1075 Function: sSetStop2
1076 Purpose:  Set stop bits to 2
1077 Call:     sSetStop2(ChP)
1078           CHANNEL_T *ChP; Ptr to channel structure
1079 */
1080 #define sSetStop2(ChP) \
1081 do { \
1082    (ChP)->TxControl[2] |= STOP2; \
1083    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
1084 } while (0)
1085
1086 /***************************************************************************
1087 Function: sSetTxXOFFChar
1088 Purpose:  Set the Tx XOFF flow control character
1089 Call:     sSetTxXOFFChar(ChP,Ch)
1090           CHANNEL_T *ChP; Ptr to channel structure
1091           Byte_t Ch; The value to set the Tx XOFF character to
1092 */
1093 #define sSetTxXOFFChar(ChP,CH) \
1094 do { \
1095    (ChP)->R[0x07] = (CH); \
1096    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
1097 } while (0)
1098
1099 /***************************************************************************
1100 Function: sSetTxXONChar
1101 Purpose:  Set the Tx XON flow control character
1102 Call:     sSetTxXONChar(ChP,Ch)
1103           CHANNEL_T *ChP; Ptr to channel structure
1104           Byte_t Ch; The value to set the Tx XON character to
1105 */
1106 #define sSetTxXONChar(ChP,CH) \
1107 do { \
1108    (ChP)->R[0x0b] = (CH); \
1109    sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \
1110 } while (0)
1111
1112 /***************************************************************************
1113 Function: sStartRxProcessor
1114 Purpose:  Start a channel's receive processor
1115 Call:     sStartRxProcessor(ChP)
1116           CHANNEL_T *ChP; Ptr to channel structure
1117 Comments: This function is used to start a Rx processor after it was
1118           stopped with sStopRxProcessor() or sStopSWInFlowCtl().  It
1119           will restart both the Rx processor and software input flow control.
1120
1121 */
1122 #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
1123
1124 /***************************************************************************
1125 Function: sWriteTxByte
1126 Purpose:  Write a transmit data byte to a channel.
1127           ByteIO_t io: Channel transmit register I/O address.  This can
1128                            be obtained with sGetTxRxDataIO().
1129           Byte_t Data; The transmit data byte.
1130 Warnings: This function writes the data byte without checking to see if
1131           sMaxTxSize is exceeded in the Tx FIFO.
1132 */
1133 #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1134
1135 /*
1136  * Begin Linux specific definitions for the Rocketport driver
1137  *
1138  * This code is Copyright Theodore Ts'o, 1995-1997
1139  */
1140
1141 struct r_port {
1142         int magic;
1143         int line;
1144         int flags;
1145         int count;
1146         int blocked_open;
1147         struct tty_struct *tty;
1148         unsigned int board:3;
1149         unsigned int aiop:2;
1150         unsigned int chan:3;
1151         CONTROLLER_t *ctlp;
1152         CHANNEL_t channel;
1153         int closing_wait;
1154         int close_delay;
1155         int intmask;
1156         int xmit_fifo_room;     /* room in xmit fifo */
1157         unsigned char *xmit_buf;
1158         int xmit_head;
1159         int xmit_tail;
1160         int xmit_cnt;
1161         int cd_status;
1162         int ignore_status_mask;
1163         int read_status_mask;
1164         int cps;
1165
1166         wait_queue_head_t open_wait;
1167         struct completion close_wait;
1168         spinlock_t slock;
1169         struct mutex write_mtx;
1170 };
1171
1172 #define RPORT_MAGIC 0x525001
1173
1174 #define NUM_BOARDS 8
1175 #define MAX_RP_PORTS (32*NUM_BOARDS)
1176
1177 /*
1178  * The size of the xmit buffer is 1 page, or 4096 bytes
1179  */
1180 #define XMIT_BUF_SIZE 4096
1181
1182 /* number of characters left in xmit buffer before we ask for more */
1183 #define WAKEUP_CHARS 256
1184
1185 /* Internal flags used only by the rocketport driver */
1186 #define ROCKET_INITIALIZED      0x80000000      /* Port is active */
1187 #define ROCKET_CLOSING          0x40000000      /* Serial port is closing */
1188 #define ROCKET_NORMAL_ACTIVE    0x20000000      /* Normal port is active */
1189
1190 /* tty subtypes */
1191 #define SERIAL_TYPE_NORMAL 1
1192
1193 /*
1194  * Assigned major numbers for the Comtrol Rocketport
1195  */
1196 #define TTY_ROCKET_MAJOR        46
1197 #define CUA_ROCKET_MAJOR        47
1198
1199 #ifdef PCI_VENDOR_ID_RP
1200 #undef PCI_VENDOR_ID_RP
1201 #undef PCI_DEVICE_ID_RP8OCTA
1202 #undef PCI_DEVICE_ID_RP8INTF
1203 #undef PCI_DEVICE_ID_RP16INTF
1204 #undef PCI_DEVICE_ID_RP32INTF
1205 #undef PCI_DEVICE_ID_URP8OCTA
1206 #undef PCI_DEVICE_ID_URP8INTF
1207 #undef PCI_DEVICE_ID_URP16INTF
1208 #undef PCI_DEVICE_ID_CRP16INTF
1209 #undef PCI_DEVICE_ID_URP32INTF
1210 #endif
1211
1212 /*  Comtrol PCI Vendor ID */
1213 #define PCI_VENDOR_ID_RP                0x11fe
1214
1215 /*  Comtrol Device ID's */
1216 #define PCI_DEVICE_ID_RP32INTF          0x0001  /* Rocketport 32 port w/external I/F     */
1217 #define PCI_DEVICE_ID_RP8INTF           0x0002  /* Rocketport 8 port w/external I/F      */
1218 #define PCI_DEVICE_ID_RP16INTF          0x0003  /* Rocketport 16 port w/external I/F     */
1219 #define PCI_DEVICE_ID_RP4QUAD           0x0004  /* Rocketport 4 port w/quad cable        */
1220 #define PCI_DEVICE_ID_RP8OCTA           0x0005  /* Rocketport 8 port w/octa cable        */
1221 #define PCI_DEVICE_ID_RP8J              0x0006  /* Rocketport 8 port w/RJ11 connectors   */
1222 #define PCI_DEVICE_ID_RP4J              0x0007  /* Rocketport 4 port w/RJ11 connectors   */
1223 #define PCI_DEVICE_ID_RP8SNI            0x0008  /* Rocketport 8 port w/ DB78 SNI (Siemens) connector */
1224 #define PCI_DEVICE_ID_RP16SNI           0x0009  /* Rocketport 16 port w/ DB78 SNI (Siemens) connector   */
1225 #define PCI_DEVICE_ID_RPP4              0x000A  /* Rocketport Plus 4 port                */
1226 #define PCI_DEVICE_ID_RPP8              0x000B  /* Rocketport Plus 8 port                */
1227 #define PCI_DEVICE_ID_RP6M              0x000C  /* RocketModem 6 port                    */
1228 #define PCI_DEVICE_ID_RP4M              0x000D  /* RocketModem 4 port                    */
1229 #define PCI_DEVICE_ID_RP2_232           0x000E  /* Rocketport Plus 2 port RS232          */
1230 #define PCI_DEVICE_ID_RP2_422           0x000F  /* Rocketport Plus 2 port RS422          */
1231
1232 /* Universal PCI boards  */
1233 #define PCI_DEVICE_ID_URP32INTF         0x0801  /* Rocketport UPCI 32 port w/external I/F */
1234 #define PCI_DEVICE_ID_URP8INTF          0x0802  /* Rocketport UPCI 8 port w/external I/F  */
1235 #define PCI_DEVICE_ID_URP16INTF         0x0803  /* Rocketport UPCI 16 port w/external I/F */
1236 #define PCI_DEVICE_ID_URP8OCTA          0x0805  /* Rocketport UPCI 8 port w/octa cable    */
1237 #define PCI_DEVICE_ID_UPCI_RM3_8PORT    0x080C  /* Rocketmodem III 8 port                 */
1238 #define PCI_DEVICE_ID_UPCI_RM3_4PORT    0x080D  /* Rocketmodem III 4 port                 */
1239
1240 /* Compact PCI device */
1241 #define PCI_DEVICE_ID_CRP16INTF         0x0903  /* Rocketport Compact PCI 16 port w/external I/F */
1242
1243 #define TTY_GET_LINE(t) t->index
1244 #define TTY_DRIVER_MINOR_START(t) t->driver->minor_start
1245 #define TTY_DRIVER_SUBTYPE(t) t->driver->subtype
1246 #define TTY_DRIVER_NAME(t) t->driver->name
1247 #define TTY_DRIVER_NAME_BASE(t) t->driver->name_base
1248 #define TTY_DRIVER_FLUSH_BUFFER_EXISTS(t) t->driver->flush_buffer
1249 #define TTY_DRIVER_FLUSH_BUFFER(t) t->driver->flush_buffer(t)
1250
1251