2 * linux/arch/arm/common/it8152.c
4 * Copyright Compulab Ltd, 2002-2007
5 * Mike Rapoport <mike@compulab.co.il>
7 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
8 * (see this file for respective copyrights)
10 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/ptrace.h>
22 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
30 #include <asm/mach/pci.h>
31 #include <asm/hardware/it8152.h>
35 static void it8152_mask_irq(unsigned int irq
)
37 if (irq
>= IT8152_LD_IRQ(0)) {
38 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR
) |
39 (1 << (irq
- IT8152_LD_IRQ(0)))),
41 } else if (irq
>= IT8152_LP_IRQ(0)) {
42 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR
) |
43 (1 << (irq
- IT8152_LP_IRQ(0)))),
45 } else if (irq
>= IT8152_PD_IRQ(0)) {
46 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR
) |
47 (1 << (irq
- IT8152_PD_IRQ(0)))),
52 static void it8152_unmask_irq(unsigned int irq
)
54 if (irq
>= IT8152_LD_IRQ(0)) {
55 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR
) &
56 ~(1 << (irq
- IT8152_LD_IRQ(0)))),
58 } else if (irq
>= IT8152_LP_IRQ(0)) {
59 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR
) &
60 ~(1 << (irq
- IT8152_LP_IRQ(0)))),
62 } else if (irq
>= IT8152_PD_IRQ(0)) {
63 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR
) &
64 ~(1 << (irq
- IT8152_PD_IRQ(0)))),
69 static inline void it8152_irq(int irq
)
71 struct irq_desc
*desc
;
73 desc
= irq_desc
+ irq
;
74 desc_handle_irq(irq
, desc
);
77 static struct irq_chip it8152_irq_chip
= {
79 .ack
= it8152_mask_irq
,
80 .mask
= it8152_mask_irq
,
81 .unmask
= it8152_unmask_irq
,
84 void it8152_init_irq(void)
88 __raw_writel((0xffff), IT8152_INTC_PDCNIMR
);
89 __raw_writel((0), IT8152_INTC_PDCNIRR
);
90 __raw_writel((0xffff), IT8152_INTC_LPCNIMR
);
91 __raw_writel((0), IT8152_INTC_LPCNIRR
);
92 __raw_writel((0xffff), IT8152_INTC_LDCNIMR
);
93 __raw_writel((0), IT8152_INTC_LDCNIRR
);
95 for (irq
= IT8152_IRQ(0); irq
<= IT8152_LAST_IRQ
; irq
++) {
96 set_irq_chip(irq
, &it8152_irq_chip
);
97 set_irq_handler(irq
, handle_level_irq
);
98 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
102 void it8152_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
104 int bits_pd
, bits_lp
, bits_ld
;
109 bits_pd
= __raw_readl(IT8152_INTC_PDCNIRR
);
110 bits_lp
= __raw_readl(IT8152_INTC_LPCNIRR
);
111 bits_ld
= __raw_readl(IT8152_INTC_LDCNIRR
);
114 __raw_writel((~bits_pd
), IT8152_INTC_PDCNIRR
);
115 __raw_writel((~bits_lp
), IT8152_INTC_LPCNIRR
);
116 __raw_writel((~bits_ld
), IT8152_INTC_LDCNIRR
);
118 if (!(bits_ld
| bits_lp
| bits_pd
)) {
119 /* Re-read to guarantee, that there was a moment of
120 time, when they all three were 0. */
121 bits_pd
= __raw_readl(IT8152_INTC_PDCNIRR
);
122 bits_lp
= __raw_readl(IT8152_INTC_LPCNIRR
);
123 if (!(bits_ld
| bits_lp
| bits_pd
))
127 bits_pd
&= ((1 << IT8152_PD_IRQ_COUNT
) - 1);
130 it8152_irq(IT8152_PD_IRQ(i
));
131 bits_pd
&= ~(1 << i
);
134 bits_lp
&= ((1 << IT8152_LP_IRQ_COUNT
) - 1);
137 it8152_irq(IT8152_LP_IRQ(i
));
138 bits_lp
&= ~(1 << i
);
141 bits_ld
&= ((1 << IT8152_LD_IRQ_COUNT
) - 1);
144 it8152_irq(IT8152_LD_IRQ(i
));
145 bits_ld
&= ~(1 << i
);
150 /* mapping for on-chip devices */
151 int __init
it8152_pci_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
153 if ((dev
->vendor
== PCI_VENDOR_ID_ITE
) &&
154 (dev
->device
== PCI_DEVICE_ID_ITE_8152
)) {
155 if ((dev
->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO
)
156 return IT8152_AUDIO_INT
;
157 if ((dev
->class >> 8) == PCI_CLASS_SERIAL_USB
)
158 return IT8152_USB_INT
;
159 if ((dev
->class >> 8) == PCI_CLASS_SYSTEM_DMA
)
160 return IT8152_CDMA_INT
;
166 static unsigned long it8152_pci_dev_base_address(struct pci_bus
*bus
,
169 unsigned long addr
= 0;
171 if (bus
->number
== 0) {
172 if (devfn
< PCI_DEVFN(MAX_SLOTS
, 0))
175 addr
= (bus
->number
<< 16) | (devfn
<< 8);
180 static int it8152_pci_read_config(struct pci_bus
*bus
,
181 unsigned int devfn
, int where
,
182 int size
, u32
*value
)
184 unsigned long addr
= it8152_pci_dev_base_address(bus
, devfn
);
190 __raw_writel((addr
+ where
), IT8152_PCI_CFG_ADDR
);
191 v
= (__raw_readl(IT8152_PCI_CFG_DATA
) >> (8 * (shift
)));
195 return PCIBIOS_SUCCESSFUL
;
198 static int it8152_pci_write_config(struct pci_bus
*bus
,
199 unsigned int devfn
, int where
,
202 unsigned long addr
= it8152_pci_dev_base_address(bus
, devfn
);
203 u32 v
, vtemp
, mask
= 0;
213 __raw_writel((addr
+ where
), IT8152_PCI_CFG_ADDR
);
214 vtemp
= __raw_readl(IT8152_PCI_CFG_DATA
);
217 vtemp
&= ~(mask
<< (8 * shift
));
221 v
= (value
<< (8 * shift
));
222 __raw_writel((addr
+ where
), IT8152_PCI_CFG_ADDR
);
223 __raw_writel((v
| vtemp
), IT8152_PCI_CFG_DATA
);
225 return PCIBIOS_SUCCESSFUL
;
228 static struct pci_ops it8152_ops
= {
229 .read
= it8152_pci_read_config
,
230 .write
= it8152_pci_write_config
,
233 static struct resource it8152_io
= {
234 .name
= "IT8152 PCI I/O region",
235 .flags
= IORESOURCE_IO
,
238 static struct resource it8152_mem
= {
239 .name
= "IT8152 PCI memory region",
242 .flags
= IORESOURCE_MEM
,
246 * The following functions are needed for DMA bouncing.
247 * ITE8152 chip can addrees up to 64MByte, so all the devices
248 * connected to ITE8152 (PCI and USB) should have limited DMA window
252 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
255 static int it8152_pci_platform_notify(struct device
*dev
)
257 if (dev
->bus
== &pci_bus_type
) {
259 *dev
->dma_mask
= (SZ_64M
- 1) | PHYS_OFFSET
;
260 dev
->coherent_dma_mask
= (SZ_64M
- 1) | PHYS_OFFSET
;
261 dmabounce_register_dev(dev
, 2048, 4096);
266 static int it8152_pci_platform_notify_remove(struct device
*dev
)
268 if (dev
->bus
== &pci_bus_type
)
269 dmabounce_unregister_dev(dev
);
274 int dma_needs_bounce(struct device
*dev
, dma_addr_t dma_addr
, size_t size
)
276 dev_dbg(dev
, "%s: dma_addr %08x, size %08x\n",
277 __func__
, dma_addr
, size
);
278 return (dev
->bus
== &pci_bus_type
) &&
279 ((dma_addr
+ size
- PHYS_OFFSET
) >= SZ_64M
);
283 * We override these so we properly do dmabounce otherwise drivers
284 * are able to set the dma_mask to 0xffffffff and we can no longer
287 * We just return true on everyhing except for < 64MB in which case
288 * we will fail miseralby and die since we can't handle that case.
290 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
292 dev_dbg(&dev
->dev
, "%s: %llx\n", __func__
, mask
);
293 if (mask
>= PHYS_OFFSET
+ SZ_64M
- 1)
300 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
302 dev_dbg(&dev
->dev
, "%s: %llx\n", __func__
, mask
);
303 if (mask
>= PHYS_OFFSET
+ SZ_64M
- 1)
309 int __init
it8152_pci_setup(int nr
, struct pci_sys_data
*sys
)
311 it8152_io
.start
= IT8152_IO_BASE
+ 0x12000;
312 it8152_io
.end
= IT8152_IO_BASE
+ 0x12000 + 0x100000;
314 sys
->mem_offset
= 0x10000000;
315 sys
->io_offset
= IT8152_IO_BASE
;
317 if (request_resource(&ioport_resource
, &it8152_io
)) {
318 printk(KERN_ERR
"PCI: unable to allocate IO region\n");
321 if (request_resource(&iomem_resource
, &it8152_mem
)) {
322 printk(KERN_ERR
"PCI: unable to allocate memory region\n");
326 sys
->resource
[0] = &it8152_io
;
327 sys
->resource
[1] = &it8152_mem
;
329 if (platform_notify
|| platform_notify_remove
) {
330 printk(KERN_ERR
"PCI: Can't use platform_notify\n");
334 platform_notify
= it8152_pci_platform_notify
;
335 platform_notify_remove
= it8152_pci_platform_notify_remove
;
340 release_resource(&it8152_io
);
342 release_resource(&it8152_mem
);
348 * If we set up a device for bus mastering, we need to check the latency
349 * timer as we don't have even crappy BIOSes to set it properly.
350 * The implementation is from arch/i386/pci/i386.c
352 unsigned int pcibios_max_latency
= 255;
354 void pcibios_set_master(struct pci_dev
*dev
)
358 /* no need to update on-chip OHCI controller */
359 if ((dev
->vendor
== PCI_VENDOR_ID_ITE
) &&
360 (dev
->device
== PCI_DEVICE_ID_ITE_8152
) &&
361 ((dev
->class >> 8) == PCI_CLASS_SERIAL_USB
))
364 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
366 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
367 else if (lat
> pcibios_max_latency
)
368 lat
= pcibios_max_latency
;
371 printk(KERN_DEBUG
"PCI: Setting latency timer of device %s to %d\n",
373 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
377 struct pci_bus
* __init
it8152_pci_scan_bus(int nr
, struct pci_sys_data
*sys
)
379 return pci_scan_bus(nr
, &it8152_ops
, sys
);