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avoid endless loops in lib/swiotlb.c
[wrt350n-kernel.git] / arch / arm / mach-omap2 / gpmc.c
blob5a4cc2076a7d4cf23c13d97e61f8bb5306b0b2e7
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/err.h>
15 #include <linux/clk.h>
16 #include <linux/ioport.h>
17 #include <linux/spinlock.h>
18
19 #include <asm/io.h>
20 #include <asm/mach-types.h>
21 #include <asm/arch/gpmc.h>
22
23 #undef DEBUG
24
25 #ifdef CONFIG_ARCH_OMAP2420
26 #define GPMC_BASE 0x6800a000
27 #endif
28
29 #ifdef CONFIG_ARCH_OMAP2430
30 #define GPMC_BASE 0x6E000000
31 #endif
32
33 #define GPMC_REVISION 0x00
34 #define GPMC_SYSCONFIG 0x10
35 #define GPMC_SYSSTATUS 0x14
36 #define GPMC_IRQSTATUS 0x18
37 #define GPMC_IRQENABLE 0x1c
38 #define GPMC_TIMEOUT_CONTROL 0x40
39 #define GPMC_ERR_ADDRESS 0x44
40 #define GPMC_ERR_TYPE 0x48
41 #define GPMC_CONFIG 0x50
42 #define GPMC_STATUS 0x54
43 #define GPMC_PREFETCH_CONFIG1 0x1e0
44 #define GPMC_PREFETCH_CONFIG2 0x1e4
45 #define GPMC_PREFETCH_CONTROL 0x1e8
46 #define GPMC_PREFETCH_STATUS 0x1f0
47 #define GPMC_ECC_CONFIG 0x1f4
48 #define GPMC_ECC_CONTROL 0x1f8
49 #define GPMC_ECC_SIZE_CONFIG 0x1fc
50
51 #define GPMC_CS0 0x60
52 #define GPMC_CS_SIZE 0x30
53
54 #define GPMC_CS_NUM 8
55 #define GPMC_MEM_START 0x00000000
56 #define GPMC_MEM_END 0x3FFFFFFF
57 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
58
59 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
60 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
61
62 static struct resource gpmc_mem_root;
63 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64 static DEFINE_SPINLOCK(gpmc_mem_lock);
65 static unsigned gpmc_cs_map;
66
67 static void __iomem *gpmc_base =
68 (void __iomem *) IO_ADDRESS(GPMC_BASE);
69 static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71
72 static struct clk *gpmc_l3_clk;
73
74 static void gpmc_write_reg(int idx, u32 val)
75 {
76 __raw_writel(val, gpmc_base + idx);
77 }
78
79 static u32 gpmc_read_reg(int idx)
80 {
81 return __raw_readl(gpmc_base + idx);
82 }
83
84 void gpmc_cs_write_reg(int cs, int idx, u32 val)
85 {
86 void __iomem *reg_addr;
87
88 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
89 __raw_writel(val, reg_addr);
90 }
91
92 u32 gpmc_cs_read_reg(int cs, int idx)
93 {
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95 }
96
97 /* TODO: Add support for gpmc_fck to clock framework and use it */
98 unsigned long gpmc_get_fclk_period(void)
99 {
100 /* In picoseconds */
101 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000);
102 }
103
104 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
105 {
106 unsigned long tick_ps;
107
108 /* Calculate in picosecs to yield more exact results */
109 tick_ps = gpmc_get_fclk_period();
110
111 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
112 }
113
114 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
115 {
116 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
117
118 return ticks * gpmc_get_fclk_period() / 1000;
119 }
120
121 #ifdef DEBUG
122 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
123 int time, const char *name)
124 #else
125 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
126 int time)
127 #endif
128 {
129 u32 l;
130 int ticks, mask, nr_bits;
131
132 if (time == 0)
133 ticks = 0;
134 else
135 ticks = gpmc_ns_to_ticks(time);
136 nr_bits = end_bit - st_bit + 1;
137 if (ticks >= 1 << nr_bits) {
138 #ifdef DEBUG
139 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
140 cs, name, time, ticks, 1 << nr_bits);
141 #endif
142 return -1;
143 }
144
145 mask = (1 << nr_bits) - 1;
146 l = gpmc_cs_read_reg(cs, reg);
147 #ifdef DEBUG
148 printk(KERN_INFO
149 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
150 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
151 (l >> st_bit) & mask, time);
152 #endif
153 l &= ~(mask << st_bit);
154 l |= ticks << st_bit;
155 gpmc_cs_write_reg(cs, reg, l);
156
157 return 0;
158 }
159
160 #ifdef DEBUG
161 #define GPMC_SET_ONE(reg, st, end, field) \
162 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
163 t->field, #field) < 0) \
164 return -1
165 #else
166 #define GPMC_SET_ONE(reg, st, end, field) \
167 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
168 return -1
169 #endif
170
171 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
172 {
173 int div;
174 u32 l;
175
176 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
177 div = l / gpmc_get_fclk_period();
178 if (div > 4)
179 return -1;
180 if (div <= 0)
181 div = 1;
182
183 return div;
184 }
185
186 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
187 {
188 int div;
189 u32 l;
190
191 div = gpmc_cs_calc_divider(cs, t->sync_clk);
192 if (div < 0)
193 return -1;
194
195 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
196 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
197 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
198
199 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
200 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
201 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
202
203 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
204 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
205 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
206 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
207
208 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
209 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
210 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
211
212 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
213
214 /* caller is expected to have initialized CONFIG1 to cover
215 * at least sync vs async
216 */
217 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
218 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
219 #ifdef DEBUG
220 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
221 cs, (div * gpmc_get_fclk_period()) / 1000, div);
222 #endif
223 l &= ~0x03;
224 l |= (div - 1);
225 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
226 }
227
228 return 0;
229 }
230
231 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
232 {
233 u32 l;
234 u32 mask;
235
236 mask = (1 << GPMC_SECTION_SHIFT) - size;
237 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
238 l &= ~0x3f;
239 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
240 l &= ~(0x0f << 8);
241 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
242 l |= 1 << 6; /* CSVALID */
243 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
244 }
245
246 static void gpmc_cs_disable_mem(int cs)
247 {
248 u32 l;
249
250 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
251 l &= ~(1 << 6); /* CSVALID */
252 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
253 }
254
255 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
256 {
257 u32 l;
258 u32 mask;
259
260 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
261 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
262 mask = (l >> 8) & 0x0f;
263 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
264 }
265
266 static int gpmc_cs_mem_enabled(int cs)
267 {
268 u32 l;
269
270 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
271 return l & (1 << 6);
272 }
273
274 int gpmc_cs_set_reserved(int cs, int reserved)
275 {
276 if (cs > GPMC_CS_NUM)
277 return -ENODEV;
278
279 gpmc_cs_map &= ~(1 << cs);
280 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
281
282 return 0;
283 }
284
285 int gpmc_cs_reserved(int cs)
286 {
287 if (cs > GPMC_CS_NUM)
288 return -ENODEV;
289
290 return gpmc_cs_map & (1 << cs);
291 }
292
293 static unsigned long gpmc_mem_align(unsigned long size)
294 {
295 int order;
296
297 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
298 order = GPMC_CHUNK_SHIFT - 1;
299 do {
300 size >>= 1;
301 order++;
302 } while (size);
303 size = 1 << order;
304 return size;
305 }
306
307 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
308 {
309 struct resource *res = &gpmc_cs_mem[cs];
310 int r;
311
312 size = gpmc_mem_align(size);
313 spin_lock(&gpmc_mem_lock);
314 res->start = base;
315 res->end = base + size - 1;
316 r = request_resource(&gpmc_mem_root, res);
317 spin_unlock(&gpmc_mem_lock);
318
319 return r;
320 }
321
322 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
323 {
324 struct resource *res = &gpmc_cs_mem[cs];
325 int r = -1;
326
327 if (cs > GPMC_CS_NUM)
328 return -ENODEV;
329
330 size = gpmc_mem_align(size);
331 if (size > (1 << GPMC_SECTION_SHIFT))
332 return -ENOMEM;
333
334 spin_lock(&gpmc_mem_lock);
335 if (gpmc_cs_reserved(cs)) {
336 r = -EBUSY;
337 goto out;
338 }
339 if (gpmc_cs_mem_enabled(cs))
340 r = adjust_resource(res, res->start & ~(size - 1), size);
341 if (r < 0)
342 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
343 size, NULL, NULL);
344 if (r < 0)
345 goto out;
346
347 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
348 *base = res->start;
349 gpmc_cs_set_reserved(cs, 1);
350 out:
351 spin_unlock(&gpmc_mem_lock);
352 return r;
353 }
354
355 void gpmc_cs_free(int cs)
356 {
357 spin_lock(&gpmc_mem_lock);
358 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
359 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
360 BUG();
361 spin_unlock(&gpmc_mem_lock);
362 return;
363 }
364 gpmc_cs_disable_mem(cs);
365 release_resource(&gpmc_cs_mem[cs]);
366 gpmc_cs_set_reserved(cs, 0);
367 spin_unlock(&gpmc_mem_lock);
368 }
369
370 void __init gpmc_mem_init(void)
371 {
372 int cs;
373 unsigned long boot_rom_space = 0;
374
375 /* never allocate the first page, to facilitate bug detection;
376 * even if we didn't boot from ROM.
377 */
378 boot_rom_space = BOOT_ROM_SPACE;
379 /* In apollon the CS0 is mapped as 0x0000 0000 */
380 if (machine_is_omap_apollon())
381 boot_rom_space = 0;
382 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
383 gpmc_mem_root.end = GPMC_MEM_END;
384
385 /* Reserve all regions that has been set up by bootloader */
386 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
387 u32 base, size;
388
389 if (!gpmc_cs_mem_enabled(cs))
390 continue;
391 gpmc_cs_get_memconf(cs, &base, &size);
392 if (gpmc_cs_insert_mem(cs, base, size) < 0)
393 BUG();
394 }
395 }
396
397 void __init gpmc_init(void)
398 {
399 u32 l;
400
401 gpmc_l3_clk = clk_get(NULL, "core_l3_ck");
402 BUG_ON(IS_ERR(gpmc_l3_clk));
403
404 l = gpmc_read_reg(GPMC_REVISION);
405 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
406 /* Set smart idle mode and automatic L3 clock gating */
407 l = gpmc_read_reg(GPMC_SYSCONFIG);
408 l &= 0x03 << 3;
409 l |= (0x02 << 3) | (1 << 0);
410 gpmc_write_reg(GPMC_SYSCONFIG, l);
411
412 gpmc_mem_init();
413 }
WRT350N Kernel Patches