| blob | 76348f060f27473b71c71de0086ff70cf6ad26d7 |
1 comment "Processor Type"
3 config CPU_32
4 bool
5 default y
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
9 # optimiser behaviour.
11 # ARM610
12 config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
18 select CPU_CP15_MMU
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
21 help
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
26 Otherwise, say N.
28 # ARM7TDMI
29 config CPU_ARM7TDMI
30 bool "Support ARM7TDMI processor"
31 depends on !MMU
32 select CPU_32v4T
33 select CPU_ABRT_LV4T
34 select CPU_CACHE_V4
35 help
36 A 32-bit RISC microprocessor based on the ARM7 processor core
37 which has no memory control unit and cache.
39 Say Y if you want support for the ARM7TDMI processor.
40 Otherwise, say N.
42 # ARM710
43 config CPU_ARM710
44 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
45 default y if ARCH_CLPS7500
46 select CPU_32v3
47 select CPU_CACHE_V3
48 select CPU_CACHE_VIVT
49 select CPU_CP15_MMU
50 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU
52 help
53 A 32-bit RISC microprocessor based on the ARM7 processor core
54 designed by Advanced RISC Machines Ltd. The ARM710 is the
55 successor to the ARM610 processor. It was released in
56 July 1994 by VLSI Technology Inc.
58 Say Y if you want support for the ARM710 processor.
59 Otherwise, say N.
61 # ARM720T
62 config CPU_ARM720T
63 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
64 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
65 select CPU_32v4T
66 select CPU_ABRT_LV4T
67 select CPU_CACHE_V4
68 select CPU_CACHE_VIVT
69 select CPU_CP15_MMU
70 select CPU_COPY_V4WT if MMU
71 select CPU_TLB_V4WT if MMU
72 help
73 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
74 MMU built around an ARM7TDMI core.
76 Say Y if you want support for the ARM720T processor.
77 Otherwise, say N.
79 # ARM740T
80 config CPU_ARM740T
81 bool "Support ARM740T processor" if ARCH_INTEGRATOR
82 depends on !MMU
83 select CPU_32v4T
84 select CPU_ABRT_LV4T
85 select CPU_CACHE_V3 # although the core is v4t
86 select CPU_CP15_MPU
87 help
88 A 32-bit RISC processor with 8KB cache or 4KB variants,
89 write buffer and MPU(Protection Unit) built around
90 an ARM7TDMI core.
92 Say Y if you want support for the ARM740T processor.
93 Otherwise, say N.
95 # ARM9TDMI
96 config CPU_ARM9TDMI
97 bool "Support ARM9TDMI processor"
98 depends on !MMU
99 select CPU_32v4T
100 select CPU_ABRT_NOMMU
101 select CPU_CACHE_V4
102 help
103 A 32-bit RISC microprocessor based on the ARM9 processor core
104 which has no memory control unit and cache.
106 Say Y if you want support for the ARM9TDMI processor.
107 Otherwise, say N.
109 # ARM920T
110 config CPU_ARM920T
111 bool "Support ARM920T processor"
112 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
113 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
114 select CPU_32v4T
115 select CPU_ABRT_EV4T
116 select CPU_CACHE_V4WT
117 select CPU_CACHE_VIVT
118 select CPU_CP15_MMU
119 select CPU_COPY_V4WB if MMU
120 select CPU_TLB_V4WBI if MMU
121 help
122 The ARM920T is licensed to be produced by numerous vendors,
123 and is used in the Maverick EP9312 and the Samsung S3C2410.
125 More information on the Maverick EP9312 at
126 <http://linuxdevices.com/products/PD2382866068.html>.
128 Say Y if you want support for the ARM920T processor.
129 Otherwise, say N.
131 # ARM922T
132 config CPU_ARM922T
133 bool "Support ARM922T processor" if ARCH_INTEGRATOR
134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
135 default y if ARCH_LH7A40X || ARCH_KS8695
136 select CPU_32v4T
137 select CPU_ABRT_EV4T
138 select CPU_CACHE_V4WT
139 select CPU_CACHE_VIVT
140 select CPU_CP15_MMU
141 select CPU_COPY_V4WB if MMU
142 select CPU_TLB_V4WBI if MMU
143 help
144 The ARM922T is a version of the ARM920T, but with smaller
145 instruction and data caches. It is used in Altera's
146 Excalibur XA device family and Micrel's KS8695 Centaur.
148 Say Y if you want support for the ARM922T processor.
149 Otherwise, say N.
151 # ARM925T
152 config CPU_ARM925T
153 bool "Support ARM925T processor" if ARCH_OMAP1
154 depends on ARCH_OMAP15XX
155 default y if ARCH_OMAP15XX
156 select CPU_32v4T
157 select CPU_ABRT_EV4T
158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT
160 select CPU_CP15_MMU
161 select CPU_COPY_V4WB if MMU
162 select CPU_TLB_V4WBI if MMU
163 help
164 The ARM925T is a mix between the ARM920T and ARM926T, but with
165 different instruction and data caches. It is used in TI's OMAP
166 device family.
168 Say Y if you want support for the ARM925T processor.
169 Otherwise, say N.
171 # ARM926T
172 config CPU_ARM926T
173 bool "Support ARM926T processor"
174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
176 select CPU_32v5
177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT
179 select CPU_CP15_MMU
180 select CPU_COPY_V4WB if MMU
181 select CPU_TLB_V4WBI if MMU
182 help
183 This is a variant of the ARM920. It has slightly different
184 instruction sequences for cache and TLB operations. Curiously,
185 there is no documentation on it at the ARM corporate website.
187 Say Y if you want support for the ARM926T processor.
188 Otherwise, say N.
190 # ARM940T
191 config CPU_ARM940T
192 bool "Support ARM940T processor" if ARCH_INTEGRATOR
193 depends on !MMU
194 select CPU_32v4T
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 help
199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and separate 4KB
201 instruction and 4KB data cases, each with a 4-word line
202 length.
204 Say Y if you want support for the ARM940T processor.
205 Otherwise, say N.
207 # ARM946E-S
208 config CPU_ARM946E
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
210 depends on !MMU
211 select CPU_32v5
212 select CPU_ABRT_NOMMU
213 select CPU_CACHE_VIVT
214 select CPU_CP15_MPU
215 help
216 ARM946E-S is a member of the ARM9E-S family of high-
217 performance, 32-bit system-on-chip processor solutions.
218 The TCM and ARMv5TE 32-bit instruction set is supported.
220 Say Y if you want support for the ARM946E-S processor.
221 Otherwise, say N.
223 # ARM1020 - needs validating
224 config CPU_ARM1020
225 bool "Support ARM1020T (rev 0) processor"
226 depends on ARCH_INTEGRATOR
227 select CPU_32v5
228 select CPU_ABRT_EV4T
229 select CPU_CACHE_V4WT
230 select CPU_CACHE_VIVT
231 select CPU_CP15_MMU
232 select CPU_COPY_V4WB if MMU
233 select CPU_TLB_V4WBI if MMU
234 help
235 The ARM1020 is the 32K cached version of the ARM10 processor,
236 with an addition of a floating-point unit.
238 Say Y if you want support for the ARM1020 processor.
239 Otherwise, say N.
241 # ARM1020E - needs validating
242 config CPU_ARM1020E
243 bool "Support ARM1020E processor"
244 depends on ARCH_INTEGRATOR
245 select CPU_32v5
246 select CPU_ABRT_EV4T
247 select CPU_CACHE_V4WT
248 select CPU_CACHE_VIVT
249 select CPU_CP15_MMU
250 select CPU_COPY_V4WB if MMU
251 select CPU_TLB_V4WBI if MMU
252 depends on n
254 # ARM1022E
255 config CPU_ARM1022
256 bool "Support ARM1022E processor"
257 depends on ARCH_INTEGRATOR
258 select CPU_32v5
259 select CPU_ABRT_EV4T
260 select CPU_CACHE_VIVT
261 select CPU_CP15_MMU
262 select CPU_COPY_V4WB if MMU # can probably do better
263 select CPU_TLB_V4WBI if MMU
264 help
265 The ARM1022E is an implementation of the ARMv5TE architecture
266 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
267 embedded trace macrocell, and a floating-point unit.
269 Say Y if you want support for the ARM1022E processor.
270 Otherwise, say N.
272 # ARM1026EJ-S
273 config CPU_ARM1026
274 bool "Support ARM1026EJ-S processor"
275 depends on ARCH_INTEGRATOR
276 select CPU_32v5
277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
278 select CPU_CACHE_VIVT
279 select CPU_CP15_MMU
280 select CPU_COPY_V4WB if MMU # can probably do better
281 select CPU_TLB_V4WBI if MMU
282 help
283 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
284 based upon the ARM10 integer core.
286 Say Y if you want support for the ARM1026EJ-S processor.
287 Otherwise, say N.
289 # SA110
290 config CPU_SA110
291 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
292 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
293 select CPU_32v3 if ARCH_RPC
294 select CPU_32v4 if !ARCH_RPC
295 select CPU_ABRT_EV4
296 select CPU_CACHE_V4WB
297 select CPU_CACHE_VIVT
298 select CPU_CP15_MMU
299 select CPU_COPY_V4WB if MMU
300 select CPU_TLB_V4WB if MMU
301 help
302 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
303 is available at five speeds ranging from 100 MHz to 233 MHz.
304 More information is available at
305 <http://developer.intel.com/design/strong/sa110.htm>.
307 Say Y if you want support for the SA-110 processor.
308 Otherwise, say N.
310 # SA1100
311 config CPU_SA1100
312 bool
313 depends on ARCH_SA1100
314 default y
315 select CPU_32v4
316 select CPU_ABRT_EV4
317 select CPU_CACHE_V4WB
318 select CPU_CACHE_VIVT
319 select CPU_CP15_MMU
320 select CPU_TLB_V4WB if MMU
322 # XScale
323 config CPU_XSCALE
324 bool
325 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
326 default y
327 select CPU_32v5
328 select CPU_ABRT_EV5T
329 select CPU_CACHE_VIVT
330 select CPU_CP15_MMU
331 select CPU_TLB_V4WBI if MMU
333 # XScale Core Version 3
334 config CPU_XSC3
335 bool
336 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
337 default y
338 select CPU_32v5
339 select CPU_ABRT_EV5T
340 select CPU_CACHE_VIVT
341 select CPU_CP15_MMU
342 select CPU_TLB_V4WBI if MMU
343 select IO_36
345 # Feroceon
346 config CPU_FEROCEON
347 bool
348 depends on ARCH_ORION
349 default y
350 select CPU_32v5
351 select CPU_ABRT_EV5T
352 select CPU_CACHE_VIVT
353 select CPU_CP15_MMU
354 select CPU_COPY_V4WB if MMU
355 select CPU_TLB_V4WBI if MMU
357 config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
366 # ARMv6
367 config CPU_V6
368 bool "Support ARM V6 processor"
369 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A
370 default y if ARCH_MX3
371 default y if ARCH_MSM7X00A
372 select CPU_32v6
373 select CPU_ABRT_EV6
374 select CPU_CACHE_V6
375 select CPU_CACHE_VIPT
376 select CPU_CP15_MMU
377 select CPU_HAS_ASID if MMU
378 select CPU_COPY_V6 if MMU
379 select CPU_TLB_V6 if MMU
381 # ARMv6k
382 config CPU_32v6K
383 bool "Support ARM V6K processor extensions" if !SMP
384 depends on CPU_V6
385 default y if SMP && !ARCH_MX3
386 help
387 Say Y here if your ARMv6 processor supports the 'K' extension.
388 This enables the kernel to use some instructions not present
389 on previous processors, and as such a kernel build with this
390 enabled will not boot on processors with do not support these
391 instructions.
393 # ARMv7
394 config CPU_V7
395 bool "Support ARM V7 processor"
396 depends on ARCH_INTEGRATOR
397 select CPU_32v6K
398 select CPU_32v7
399 select CPU_ABRT_EV7
400 select CPU_CACHE_V7
401 select CPU_CACHE_VIPT
402 select CPU_CP15_MMU
403 select CPU_HAS_ASID if MMU
404 select CPU_COPY_V6 if MMU
405 select CPU_TLB_V7 if MMU
407 # Figure out what processor architecture version we should be using.
408 # This defines the compiler instruction set which depends on the machine type.
409 config CPU_32v3
410 bool
411 select TLS_REG_EMUL if SMP || !MMU
412 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
414 config CPU_32v4
415 bool
416 select TLS_REG_EMUL if SMP || !MMU
417 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
419 config CPU_32v4T
420 bool
421 select TLS_REG_EMUL if SMP || !MMU
422 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
424 config CPU_32v5
425 bool
426 select TLS_REG_EMUL if SMP || !MMU
427 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
429 config CPU_32v6
430 bool
431 select TLS_REG_EMUL if !CPU_32v6K && !MMU
433 config CPU_32v7
434 bool
436 # The abort model
437 config CPU_ABRT_NOMMU
438 bool
440 config CPU_ABRT_EV4
441 bool
443 config CPU_ABRT_EV4T
444 bool
446 config CPU_ABRT_LV4T
447 bool
449 config CPU_ABRT_EV5T
450 bool
452 config CPU_ABRT_EV5TJ
453 bool
455 config CPU_ABRT_EV6
456 bool
458 config CPU_ABRT_EV7
459 bool
461 # The cache model
462 config CPU_CACHE_V3
463 bool
465 config CPU_CACHE_V4
466 bool
468 config CPU_CACHE_V4WT
469 bool
471 config CPU_CACHE_V4WB
472 bool
474 config CPU_CACHE_V6
475 bool
477 config CPU_CACHE_V7
478 bool
480 config CPU_CACHE_VIVT
481 bool
483 config CPU_CACHE_VIPT
484 bool
486 if MMU
487 # The copy-page model
488 config CPU_COPY_V3
489 bool
491 config CPU_COPY_V4WT
492 bool
494 config CPU_COPY_V4WB
495 bool
497 config CPU_COPY_V6
498 bool
500 # This selects the TLB model
501 config CPU_TLB_V3
502 bool
503 help
504 ARM Architecture Version 3 TLB.
506 config CPU_TLB_V4WT
507 bool
508 help
509 ARM Architecture Version 4 TLB with writethrough cache.
511 config CPU_TLB_V4WB
512 bool
513 help
514 ARM Architecture Version 4 TLB with writeback cache.
516 config CPU_TLB_V4WBI
517 bool
518 help
519 ARM Architecture Version 4 TLB with writeback cache and invalidate
520 instruction cache entry.
522 config CPU_TLB_V6
523 bool
525 config CPU_TLB_V7
526 bool
528 endif
530 config CPU_HAS_ASID
531 bool
532 help
533 This indicates whether the CPU has the ASID register; used to
534 tag TLB and possibly cache entries.
536 config CPU_CP15
537 bool
538 help
539 Processor has the CP15 register.
541 config CPU_CP15_MMU
542 bool
543 select CPU_CP15
544 help
545 Processor has the CP15 register, which has MMU related registers.
547 config CPU_CP15_MPU
548 bool
549 select CPU_CP15
550 help
551 Processor has the CP15 register, which has MPU related registers.
553 #
554 # CPU supports 36-bit I/O
555 #
556 config IO_36
557 bool
559 comment "Processor Features"
561 config ARM_THUMB
562 bool "Support Thumb user binaries"
563 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
564 default y
565 help
566 Say Y if you want to include kernel support for running user space
567 Thumb binaries.
569 The Thumb instruction set is a compressed form of the standard ARM
570 instruction set resulting in smaller binaries at the expense of
571 slightly less efficient code.
573 If you don't know what this all is, saying Y is a safe choice.
575 config CPU_BIG_ENDIAN
576 bool "Build big-endian kernel"
577 depends on ARCH_SUPPORTS_BIG_ENDIAN
578 help
579 Say Y if you plan on running a kernel in big-endian mode.
580 Note that your board must be properly built and your board
581 port must properly enable any big-endian related features
582 of your chipset/board/processor.
584 config CPU_HIGH_VECTOR
585 depends on !MMU && CPU_CP15 && !CPU_ARM740T
586 bool "Select the High exception vector"
587 default n
588 help
589 Say Y here to select high exception vector(0xFFFF0000~).
590 The exception vector can be vary depending on the platform
591 design in nommu mode. If your platform needs to select
592 high exception vector, say Y.
593 Otherwise or if you are unsure, say N, and the low exception
594 vector (0x00000000~) will be used.
596 config CPU_ICACHE_DISABLE
597 bool "Disable I-Cache (I-bit)"
598 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
599 help
600 Say Y here to disable the processor instruction cache. Unless
601 you have a reason not to or are unsure, say N.
603 config CPU_DCACHE_DISABLE
604 bool "Disable D-Cache (C-bit)"
605 depends on CPU_CP15
606 help
607 Say Y here to disable the processor data cache. Unless
608 you have a reason not to or are unsure, say N.
610 config CPU_DCACHE_SIZE
611 hex
612 depends on CPU_ARM740T || CPU_ARM946E
613 default 0x00001000 if CPU_ARM740T
614 default 0x00002000 # default size for ARM946E-S
615 help
616 Some cores are synthesizable to have various sized cache. For
617 ARM946E-S case, it can vary from 0KB to 1MB.
618 To support such cache operations, it is efficient to know the size
619 before compile time.
620 If your SoC is configured to have a different size, define the value
621 here with proper conditions.
623 config CPU_DCACHE_WRITETHROUGH
624 bool "Force write through D-cache"
625 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
626 default y if CPU_ARM925T
627 help
628 Say Y here to use the data cache in writethrough mode. Unless you
629 specifically require this or are unsure, say N.
631 config CPU_CACHE_ROUND_ROBIN
632 bool "Round robin I and D cache replacement algorithm"
633 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
634 help
635 Say Y here to use the predictable round-robin cache replacement
636 policy. Unless you specifically require this or are unsure, say N.
638 config CPU_BPREDICT_DISABLE
639 bool "Disable branch prediction"
640 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
641 help
642 Say Y here to disable branch prediction. If unsure, say N.
644 config TLS_REG_EMUL
645 bool
646 help
647 An SMP system using a pre-ARMv6 processor (there are apparently
648 a few prototypes like that in existence) and therefore access to
649 that required register must be emulated.
651 config HAS_TLS_REG
652 bool
653 depends on !TLS_REG_EMUL
654 default y if SMP || CPU_32v7
655 help
656 This selects support for the CP15 thread register.
657 It is defined to be available on some ARMv6 processors (including
658 all SMP capable ARMv6's) or later processors. User space may
659 assume directly accessing that register and always obtain the
660 expected value only on ARMv7 and above.
662 config NEEDS_SYSCALL_FOR_CMPXCHG
663 bool
664 help
665 SMP on a pre-ARMv6 processor? Well OK then.
666 Forget about fast user space cmpxchg support.
667 It is just not possible.
669 config OUTER_CACHE
670 bool
671 default n
673 config CACHE_L2X0
674 bool
675 select OUTER_CACHE