arch/parisc/kernel/irq.c

   1 /*
   2  * Code to handle x86 style IRQs plus some generic interrupt stuff.
   3  *
   4  * Copyright (C) 1992 Linus Torvalds
   5  * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle
   6  * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
   7  * Copyright (C) 1999-2000 Grant Grundler
   8  * Copyright (c) 2005 Matthew Wilcox
   9  *
  10  *    This program is free software; you can redistribute it and/or modify
  11  *    it under the terms of the GNU General Public License as published by
  12  *    the Free Software Foundation; either version 2, or (at your option)
  13  *    any later version.
  14  *
  15  *    This program is distributed in the hope that it will be useful,
  16  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *    GNU General Public License for more details.
  19  *
  20  *    You should have received a copy of the GNU General Public License
  21  *    along with this program; if not, write to the Free Software
  22  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24 #include <linux/bitops.h>
  25 #include <linux/errno.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/kernel_stat.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/types.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/smp.h>
  35
  36 #undef PARISC_IRQ_CR16_COUNTS
  37
  38 extern irqreturn_t timer_interrupt(int, void *);
  39 extern irqreturn_t ipi_interrupt(int, void *);
  40
  41 #define EIEM_MASK(irq)       (1UL<<(CPU_IRQ_MAX - irq))
  42
  43 /* Bits in EIEM correlate with cpu_irq_action[].
  44 ** Numbered *Big Endian*! (ie bit 0 is MSB)
  45 */
  46 static volatile unsigned long cpu_eiem = 0;
  47
  48 /*
  49 ** local ACK bitmap ... habitually set to 1, but reset to zero
  50 ** between ->ack() and ->end() of the interrupt to prevent
  51 ** re-interruption of a processing interrupt.
  52 */
  53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL;
  54
  55 static void cpu_disable_irq(unsigned int irq)
  56 {
  57         unsigned long eirr_bit = EIEM_MASK(irq);
  58
  59         cpu_eiem &= ~eirr_bit;
  60         /* Do nothing on the other CPUs.  If they get this interrupt,
  61          * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't
  62          * handle it, and the set_eiem() at the bottom will ensure it
  63          * then gets disabled */
  64 }
  65
  66 static void cpu_enable_irq(unsigned int irq)
  67 {
  68         unsigned long eirr_bit = EIEM_MASK(irq);
  69
  70         cpu_eiem |= eirr_bit;
  71
  72         /* This is just a simple NOP IPI.  But what it does is cause
  73          * all the other CPUs to do a set_eiem(cpu_eiem) at the end
  74          * of the interrupt handler */
  75         smp_send_all_nop();
  76 }
  77
  78 static unsigned int cpu_startup_irq(unsigned int irq)
  79 {
  80         cpu_enable_irq(irq);
  81         return 0;
  82 }
  83
  84 void no_ack_irq(unsigned int irq) { }
  85 void no_end_irq(unsigned int irq) { }
  86
  87 void cpu_ack_irq(unsigned int irq)
  88 {
  89         unsigned long mask = EIEM_MASK(irq);
  90         int cpu = smp_processor_id();
  91
  92         /* Clear in EIEM so we can no longer process */
  93         per_cpu(local_ack_eiem, cpu) &= ~mask;
  94
  95         /* disable the interrupt */
  96         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
  97
  98         /* and now ack it */
  99         mtctl(mask, 23);
 100 }
 101
 102 void cpu_end_irq(unsigned int irq)
 103 {
 104         unsigned long mask = EIEM_MASK(irq);
 105         int cpu = smp_processor_id();
 106
 107         /* set it in the eiems---it's no longer in process */
 108         per_cpu(local_ack_eiem, cpu) |= mask;
 109
 110         /* enable the interrupt */
 111         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
 112 }
 113
 114 #ifdef CONFIG_SMP
 115 int cpu_check_affinity(unsigned int irq, cpumask_t *dest)
 116 {
 117         int cpu_dest;
 118
 119         /* timer and ipi have to always be received on all CPUs */
 120         if (CHECK_IRQ_PER_CPU(irq)) {
 121                 /* Bad linux design decision.  The mask has already
 122                  * been set; we must reset it */
 123                 irq_desc[irq].affinity = CPU_MASK_ALL;
 124                 return -EINVAL;
 125         }
 126
 127         /* whatever mask they set, we just allow one CPU */
 128         cpu_dest = first_cpu(*dest);
 129         *dest = cpumask_of_cpu(cpu_dest);
 130
 131         return 0;
 132 }
 133
 134 static void cpu_set_affinity_irq(unsigned int irq, cpumask_t dest)
 135 {
 136         if (cpu_check_affinity(irq, &dest))
 137                 return;
 138
 139         irq_desc[irq].affinity = dest;
 140 }
 141 #endif
 142
 143 static struct hw_interrupt_type cpu_interrupt_type = {
 144         .typename       = "CPU",
 145         .startup        = cpu_startup_irq,
 146         .shutdown       = cpu_disable_irq,
 147         .enable         = cpu_enable_irq,
 148         .disable        = cpu_disable_irq,
 149         .ack            = cpu_ack_irq,
 150         .end            = cpu_end_irq,
 151 #ifdef CONFIG_SMP
 152         .set_affinity   = cpu_set_affinity_irq,
 153 #endif
 154         /* XXX: Needs to be written.  We managed without it so far, but
 155          * we really ought to write it.
 156          */
 157         .retrigger      = NULL,
 158 };
 159
 160 int show_interrupts(struct seq_file *p, void *v)
 161 {
 162         int i = *(loff_t *) v, j;
 163         unsigned long flags;
 164
 165         if (i == 0) {
 166                 seq_puts(p, "    ");
 167                 for_each_online_cpu(j)
 168                         seq_printf(p, "       CPU%d", j);
 169
 170 #ifdef PARISC_IRQ_CR16_COUNTS
 171                 seq_printf(p, " [min/avg/max] (CPU cycle counts)");
 172 #endif
 173                 seq_putc(p, '\n');
 174         }
 175
 176         if (i < NR_IRQS) {
 177                 struct irqaction *action;
 178
 179                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 180                 action = irq_desc[i].action;
 181                 if (!action)
 182                         goto skip;
 183                 seq_printf(p, "%3d: ", i);
 184 #ifdef CONFIG_SMP
 185                 for_each_online_cpu(j)
 186                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
 187 #else
 188                 seq_printf(p, "%10u ", kstat_irqs(i));
 189 #endif
 190
 191                 seq_printf(p, " %14s", irq_desc[i].chip->typename);
 192 #ifndef PARISC_IRQ_CR16_COUNTS
 193                 seq_printf(p, "  %s", action->name);
 194
 195                 while ((action = action->next))
 196                         seq_printf(p, ", %s", action->name);
 197 #else
 198                 for ( ;action; action = action->next) {
 199                         unsigned int k, avg, min, max;
 200
 201                         min = max = action->cr16_hist[0];
 202
 203                         for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) {
 204                                 int hist = action->cr16_hist[k];
 205
 206                                 if (hist) {
 207                                         avg += hist;
 208                                 } else
 209                                         break;
 210
 211                                 if (hist > max) max = hist;
 212                                 if (hist < min) min = hist;
 213                         }
 214
 215                         avg /= k;
 216                         seq_printf(p, " %s[%d/%d/%d]", action->name,
 217                                         min,avg,max);
 218                 }
 219 #endif
 220
 221                 seq_putc(p, '\n');
 222  skip:
 223                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 224         }
 225
 226         return 0;
 227 }
 228
 229
 230
 231 /*
 232 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data.
 233 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit.
 234 **
 235 ** To use txn_XXX() interfaces, get a Virtual IRQ first.
 236 ** Then use that to get the Transaction address and data.
 237 */
 238
 239 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
 240 {
 241         if (irq_desc[irq].action)
 242                 return -EBUSY;
 243         if (irq_desc[irq].chip != &cpu_interrupt_type)
 244                 return -EBUSY;
 245
 246         if (type) {
 247                 irq_desc[irq].chip = type;
 248                 irq_desc[irq].chip_data = data;
 249                 cpu_interrupt_type.enable(irq);
 250         }
 251         return 0;
 252 }
 253
 254 int txn_claim_irq(int irq)
 255 {
 256         return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq;
 257 }
 258
 259 /*
 260  * The bits_wide parameter accommodates the limitations of the HW/SW which
 261  * use these bits:
 262  * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register)
 263  * V-class (EPIC):          6 bits
 264  * N/L/A-class (iosapic):   8 bits
 265  * PCI 2.2 MSI:            16 bits
 266  * Some PCI devices:       32 bits (Symbios SCSI/ATM/HyperFabric)
 267  *
 268  * On the service provider side:
 269  * o PA 1.1 (and PA2.0 narrow mode)     5-bits (width of EIR register)
 270  * o PA 2.0 wide mode                   6-bits (per processor)
 271  * o IA64                               8-bits (0-256 total)
 272  *
 273  * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported
 274  * by the processor...and the N/L-class I/O subsystem supports more bits than
 275  * PA2.0 has. The first case is the problem.
 276  */
 277 int txn_alloc_irq(unsigned int bits_wide)
 278 {
 279         int irq;
 280
 281         /* never return irq 0 cause that's the interval timer */
 282         for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) {
 283                 if (cpu_claim_irq(irq, NULL, NULL) < 0)
 284                         continue;
 285                 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide))
 286                         continue;
 287                 return irq;
 288         }
 289
 290         /* unlikely, but be prepared */
 291         return -1;
 292 }
 293
 294
 295 unsigned long txn_affinity_addr(unsigned int irq, int cpu)
 296 {
 297 #ifdef CONFIG_SMP
 298         irq_desc[irq].affinity = cpumask_of_cpu(cpu);
 299 #endif
 300
 301         return cpu_data[cpu].txn_addr;
 302 }
 303
 304
 305 unsigned long txn_alloc_addr(unsigned int virt_irq)
 306 {
 307         static int next_cpu = -1;
 308
 309         next_cpu++; /* assign to "next" CPU we want this bugger on */
 310
 311         /* validate entry */
 312         while ((next_cpu < NR_CPUS) && (!cpu_data[next_cpu].txn_addr ||
 313                 !cpu_online(next_cpu)))
 314                 next_cpu++;
 315
 316         if (next_cpu >= NR_CPUS)
 317                 next_cpu = 0;   /* nothing else, assign monarch */
 318
 319         return txn_affinity_addr(virt_irq, next_cpu);
 320 }
 321
 322
 323 unsigned int txn_alloc_data(unsigned int virt_irq)
 324 {
 325         return virt_irq - CPU_IRQ_BASE;
 326 }
 327
 328 static inline int eirr_to_irq(unsigned long eirr)
 329 {
 330         int bit = fls_long(eirr);
 331         return (BITS_PER_LONG - bit) + TIMER_IRQ;
 332 }
 333
 334 /* ONLY called from entry.S:intr_extint() */
 335 void do_cpu_irq_mask(struct pt_regs *regs)
 336 {
 337         struct pt_regs *old_regs;
 338         unsigned long eirr_val;
 339         int irq, cpu = smp_processor_id();
 340 #ifdef CONFIG_SMP
 341         cpumask_t dest;
 342 #endif
 343
 344         old_regs = set_irq_regs(regs);
 345         local_irq_disable();
 346         irq_enter();
 347
 348         eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu);
 349         if (!eirr_val)
 350                 goto set_out;
 351         irq = eirr_to_irq(eirr_val);
 352
 353 #ifdef CONFIG_SMP
 354         dest = irq_desc[irq].affinity;
 355         if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) &&
 356             !cpu_isset(smp_processor_id(), dest)) {
 357                 int cpu = first_cpu(dest);
 358
 359                 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n",
 360                        irq, smp_processor_id(), cpu);
 361                 gsc_writel(irq + CPU_IRQ_BASE,
 362                            cpu_data[cpu].hpa);
 363                 goto set_out;
 364         }
 365 #endif
 366         __do_IRQ(irq);
 367
 368  out:
 369         irq_exit();
 370         set_irq_regs(old_regs);
 371         return;
 372
 373  set_out:
 374         set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu));
 375         goto out;
 376 }
 377
 378 static struct irqaction timer_action = {
 379         .handler = timer_interrupt,
 380         .name = "timer",
 381         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL,
 382 };
 383
 384 #ifdef CONFIG_SMP
 385 static struct irqaction ipi_action = {
 386         .handler = ipi_interrupt,
 387         .name = "IPI",
 388         .flags = IRQF_DISABLED | IRQF_PERCPU,
 389 };
 390 #endif
 391
 392 static void claim_cpu_irqs(void)
 393 {
 394         int i;
 395         for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
 396                 irq_desc[i].chip = &cpu_interrupt_type;
 397         }
 398
 399         irq_desc[TIMER_IRQ].action = &timer_action;
 400         irq_desc[TIMER_IRQ].status = IRQ_PER_CPU;
 401 #ifdef CONFIG_SMP
 402         irq_desc[IPI_IRQ].action = &ipi_action;
 403         irq_desc[IPI_IRQ].status = IRQ_PER_CPU;
 404 #endif
 405 }
 406
 407 void __init init_IRQ(void)
 408 {
 409         local_irq_disable();    /* PARANOID - should already be disabled */
 410         mtctl(~0UL, 23);        /* EIRR : clear all pending external intr */
 411         claim_cpu_irqs();
 412 #ifdef CONFIG_SMP
 413         if (!cpu_eiem)
 414                 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ);
 415 #else
 416         cpu_eiem = EIEM_MASK(TIMER_IRQ);
 417 #endif
 418         set_eiem(cpu_eiem);     /* EIEM : enable all external intr */
 419
 420 }
 421
 422 void ack_bad_irq(unsigned int irq)
 423 {
 424         printk("unexpected IRQ %d\n", irq);
 425 }