include/asm-x86/geode.h

   1 /*
   2  * AMD Geode definitions
   3  * Copyright (C) 2006, Advanced Micro Devices, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of version 2 of the GNU General Public License
   7  * as published by the Free Software Foundation.
   8  */
   9
  10 #ifndef _ASM_GEODE_H_
  11 #define _ASM_GEODE_H_
  12
  13 #include <asm/processor.h>
  14 #include <linux/io.h>
  15
  16 /* Generic southbridge functions */
  17
  18 #define GEODE_DEV_PMS 0
  19 #define GEODE_DEV_ACPI 1
  20 #define GEODE_DEV_GPIO 2
  21 #define GEODE_DEV_MFGPT 3
  22
  23 extern int geode_get_dev_base(unsigned int dev);
  24
  25 /* Useful macros */
  26 #define geode_pms_base()        geode_get_dev_base(GEODE_DEV_PMS)
  27 #define geode_acpi_base()       geode_get_dev_base(GEODE_DEV_ACPI)
  28 #define geode_gpio_base()       geode_get_dev_base(GEODE_DEV_GPIO)
  29 #define geode_mfgpt_base()      geode_get_dev_base(GEODE_DEV_MFGPT)
  30
  31 /* MSRS */
  32
  33 #define GX_GLCP_SYS_RSTPLL      0x4C000014
  34
  35 #define MSR_LBAR_SMB            0x5140000B
  36 #define MSR_LBAR_GPIO           0x5140000C
  37 #define MSR_LBAR_MFGPT          0x5140000D
  38 #define MSR_LBAR_ACPI           0x5140000E
  39 #define MSR_LBAR_PMS            0x5140000F
  40
  41 #define MSR_DIVIL_SOFT_RESET    0x51400017
  42
  43 #define MSR_PIC_YSEL_LOW        0x51400020
  44 #define MSR_PIC_YSEL_HIGH       0x51400021
  45 #define MSR_PIC_ZSEL_LOW        0x51400022
  46 #define MSR_PIC_ZSEL_HIGH       0x51400023
  47
  48 #define MFGPT_IRQ_MSR           0x51400028
  49 #define MFGPT_NR_MSR            0x51400029
  50
  51 /* Resource Sizes */
  52
  53 #define LBAR_GPIO_SIZE          0xFF
  54 #define LBAR_MFGPT_SIZE         0x40
  55 #define LBAR_ACPI_SIZE          0x40
  56 #define LBAR_PMS_SIZE           0x80
  57
  58 /* ACPI registers (PMS block) */
  59
  60 /*
  61  * PM1_EN is only valid when VSA is enabled for 16 bit reads.
  62  * When VSA is not enabled, *always* read both PM1_STS and PM1_EN
  63  * with a 32 bit read at offset 0x0
  64  */
  65
  66 #define PM1_STS                 0x00
  67 #define PM1_EN                  0x02
  68 #define PM1_CNT                 0x08
  69 #define PM2_CNT                 0x0C
  70 #define PM_TMR                  0x10
  71 #define PM_GPE0_STS             0x18
  72 #define PM_GPE0_EN              0x1C
  73
  74 /* PMC registers (PMS block) */
  75
  76 #define PM_SSD                  0x00
  77 #define PM_SCXA                 0x04
  78 #define PM_SCYA                 0x08
  79 #define PM_OUT_SLPCTL           0x0C
  80 #define PM_SCLK                 0x10
  81 #define PM_SED                  0x1
  82 #define PM_SCXD                 0x18
  83 #define PM_SCYD                 0x1C
  84 #define PM_IN_SLPCTL            0x20
  85 #define PM_WKD                  0x30
  86 #define PM_WKXD                 0x34
  87 #define PM_RD                   0x38
  88 #define PM_WKXA                 0x3C
  89 #define PM_FSD                  0x40
  90 #define PM_TSD                  0x44
  91 #define PM_PSD                  0x48
  92 #define PM_NWKD                 0x4C
  93 #define PM_AWKD                 0x50
  94 #define PM_SSC                  0x54
  95
  96 /* GPIO */
  97
  98 #define GPIO_OUTPUT_VAL         0x00
  99 #define GPIO_OUTPUT_ENABLE      0x04
 100 #define GPIO_OUTPUT_OPEN_DRAIN  0x08
 101 #define GPIO_OUTPUT_INVERT      0x0C
 102 #define GPIO_OUTPUT_AUX1        0x10
 103 #define GPIO_OUTPUT_AUX2        0x14
 104 #define GPIO_PULL_UP            0x18
 105 #define GPIO_PULL_DOWN          0x1C
 106 #define GPIO_INPUT_ENABLE       0x20
 107 #define GPIO_INPUT_INVERT       0x24
 108 #define GPIO_INPUT_FILTER       0x28
 109 #define GPIO_INPUT_EVENT_COUNT  0x2C
 110 #define GPIO_READ_BACK          0x30
 111 #define GPIO_INPUT_AUX1         0x34
 112 #define GPIO_EVENTS_ENABLE      0x38
 113 #define GPIO_LOCK_ENABLE        0x3C
 114 #define GPIO_POSITIVE_EDGE_EN   0x40
 115 #define GPIO_NEGATIVE_EDGE_EN   0x44
 116 #define GPIO_POSITIVE_EDGE_STS  0x48
 117 #define GPIO_NEGATIVE_EDGE_STS  0x4C
 118
 119 #define GPIO_MAP_X              0xE0
 120 #define GPIO_MAP_Y              0xE4
 121 #define GPIO_MAP_Z              0xE8
 122 #define GPIO_MAP_W              0xEC
 123
 124 static inline u32 geode_gpio(unsigned int nr)
 125 {
 126         BUG_ON(nr > 28);
 127         return 1 << nr;
 128 }
 129
 130 extern void geode_gpio_set(u32, unsigned int);
 131 extern void geode_gpio_clear(u32, unsigned int);
 132 extern int geode_gpio_isset(u32, unsigned int);
 133 extern void geode_gpio_setup_event(unsigned int, int, int);
 134 extern void geode_gpio_set_irq(unsigned int, unsigned int);
 135
 136 static inline void geode_gpio_event_irq(unsigned int gpio, int pair)
 137 {
 138         geode_gpio_setup_event(gpio, pair, 0);
 139 }
 140
 141 static inline void geode_gpio_event_pme(unsigned int gpio, int pair)
 142 {
 143         geode_gpio_setup_event(gpio, pair, 1);
 144 }
 145
 146 /* Specific geode tests */
 147
 148 static inline int is_geode_gx(void)
 149 {
 150         return ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC) &&
 151                 (boot_cpu_data.x86 == 5) &&
 152                 (boot_cpu_data.x86_model == 5));
 153 }
 154
 155 static inline int is_geode_lx(void)
 156 {
 157         return ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
 158                 (boot_cpu_data.x86 == 5) &&
 159                 (boot_cpu_data.x86_model == 10));
 160 }
 161
 162 static inline int is_geode(void)
 163 {
 164         return (is_geode_gx() || is_geode_lx());
 165 }
 166
 167 /* MFGPTs */
 168
 169 #define MFGPT_MAX_TIMERS        8
 170 #define MFGPT_TIMER_ANY         -1
 171
 172 #define MFGPT_DOMAIN_WORKING    1
 173 #define MFGPT_DOMAIN_STANDBY    2
 174 #define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
 175
 176 #define MFGPT_CMP1              0
 177 #define MFGPT_CMP2              1
 178
 179 #define MFGPT_EVENT_IRQ         0
 180 #define MFGPT_EVENT_NMI         1
 181 #define MFGPT_EVENT_RESET       3
 182
 183 #define MFGPT_REG_CMP1          0
 184 #define MFGPT_REG_CMP2          2
 185 #define MFGPT_REG_COUNTER       4
 186 #define MFGPT_REG_SETUP         6
 187
 188 #define MFGPT_SETUP_CNTEN       (1 << 15)
 189 #define MFGPT_SETUP_CMP2        (1 << 14)
 190 #define MFGPT_SETUP_CMP1        (1 << 13)
 191 #define MFGPT_SETUP_SETUP       (1 << 12)
 192 #define MFGPT_SETUP_STOPEN      (1 << 11)
 193 #define MFGPT_SETUP_EXTEN       (1 << 10)
 194 #define MFGPT_SETUP_REVEN       (1 << 5)
 195 #define MFGPT_SETUP_CLKSEL      (1 << 4)
 196
 197 static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
 198 {
 199         u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
 200         outw(value, base + reg + (timer * 8));
 201 }
 202
 203 static inline u16 geode_mfgpt_read(int timer, u16 reg)
 204 {
 205         u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
 206         return inw(base + reg + (timer * 8));
 207 }
 208
 209 extern int __init geode_mfgpt_detect(void);
 210 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
 211 extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
 212 extern int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner);
 213
 214 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
 215 #define geode_mfgpt_release_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 0)
 216
 217 #endif