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x86: unify pageattr_32.c and pageattr_64.c
[wrt350n-kernel.git] / include / sound / ac97_codec.h
blob01480581f825c6886b990972104c7541dcc837a5
1 #ifndef __SOUND_AC97_CODEC_H
2 #define __SOUND_AC97_CODEC_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
6 * Universal interface for Audio Codec '97
7 *
8 * For more details look to AC '97 component specification revision 2.1
9 * by Intel Corporation (http://developer.intel.com).
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/workqueue.h>
31 #include "pcm.h"
32 #include "control.h"
33 #include "info.h"
34
35 /*
36 * AC'97 codec registers
37 */
38
39 #define AC97_RESET 0x00 /* Reset */
40 #define AC97_MASTER 0x02 /* Master Volume */
41 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
42 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
43 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
44 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optinal) */
45 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
46 #define AC97_MIC 0x0e /* MIC Volume */
47 #define AC97_LINE 0x10 /* Line In Volume */
48 #define AC97_CD 0x12 /* CD Volume */
49 #define AC97_VIDEO 0x14 /* Video Volume (optional) */
50 #define AC97_AUX 0x16 /* AUX Volume (optional) */
51 #define AC97_PCM 0x18 /* PCM Volume */
52 #define AC97_REC_SEL 0x1a /* Record Select */
53 #define AC97_REC_GAIN 0x1c /* Record Gain */
54 #define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */
55 #define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */
56 #define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */
57 #define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */
58 #define AC97_POWERDOWN 0x26 /* Powerdown control / status */
59 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
60 #define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */
61 #define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */
62 #define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
63 #define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
64 #define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
65 #define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
66 #define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
67 #define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */
68 #define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */
69 #define AC97_SPDIF 0x3a /* S/PDIF control */
70 /* range 0x3c-0x58 - MODEM */
71 #define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */
72 #define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */
73 #define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */
74 #define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */
75 #define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */
76 #define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */
77 #define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */
78 #define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */
79 #define AC97_GPIO_CFG 0x4c /* GPIO Configuration */
80 #define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */
81 #define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */
82 #define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */
83 #define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */
84 #define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */
85 /* range 0x5a-0x7b - Vendor Specific */
86 #define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */
87 #define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */
88 /* range 0x60-0x6f (page 1) - extended codec registers */
89 #define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */
90 #define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */
91 #define AC97_PCI_SID 0x64 /* PCI Subsystem ID */
92 #define AC97_FUNC_SELECT 0x66 /* Function Select */
93 #define AC97_FUNC_INFO 0x68 /* Function Information */
94 #define AC97_SENSE_INFO 0x6a /* Sense Details */
95
96 /* slot allocation */
97 #define AC97_SLOT_TAG 0
98 #define AC97_SLOT_CMD_ADDR 1
99 #define AC97_SLOT_CMD_DATA 2
100 #define AC97_SLOT_PCM_LEFT 3
101 #define AC97_SLOT_PCM_RIGHT 4
102 #define AC97_SLOT_MODEM_LINE1 5
103 #define AC97_SLOT_PCM_CENTER 6
104 #define AC97_SLOT_MIC 6 /* input */
105 #define AC97_SLOT_SPDIF_LEFT1 6
106 #define AC97_SLOT_PCM_SLEFT 7 /* surround left */
107 #define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
108 #define AC97_SLOT_SPDIF_LEFT 7
109 #define AC97_SLOT_PCM_SRIGHT 8 /* surround right */
110 #define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
111 #define AC97_SLOT_SPDIF_RIGHT 8
112 #define AC97_SLOT_LFE 9
113 #define AC97_SLOT_SPDIF_RIGHT1 9
114 #define AC97_SLOT_MODEM_LINE2 10
115 #define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
116 #define AC97_SLOT_SPDIF_LEFT2 10
117 #define AC97_SLOT_HANDSET 11 /* output */
118 #define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
119 #define AC97_SLOT_SPDIF_RIGHT2 11
120 #define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */
121 #define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
122
123 /* basic capabilities (reset register) */
124 #define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */
125 #define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */
126 #define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */
127 #define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */
128 #define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */
129 #define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */
130 #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
131 #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
132 #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
133 #define AC97_BC_DAC_MASK 0x00c0
134 #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
135 #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
136 #define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
137 #define AC97_BC_ADC_MASK 0x0300
138
139 /* general purpose */
140 #define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */
141 #define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */
142 #define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */
143
144 /* powerdown bits */
145 #define AC97_PD_ADC_STATUS 0x0001 /* ADC status (RO) */
146 #define AC97_PD_DAC_STATUS 0x0002 /* DAC status (RO) */
147 #define AC97_PD_MIXER_STATUS 0x0004 /* Analog mixer status (RO) */
148 #define AC97_PD_VREF_STATUS 0x0008 /* Vref status (RO) */
149 #define AC97_PD_PR0 0x0100 /* Power down PCM ADCs and input MUX */
150 #define AC97_PD_PR1 0x0200 /* Power down PCM front DAC */
151 #define AC97_PD_PR2 0x0400 /* Power down Mixer (Vref still on) */
152 #define AC97_PD_PR3 0x0800 /* Power down Mixer (Vref off) */
153 #define AC97_PD_PR4 0x1000 /* Power down AC-Link */
154 #define AC97_PD_PR5 0x2000 /* Disable internal clock usage */
155 #define AC97_PD_PR6 0x4000 /* Headphone amplifier */
156 #define AC97_PD_EAPD 0x8000 /* External Amplifer Power Down (EAPD) */
157
158 /* extended audio ID bit defines */
159 #define AC97_EI_VRA 0x0001 /* Variable bit rate supported */
160 #define AC97_EI_DRA 0x0002 /* Double rate supported */
161 #define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */
162 #define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */
163 #define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */
164 #define AC97_EI_DACS_SLOT_SHIFT 4
165 #define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */
166 #define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */
167 #define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */
168 #define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */
169 #define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */
170 #define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */
171 #define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */
172 #define AC97_EI_REV_SHIFT 10
173 #define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */
174 #define AC97_EI_ADDR_SHIFT 14
175
176 /* extended audio status and control bit defines */
177 #define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */
178 #define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
179 #define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */
180 #define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */
181 #define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
182 #define AC97_EA_SPSA_SLOT_SHIFT 4
183 #define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
184 #define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
185 #define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
186 #define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
187 #define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */
188 #define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */
189 #define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */
190 #define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */
191 #define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */
192 #define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */
193 #define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */
194 #define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */
195 #define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */
196
197 /* S/PDIF control bit defines */
198 #define AC97_SC_PRO 0x0001 /* Professional status */
199 #define AC97_SC_NAUDIO 0x0002 /* Non audio stream */
200 #define AC97_SC_COPY 0x0004 /* Copyright status */
201 #define AC97_SC_PRE 0x0008 /* Preemphasis status */
202 #define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */
203 #define AC97_SC_CC_SHIFT 4
204 #define AC97_SC_L 0x0800 /* Generation Level status */
205 #define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
206 #define AC97_SC_SPSR_SHIFT 12
207 #define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
208 #define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */
209 #define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */
210 #define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */
211 #define AC97_SC_V 0x8000 /* Validity status */
212
213 /* Interrupt and Paging bit defines (AC'97 2.3) */
214 #define AC97_PAGE_MASK 0x000f /* Page Selector */
215 #define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
216 #define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */
217 #define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */
218 #define AC97_INT_SENSE 0x1000 /* Sense Cycle */
219 #define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */
220 #define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */
221 #define AC97_INT_STATUS 0x8000 /* Interrupt Status */
222
223 /* extended modem ID bit defines */
224 #define AC97_MEI_LINE1 0x0001 /* Line1 present */
225 #define AC97_MEI_LINE2 0x0002 /* Line2 present */
226 #define AC97_MEI_HANDSET 0x0004 /* Handset present */
227 #define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */
228 #define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */
229 #define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */
230 #define AC97_MEI_ADDR_SHIFT 14
231
232 /* extended modem status and control bit defines */
233 #define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */
234 #define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */
235 #define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */
236 #define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */
237 #define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */
238 #define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */
239 #define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */
240 #define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */
241 #define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */
242 #define AC97_MEA_PRB 0x0200 /* reserved */
243 #define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */
244 #define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */
245 #define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */
246 #define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */
247 #define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
248 #define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
249
250 /* modem gpio status defines */
251 #define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
252 #define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
253 #define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
254 #define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
255 #define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
256 #define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
257 #define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
258 #define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
259 #define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
260 #define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
261 #define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
262 #define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
263 #define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
264 #define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
265 #define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
266 #define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
267
268 /* specific - SigmaTel */
269 #define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
270 #define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
271 #define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
272 #define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
273 #define AC97_SIGMATEL_DAC2INVERT 0x6e
274 #define AC97_SIGMATEL_BIAS1 0x70
275 #define AC97_SIGMATEL_BIAS2 0x72
276 #define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
277 #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
278 #define AC97_SIGMATEL_CIC1 0x76
279 #define AC97_SIGMATEL_CIC2 0x78
280
281 /* specific - Analog Devices */
282 #define AC97_AD_TEST 0x5a /* test register */
283 #define AC97_AD_TEST2 0x5c /* undocumented test register 2 */
284 #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
285 #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
286 #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
287 #define AC97_AD_MISC 0x76 /* Misc Control Bits */
288
289 /* specific - Cirrus Logic */
290 #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
291 #define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
292 #define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
293 #define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
294 #define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
295 #define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
296 #define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
297
298 /* specific - Conexant */
299 #define AC97_CXR_AUDIO_MISC 0x5c
300 #define AC97_CXR_SPDIFEN (1<<3)
301 #define AC97_CXR_COPYRGT (1<<2)
302 #define AC97_CXR_SPDIF_MASK (3<<0)
303 #define AC97_CXR_SPDIF_PCM 0x0
304 #define AC97_CXR_SPDIF_AC3 0x2
305
306 /* specific - ALC */
307 #define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
308 /* S/PDIF input status 1 bit defines */
309 #define AC97_ALC650_PRO 0x0001 /* Professional status */
310 #define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
311 #define AC97_ALC650_COPY 0x0004 /* Copyright status */
312 #define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
313 #define AC97_ALC650_PRE_SHIFT 3
314 #define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
315 #define AC97_ALC650_MODE_SHIFT 6
316 #define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
317 #define AC97_ALC650_CC_SHIFT 8
318 #define AC97_ALC650_L 0x8000 /* Generation Level status */
319
320 #define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
321 /* S/PDIF input status 2 bit defines */
322 #define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
323 #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
324 #define AC97_ALC650_CHANNEL_SHIFT 4
325 #define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
326 #define AC97_ALC650_SPSR_SHIFT 8
327 #define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
328 #define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
329 #define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
330 #define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
331 #define AC97_ALC650_CLOCK_SHIFT 12
332 #define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
333 #define AC97_ALC650_V 0x8000 /* Validity status */
334
335 #define AC97_ALC650_SURR_DAC_VOL 0x64
336 #define AC97_ALC650_LFE_DAC_VOL 0x66
337 #define AC97_ALC650_UNKNOWN1 0x68
338 #define AC97_ALC650_MULTICH 0x6a
339 #define AC97_ALC650_UNKNOWN2 0x6c
340 #define AC97_ALC650_REVISION 0x6e
341 #define AC97_ALC650_UNKNOWN3 0x70
342 #define AC97_ALC650_UNKNOWN4 0x72
343 #define AC97_ALC650_MISC 0x74
344 #define AC97_ALC650_GPIO_SETUP 0x76
345 #define AC97_ALC650_GPIO_STATUS 0x78
346 #define AC97_ALC650_CLOCK 0x7a
347
348 /* specific - Yamaha YMF7x3 */
349 #define AC97_YMF7X3_DIT_CTRL 0x66 /* DIT Control (YMF743) / 2 (YMF753) */
350 #define AC97_YMF7X3_3D_MODE_SEL 0x68 /* 3D Mode Select */
351
352 /* specific - C-Media */
353 #define AC97_CM9738_VENDOR_CTRL 0x5a
354 #define AC97_CM9739_MULTI_CHAN 0x64
355 #define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
356 #define AC97_CM9739_SPDIF_CTRL 0x6c
357
358 /* specific - wolfson */
359 #define AC97_WM97XX_FMIXER_VOL 0x72
360 #define AC97_WM9704_RMIXER_VOL 0x74
361 #define AC97_WM9704_TEST 0x5a
362 #define AC97_WM9704_RPCM_VOL 0x70
363 #define AC97_WM9711_OUT3VOL 0x16
364
365
366 /* ac97->scaps */
367 #define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
368 #define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */
369 #define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */
370 #define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */
371 #define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */
372 #define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */
373 #define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */
374 #define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */
375 #define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */
376 #define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */
377 #define AC97_SCAP_EAPD_LED (1<<10) /* EAPD as mute LED */
378 #define AC97_SCAP_POWER_SAVE (1<<11) /* capable for aggresive power-saving */
379
380 /* ac97->flags */
381 #define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
382 #define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */
383 #define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */
384 #define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */
385 #define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */
386 #define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */
387 #define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */
388 #define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */
389 #define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */
390 #define AC97_MODEM_PATCH (1<<9) /* modem patch */
391 #define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */
392 #define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */
393 #define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */
394 #define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */
395 #define AC97_HAS_NO_CD (1<<14) /* no CD volume */
396 #define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */
397 #define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */
398 #define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */
399 #define AC97_HAS_NO_AUX (1<<18) /* no standard AC97 AUX volume and mute */
400
401 /* rates indexes */
402 #define AC97_RATES_FRONT_DAC 0
403 #define AC97_RATES_SURR_DAC 1
404 #define AC97_RATES_LFE_DAC 2
405 #define AC97_RATES_ADC 3
406 #define AC97_RATES_MIC_ADC 4
407 #define AC97_RATES_SPDIF 5
408
409 /*
410 *
411 */
412
413 struct snd_ac97;
414
415 struct snd_ac97_build_ops {
416 int (*build_3d) (struct snd_ac97 *ac97);
417 int (*build_specific) (struct snd_ac97 *ac97);
418 int (*build_spdif) (struct snd_ac97 *ac97);
419 int (*build_post_spdif) (struct snd_ac97 *ac97);
420 #ifdef CONFIG_PM
421 void (*suspend) (struct snd_ac97 *ac97);
422 void (*resume) (struct snd_ac97 *ac97);
423 #endif
424 void (*update_jacks) (struct snd_ac97 *ac97); /* for jack-sharing */
425 };
426
427 struct snd_ac97_bus_ops {
428 void (*reset) (struct snd_ac97 *ac97);
429 void (*warm_reset)(struct snd_ac97 *ac97);
430 void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val);
431 unsigned short (*read) (struct snd_ac97 *ac97, unsigned short reg);
432 void (*wait) (struct snd_ac97 *ac97);
433 void (*init) (struct snd_ac97 *ac97);
434 };
435
436 struct snd_ac97_bus {
437 /* -- lowlevel (hardware) driver specific -- */
438 struct snd_ac97_bus_ops *ops;
439 void *private_data;
440 void (*private_free) (struct snd_ac97_bus *bus);
441 /* --- */
442 struct snd_card *card;
443 unsigned short num; /* bus number */
444 unsigned short no_vra: 1, /* bridge doesn't support VRA */
445 dra: 1, /* bridge supports double rate */
446 isdin: 1;/* independent SDIN */
447 unsigned int clock; /* AC'97 base clock (usually 48000Hz) */
448 spinlock_t bus_lock; /* used mainly for slot allocation */
449 unsigned short used_slots[2][4]; /* actually used PCM slots */
450 unsigned short pcms_count; /* count of PCMs */
451 struct ac97_pcm *pcms;
452 struct snd_ac97 *codec[4];
453 struct snd_info_entry *proc;
454 };
455
456 /* static resolution table */
457 struct snd_ac97_res_table {
458 unsigned short reg; /* register */
459 unsigned short bits; /* resolution bitmask */
460 };
461
462 struct snd_ac97_template {
463 void *private_data;
464 void (*private_free) (struct snd_ac97 *ac97);
465 struct pci_dev *pci; /* assigned PCI device - used for quirks */
466 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
467 unsigned short addr; /* physical address of codec [0-3] */
468 unsigned int scaps; /* driver capabilities */
469 const struct snd_ac97_res_table *res_table; /* static resolution */
470 };
471
472 struct snd_ac97 {
473 /* -- lowlevel (hardware) driver specific -- */
474 struct snd_ac97_build_ops * build_ops;
475 void *private_data;
476 void (*private_free) (struct snd_ac97 *ac97);
477 /* --- */
478 struct snd_ac97_bus *bus;
479 struct pci_dev *pci; /* assigned PCI device - used for quirks */
480 struct snd_info_entry *proc;
481 struct snd_info_entry *proc_regs;
482 unsigned short subsystem_vendor;
483 unsigned short subsystem_device;
484 struct mutex reg_mutex;
485 struct mutex page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */
486 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
487 unsigned short addr; /* physical address of codec [0-3] */
488 unsigned int id; /* identification of codec */
489 unsigned short caps; /* capabilities (register 0) */
490 unsigned short ext_id; /* extended feature identification (register 28) */
491 unsigned short ext_mid; /* extended modem ID (register 3C) */
492 const struct snd_ac97_res_table *res_table; /* static resolution */
493 unsigned int scaps; /* driver capabilities */
494 unsigned int flags; /* specific code */
495 unsigned int rates[6]; /* see AC97_RATES_* defines */
496 unsigned int spdif_status;
497 unsigned short regs[0x80]; /* register cache */
498 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
499 union { /* vendor specific code */
500 struct {
501 unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
502 unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
503 unsigned short id[3]; // codec IDs (lower 16-bit word)
504 unsigned short pcmreg[3]; // PCM registers
505 unsigned short codec_cfg[3]; // CODEC_CFG bits
506 unsigned char swap_mic_linein; // AD1986/AD1986A only
507 } ad18xx;
508 unsigned int dev_flags; /* device specific */
509 } spec;
510 /* jack-sharing info */
511 unsigned char indep_surround;
512 unsigned char channel_mode;
513
514 #ifdef CONFIG_SND_AC97_POWER_SAVE
515 unsigned int power_up; /* power states */
516 struct delayed_work power_work;
517 #endif
518 struct device dev;
519 };
520
521 #define to_ac97_t(d) container_of(d, struct snd_ac97, dev)
522
523 /* conditions */
524 static inline int ac97_is_audio(struct snd_ac97 * ac97)
525 {
526 return (ac97->scaps & AC97_SCAP_AUDIO);
527 }
528 static inline int ac97_is_modem(struct snd_ac97 * ac97)
529 {
530 return (ac97->scaps & AC97_SCAP_MODEM);
531 }
532 static inline int ac97_is_rev22(struct snd_ac97 * ac97)
533 {
534 return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22;
535 }
536 static inline int ac97_can_amap(struct snd_ac97 * ac97)
537 {
538 return (ac97->ext_id & AC97_EI_AMAP) != 0;
539 }
540 static inline int ac97_can_spdif(struct snd_ac97 * ac97)
541 {
542 return (ac97->ext_id & AC97_EI_SPDIF) != 0;
543 }
544
545 /* functions */
546 /* create new AC97 bus */
547 int snd_ac97_bus(struct snd_card *card, int num, struct snd_ac97_bus_ops *ops,
548 void *private_data, struct snd_ac97_bus **rbus);
549 /* create mixer controls */
550 int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template,
551 struct snd_ac97 **rac97);
552 const char *snd_ac97_get_short_name(struct snd_ac97 *ac97);
553
554 void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
555 unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
556 void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
557 int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value);
558 int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value);
559 #ifdef CONFIG_SND_AC97_POWER_SAVE
560 int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup);
561 #else
562 static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg,
563 int powerup)
564 {
565 return 0;
566 }
567 #endif
568 #ifdef CONFIG_PM
569 void snd_ac97_suspend(struct snd_ac97 *ac97);
570 void snd_ac97_resume(struct snd_ac97 *ac97);
571 #endif
572
573 /* quirk types */
574 enum {
575 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
576 AC97_TUNE_NONE = 0, /* nothing extra to do */
577 AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */
578 AC97_TUNE_SWAP_HP, /* swap headphone and master controls */
579 AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */
580 AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */
581 AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */
582 AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */
583 AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */
584 AC97_TUNE_HP_MUTE_LED, /* EAPD bit works as mute LED, use headphone control as master */
585 };
586
587 struct ac97_quirk {
588 unsigned short subvendor; /* PCI subsystem vendor id */
589 unsigned short subdevice; /* PCI sybsystem device id */
590 unsigned short mask; /* device id bit mask, 0 = accept all */
591 unsigned int codec_id; /* codec id (if any), 0 = accept all */
592 const char *name; /* name shown as info */
593 int type; /* quirk type above */
594 };
595
596 int snd_ac97_tune_hardware(struct snd_ac97 *ac97, struct ac97_quirk *quirk, const char *override);
597 int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate);
598
599 /*
600 * PCM allocation
601 */
602
603 enum ac97_pcm_cfg {
604 AC97_PCM_CFG_FRONT = 2,
605 AC97_PCM_CFG_REAR = 10, /* alias surround */
606 AC97_PCM_CFG_LFE = 11, /* center + lfe */
607 AC97_PCM_CFG_40 = 4, /* front + rear */
608 AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */
609 AC97_PCM_CFG_SPDIF = 20
610 };
611
612 struct ac97_pcm {
613 struct snd_ac97_bus *bus;
614 unsigned int stream: 1, /* stream type: 1 = capture */
615 exclusive: 1, /* exclusive mode, don't override with other pcms */
616 copy_flag: 1, /* lowlevel driver must fill all entries */
617 spdif: 1; /* spdif pcm */
618 unsigned short aslots; /* active slots */
619 unsigned short cur_dbl; /* current double-rate state */
620 unsigned int rates; /* available rates */
621 struct {
622 unsigned short slots; /* driver input: requested AC97 slot numbers */
623 unsigned short rslots[4]; /* allocated slots per codecs */
624 unsigned char rate_table[4];
625 struct snd_ac97 *codec[4]; /* allocated codecs */
626 } r[2]; /* 0 = standard rates, 1 = double rates */
627 unsigned long private_value; /* used by the hardware driver */
628 };
629
630 int snd_ac97_pcm_assign(struct snd_ac97_bus *ac97,
631 unsigned short pcms_count,
632 const struct ac97_pcm *pcms);
633 int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate,
634 enum ac97_pcm_cfg cfg, unsigned short slots);
635 int snd_ac97_pcm_close(struct ac97_pcm *pcm);
636 int snd_ac97_pcm_double_rate_rules(struct snd_pcm_runtime *runtime);
637
638 /* ad hoc AC97 device driver access */
639 extern struct bus_type ac97_bus_type;
640
641 #endif /* __SOUND_AC97_CODEC_H */
WRT350N Kernel Patches