| blob | f7458396cd7c022968abb231d1fdf62cb5ec2c67 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <asm/processor.h>
23 #include <asm/page.h>
24 #include <asm/mmu.h>
25 #include <asm/cache.h>
26 #include <asm/pgtable.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
32 /* Macro to make the code more readable. */
33 #ifdef CONFIG_8xx_CPU6
34 #define DO_8xx_CPU6(val, reg) \
35 li reg, val; \
36 stw reg, 12(r0); \
37 lwz reg, 12(r0);
38 #else
39 #define DO_8xx_CPU6(val, reg)
40 #endif
41 .section .text.head, "ax"
42 _ENTRY(_stext);
43 _ENTRY(_start);
45 /* MPC8xx
46 * This port was done on an MBX board with an 860. Right now I only
47 * support an ELF compressed (zImage) boot from EPPC-Bug because the
48 * code there loads up some registers before calling us:
49 * r3: ptr to board info data
50 * r4: initrd_start or if no initrd then 0
51 * r5: initrd_end - unused if r4 is 0
52 * r6: Start of command line string
53 * r7: End of command line string
54 *
55 * I decided to use conditional compilation instead of checking PVR and
56 * adding more processor specific branches around code I don't need.
57 * Since this is an embedded processor, I also appreciate any memory
58 * savings I can get.
59 *
60 * The MPC8xx does not have any BATs, but it supports large page sizes.
61 * We first initialize the MMU to support 8M byte pages, then load one
62 * entry into each of the instruction and data TLBs to map the first
63 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
64 * the "internal" processor registers before MMU_init is called.
65 *
66 * The TLB code currently contains a major hack. Since I use the condition
67 * code register, I have to save and restore it. I am out of registers, so
68 * I just store it in memory location 0 (the TLB handlers are not reentrant).
69 * To avoid making any decisions, I need to use the "segment" valid bit
70 * in the first level table, but that would require many changes to the
71 * Linux page directory/table functions that I don't want to do right now.
72 *
73 * I used to use SPRG2 for a temporary register in the TLB handler, but it
74 * has since been put to other uses. I now use a hack to save a register
75 * and the CCR at memory location 0.....Someday I'll fix this.....
76 * -- Dan
77 */
78 .globl __start
79 __start:
80 mr r31,r3 /* save parameters */
81 mr r30,r4
82 mr r29,r5
83 mr r28,r6
84 mr r27,r7
86 /* We have to turn on the MMU right away so we get cache modes
87 * set correctly.
88 */
89 bl initial_mmu
91 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
92 * ready to work.
93 */
95 turn_on_mmu:
96 mfmsr r0
97 ori r0,r0,MSR_DR|MSR_IR
98 mtspr SPRN_SRR1,r0
99 lis r0,start_here@h
100 ori r0,r0,start_here@l
101 mtspr SPRN_SRR0,r0
102 SYNC
103 rfi /* enables MMU */
105 /*
106 * Exception entry code. This code runs with address translation
107 * turned off, i.e. using physical addresses.
108 * We assume sprg3 has the physical address of the current
109 * task's thread_struct.
110 */
111 #define EXCEPTION_PROLOG \
112 mtspr SPRN_SPRG0,r10; \
113 mtspr SPRN_SPRG1,r11; \
114 mfcr r10; \
115 EXCEPTION_PROLOG_1; \
116 EXCEPTION_PROLOG_2
118 #define EXCEPTION_PROLOG_1 \
119 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
120 andi. r11,r11,MSR_PR; \
121 tophys(r11,r1); /* use tophys(r1) if kernel */ \
122 beq 1f; \
123 mfspr r11,SPRN_SPRG3; \
124 lwz r11,THREAD_INFO-THREAD(r11); \
125 addi r11,r11,THREAD_SIZE; \
126 tophys(r11,r11); \
127 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
130 #define EXCEPTION_PROLOG_2 \
131 CLR_TOP32(r11); \
132 stw r10,_CCR(r11); /* save registers */ \
133 stw r12,GPR12(r11); \
134 stw r9,GPR9(r11); \
135 mfspr r10,SPRN_SPRG0; \
136 stw r10,GPR10(r11); \
137 mfspr r12,SPRN_SPRG1; \
138 stw r12,GPR11(r11); \
139 mflr r10; \
140 stw r10,_LINK(r11); \
141 mfspr r12,SPRN_SRR0; \
142 mfspr r9,SPRN_SRR1; \
143 stw r1,GPR1(r11); \
144 stw r1,0(r11); \
145 tovirt(r1,r11); /* set new kernel sp */ \
146 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
147 MTMSRD(r10); /* (except for mach check in rtas) */ \
148 stw r0,GPR0(r11); \
149 SAVE_4GPRS(3, r11); \
150 SAVE_2GPRS(7, r11)
152 /*
153 * Note: code which follows this uses cr0.eq (set if from kernel),
154 * r11, r12 (SRR0), and r9 (SRR1).
155 *
156 * Note2: once we have set r1 we are in a position to take exceptions
157 * again, and we could thus set MSR:RI at that point.
158 */
160 /*
161 * Exception vectors.
162 */
163 #define EXCEPTION(n, label, hdlr, xfer) \
164 . = n; \
165 label: \
166 EXCEPTION_PROLOG; \
167 addi r3,r1,STACK_FRAME_OVERHEAD; \
168 xfer(n, hdlr)
170 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
171 li r10,trap; \
172 stw r10,_TRAP(r11); \
173 li r10,MSR_KERNEL; \
174 copyee(r10, r9); \
175 bl tfer; \
176 i##n: \
177 .long hdlr; \
178 .long ret
180 #define COPY_EE(d, s) rlwimi d,s,0,16,16
181 #define NOCOPY(d, s)
183 #define EXC_XFER_STD(n, hdlr) \
184 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
185 ret_from_except_full)
187 #define EXC_XFER_LITE(n, hdlr) \
188 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
189 ret_from_except)
191 #define EXC_XFER_EE(n, hdlr) \
192 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
193 ret_from_except_full)
195 #define EXC_XFER_EE_LITE(n, hdlr) \
196 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
197 ret_from_except)
199 /* System reset */
200 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
202 /* Machine check */
203 . = 0x200
204 MachineCheck:
205 EXCEPTION_PROLOG
206 mfspr r4,SPRN_DAR
207 stw r4,_DAR(r11)
208 mfspr r5,SPRN_DSISR
209 stw r5,_DSISR(r11)
210 addi r3,r1,STACK_FRAME_OVERHEAD
211 EXC_XFER_STD(0x200, machine_check_exception)
213 /* Data access exception.
214 * This is "never generated" by the MPC8xx. We jump to it for other
215 * translation errors.
216 */
217 . = 0x300
218 DataAccess:
219 EXCEPTION_PROLOG
220 mfspr r10,SPRN_DSISR
221 stw r10,_DSISR(r11)
222 mr r5,r10
223 mfspr r4,SPRN_DAR
224 EXC_XFER_EE_LITE(0x300, handle_page_fault)
226 /* Instruction access exception.
227 * This is "never generated" by the MPC8xx. We jump to it for other
228 * translation errors.
229 */
230 . = 0x400
231 InstructionAccess:
232 EXCEPTION_PROLOG
233 mr r4,r12
234 mr r5,r9
235 EXC_XFER_EE_LITE(0x400, handle_page_fault)
237 /* External interrupt */
238 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
240 /* Alignment exception */
241 . = 0x600
242 Alignment:
243 EXCEPTION_PROLOG
244 mfspr r4,SPRN_DAR
245 stw r4,_DAR(r11)
246 mfspr r5,SPRN_DSISR
247 stw r5,_DSISR(r11)
248 addi r3,r1,STACK_FRAME_OVERHEAD
249 EXC_XFER_EE(0x600, alignment_exception)
251 /* Program check exception */
252 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
254 /* No FPU on MPC8xx. This exception is not supposed to happen.
255 */
256 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
258 /* Decrementer */
259 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
261 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
262 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
264 /* System call */
265 . = 0xc00
266 SystemCall:
267 EXCEPTION_PROLOG
268 EXC_XFER_EE_LITE(0xc00, DoSyscall)
270 /* Single step - not used on 601 */
271 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
272 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
273 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
275 /* On the MPC8xx, this is a software emulation interrupt. It occurs
276 * for all unimplemented and illegal instructions.
277 */
278 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
280 . = 0x1100
281 /*
282 * For the MPC8xx, this is a software tablewalk to load the instruction
283 * TLB. It is modelled after the example in the Motorola manual. The task
284 * switch loads the M_TWB register with the pointer to the first level table.
285 * If we discover there is no second level table (value is zero) or if there
286 * is an invalid pte, we load that into the TLB, which causes another fault
287 * into the TLB Error interrupt where we can handle such problems.
288 * We have to use the MD_xxx registers for the tablewalk because the
289 * equivalent MI_xxx registers only perform the attribute functions.
290 */
291 InstructionTLBMiss:
292 #ifdef CONFIG_8xx_CPU6
293 stw r3, 8(r0)
294 #endif
295 DO_8xx_CPU6(0x3f80, r3)
296 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
297 mfcr r10
298 stw r10, 0(r0)
299 stw r11, 4(r0)
300 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
301 #ifdef CONFIG_8xx_CPU15
302 addi r11, r10, 0x1000
303 tlbie r11
304 addi r11, r10, -0x1000
305 tlbie r11
306 #endif
307 DO_8xx_CPU6(0x3780, r3)
308 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
309 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
311 /* If we are faulting a kernel address, we have to use the
312 * kernel page tables.
313 */
314 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
315 beq 3f
316 lis r11, swapper_pg_dir@h
317 ori r11, r11, swapper_pg_dir@l
318 rlwimi r10, r11, 0, 2, 19
319 3:
320 lwz r11, 0(r10) /* Get the level 1 entry */
321 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
322 beq 2f /* If zero, don't try to find a pte */
324 /* We have a pte table, so load the MI_TWC with the attributes
325 * for this "segment."
326 */
327 ori r11,r11,1 /* Set valid bit */
328 DO_8xx_CPU6(0x2b80, r3)
329 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
330 DO_8xx_CPU6(0x3b80, r3)
331 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
332 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
333 lwz r10, 0(r11) /* Get the pte */
335 ori r10, r10, _PAGE_ACCESSED
336 stw r10, 0(r11)
338 /* The Linux PTE won't go exactly into the MMU TLB.
339 * Software indicator bits 21, 22 and 28 must be clear.
340 * Software indicator bits 24, 25, 26, and 27 must be
341 * set. All other Linux PTE bits control the behavior
342 * of the MMU.
343 */
344 2: li r11, 0x00f0
345 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
346 DO_8xx_CPU6(0x2d80, r3)
347 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
349 mfspr r10, SPRN_M_TW /* Restore registers */
350 lwz r11, 0(r0)
351 mtcr r11
352 lwz r11, 4(r0)
353 #ifdef CONFIG_8xx_CPU6
354 lwz r3, 8(r0)
355 #endif
356 rfi
358 . = 0x1200
359 DataStoreTLBMiss:
360 #ifdef CONFIG_8xx_CPU6
361 stw r3, 8(r0)
362 #endif
363 DO_8xx_CPU6(0x3f80, r3)
364 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
365 mfcr r10
366 stw r10, 0(r0)
367 stw r11, 4(r0)
368 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
370 /* If we are faulting a kernel address, we have to use the
371 * kernel page tables.
372 */
373 andi. r11, r10, 0x0800
374 beq 3f
375 lis r11, swapper_pg_dir@h
376 ori r11, r11, swapper_pg_dir@l
377 rlwimi r10, r11, 0, 2, 19
378 3:
379 lwz r11, 0(r10) /* Get the level 1 entry */
380 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
381 beq 2f /* If zero, don't try to find a pte */
383 /* We have a pte table, so load fetch the pte from the table.
384 */
385 ori r11, r11, 1 /* Set valid bit in physical L2 page */
386 DO_8xx_CPU6(0x3b80, r3)
387 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
388 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
389 lwz r10, 0(r10) /* Get the pte */
391 /* Insert the Guarded flag into the TWC from the Linux PTE.
392 * It is bit 27 of both the Linux PTE and the TWC (at least
393 * I got that right :-). It will be better when we can put
394 * this into the Linux pgd/pmd and load it in the operation
395 * above.
396 */
397 rlwimi r11, r10, 0, 27, 27
398 DO_8xx_CPU6(0x3b80, r3)
399 mtspr SPRN_MD_TWC, r11
401 mfspr r11, SPRN_MD_TWC /* get the pte address again */
402 ori r10, r10, _PAGE_ACCESSED
403 stw r10, 0(r11)
405 /* The Linux PTE won't go exactly into the MMU TLB.
406 * Software indicator bits 21, 22 and 28 must be clear.
407 * Software indicator bits 24, 25, 26, and 27 must be
408 * set. All other Linux PTE bits control the behavior
409 * of the MMU.
410 */
411 2: li r11, 0x00f0
412 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
413 DO_8xx_CPU6(0x3d80, r3)
414 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
416 mfspr r10, SPRN_M_TW /* Restore registers */
417 lwz r11, 0(r0)
418 mtcr r11
419 lwz r11, 4(r0)
420 #ifdef CONFIG_8xx_CPU6
421 lwz r3, 8(r0)
422 #endif
423 rfi
425 /* This is an instruction TLB error on the MPC8xx. This could be due
426 * to many reasons, such as executing guarded memory or illegal instruction
427 * addresses. There is nothing to do but handle a big time error fault.
428 */
429 . = 0x1300
430 InstructionTLBError:
431 b InstructionAccess
433 /* This is the data TLB error on the MPC8xx. This could be due to
434 * many reasons, including a dirty update to a pte. We can catch that
435 * one here, but anything else is an error. First, we track down the
436 * Linux pte. If it is valid, write access is allowed, but the
437 * page dirty bit is not set, we will set it and reload the TLB. For
438 * any other case, we bail out to a higher level function that can
439 * handle it.
440 */
441 . = 0x1400
442 DataTLBError:
443 #ifdef CONFIG_8xx_CPU6
444 stw r3, 8(r0)
445 #endif
446 DO_8xx_CPU6(0x3f80, r3)
447 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
448 mfcr r10
449 stw r10, 0(r0)
450 stw r11, 4(r0)
452 /* First, make sure this was a store operation.
453 */
454 mfspr r10, SPRN_DSISR
455 andis. r11, r10, 0x0200 /* If set, indicates store op */
456 beq 2f
458 /* The EA of a data TLB miss is automatically stored in the MD_EPN
459 * register. The EA of a data TLB error is automatically stored in
460 * the DAR, but not the MD_EPN register. We must copy the 20 most
461 * significant bits of the EA from the DAR to MD_EPN before we
462 * start walking the page tables. We also need to copy the CASID
463 * value from the M_CASID register.
464 * Addendum: The EA of a data TLB error is _supposed_ to be stored
465 * in DAR, but it seems that this doesn't happen in some cases, such
466 * as when the error is due to a dcbi instruction to a page with a
467 * TLB that doesn't have the changed bit set. In such cases, there
468 * does not appear to be any way to recover the EA of the error
469 * since it is neither in DAR nor MD_EPN. As a workaround, the
470 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
471 * are initialized in mapin_ram(). This will avoid the problem,
472 * assuming we only use the dcbi instruction on kernel addresses.
473 */
474 mfspr r10, SPRN_DAR
475 rlwinm r11, r10, 0, 0, 19
476 ori r11, r11, MD_EVALID
477 mfspr r10, SPRN_M_CASID
478 rlwimi r11, r10, 0, 28, 31
479 DO_8xx_CPU6(0x3780, r3)
480 mtspr SPRN_MD_EPN, r11
482 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
484 /* If we are faulting a kernel address, we have to use the
485 * kernel page tables.
486 */
487 andi. r11, r10, 0x0800
488 beq 3f
489 lis r11, swapper_pg_dir@h
490 ori r11, r11, swapper_pg_dir@l
491 rlwimi r10, r11, 0, 2, 19
492 3:
493 lwz r11, 0(r10) /* Get the level 1 entry */
494 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
495 beq 2f /* If zero, bail */
497 /* We have a pte table, so fetch the pte from the table.
498 */
499 ori r11, r11, 1 /* Set valid bit in physical L2 page */
500 DO_8xx_CPU6(0x3b80, r3)
501 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
502 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
503 lwz r10, 0(r11) /* Get the pte */
505 andi. r11, r10, _PAGE_RW /* Is it writeable? */
506 beq 2f /* Bail out if not */
508 /* Update 'changed', among others.
509 */
510 ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
511 mfspr r11, SPRN_MD_TWC /* Get pte address again */
512 stw r10, 0(r11) /* and update pte in table */
514 /* The Linux PTE won't go exactly into the MMU TLB.
515 * Software indicator bits 21, 22 and 28 must be clear.
516 * Software indicator bits 24, 25, 26, and 27 must be
517 * set. All other Linux PTE bits control the behavior
518 * of the MMU.
519 */
520 li r11, 0x00f0
521 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
522 DO_8xx_CPU6(0x3d80, r3)
523 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
525 mfspr r10, SPRN_M_TW /* Restore registers */
526 lwz r11, 0(r0)
527 mtcr r11
528 lwz r11, 4(r0)
529 #ifdef CONFIG_8xx_CPU6
530 lwz r3, 8(r0)
531 #endif
532 rfi
533 2:
534 mfspr r10, SPRN_M_TW /* Restore registers */
535 lwz r11, 0(r0)
536 mtcr r11
537 lwz r11, 4(r0)
538 #ifdef CONFIG_8xx_CPU6
539 lwz r3, 8(r0)
540 #endif
541 b DataAccess
543 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
544 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
545 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
546 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
547 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
548 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
549 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
551 /* On the MPC8xx, these next four traps are used for development
552 * support of breakpoints and such. Someday I will get around to
553 * using them.
554 */
555 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
556 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
557 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
558 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
560 . = 0x2000
562 .globl giveup_fpu
563 giveup_fpu:
564 blr
566 /*
567 * This is where the main kernel code starts.
568 */
569 start_here:
570 /* ptr to current */
571 lis r2,init_task@h
572 ori r2,r2,init_task@l
574 /* ptr to phys current thread */
575 tophys(r4,r2)
576 addi r4,r4,THREAD /* init task's THREAD */
577 mtspr SPRN_SPRG3,r4
578 li r3,0
579 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
581 /* stack */
582 lis r1,init_thread_union@ha
583 addi r1,r1,init_thread_union@l
584 li r0,0
585 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
587 bl early_init /* We have to do this with MMU on */
589 /*
590 * Decide what sort of machine this is and initialize the MMU.
591 */
592 mr r3,r31
593 mr r4,r30
594 mr r5,r29
595 mr r6,r28
596 mr r7,r27
597 bl machine_init
598 bl MMU_init
600 /*
601 * Go back to running unmapped so we can load up new values
602 * and change to using our exception vectors.
603 * On the 8xx, all we have to do is invalidate the TLB to clear
604 * the old 8M byte TLB mappings and load the page table base register.
605 */
606 /* The right way to do this would be to track it down through
607 * init's THREAD like the context switch code does, but this is
608 * easier......until someone changes init's static structures.
609 */
610 lis r6, swapper_pg_dir@h
611 ori r6, r6, swapper_pg_dir@l
612 tophys(r6,r6)
613 #ifdef CONFIG_8xx_CPU6
614 lis r4, cpu6_errata_word@h
615 ori r4, r4, cpu6_errata_word@l
616 li r3, 0x3980
617 stw r3, 12(r4)
618 lwz r3, 12(r4)
619 #endif
620 mtspr SPRN_M_TWB, r6
621 lis r4,2f@h
622 ori r4,r4,2f@l
623 tophys(r4,r4)
624 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
625 mtspr SPRN_SRR0,r4
626 mtspr SPRN_SRR1,r3
627 rfi
628 /* Load up the kernel context */
629 2:
630 SYNC /* Force all PTE updates to finish */
631 tlbia /* Clear all TLB entries */
632 sync /* wait for tlbia/tlbie to finish */
633 TLBSYNC /* ... on all CPUs */
635 /* set up the PTE pointers for the Abatron bdiGDB.
636 */
637 tovirt(r6,r6)
638 lis r5, abatron_pteptrs@h
639 ori r5, r5, abatron_pteptrs@l
640 stw r5, 0xf0(r0) /* Must match your Abatron config file */
641 tophys(r5,r5)
642 stw r6, 0(r5)
644 /* Now turn on the MMU for real! */
645 li r4,MSR_KERNEL
646 lis r3,start_kernel@h
647 ori r3,r3,start_kernel@l
648 mtspr SPRN_SRR0,r3
649 mtspr SPRN_SRR1,r4
650 rfi /* enable MMU and jump to start_kernel */
652 /* Set up the initial MMU state so we can do the first level of
653 * kernel initialization. This maps the first 8 MBytes of memory 1:1
654 * virtual to physical. Also, set the cache mode since that is defined
655 * by TLB entries and perform any additional mapping (like of the IMMR).
656 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
657 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
658 * these mappings is mapped by page tables.
659 */
660 initial_mmu:
661 tlbia /* Invalidate all TLB entries */
662 #ifdef CONFIG_PIN_TLB
663 lis r8, MI_RSV4I@h
664 ori r8, r8, 0x1c00
665 #else
666 li r8, 0
667 #endif
668 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
670 #ifdef CONFIG_PIN_TLB
671 lis r10, (MD_RSV4I | MD_RESETVAL)@h
672 ori r10, r10, 0x1c00
673 mr r8, r10
674 #else
675 lis r10, MD_RESETVAL@h
676 #endif
677 #ifndef CONFIG_8xx_COPYBACK
678 oris r10, r10, MD_WTDEF@h
679 #endif
680 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
682 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
683 * we can load the instruction and data TLB registers with the
684 * same values.
685 */
686 lis r8, KERNELBASE@h /* Create vaddr for TLB */
687 ori r8, r8, MI_EVALID /* Mark it valid */
688 mtspr SPRN_MI_EPN, r8
689 mtspr SPRN_MD_EPN, r8
690 li r8, MI_PS8MEG /* Set 8M byte page */
691 ori r8, r8, MI_SVALID /* Make it valid */
692 mtspr SPRN_MI_TWC, r8
693 mtspr SPRN_MD_TWC, r8
694 li r8, MI_BOOTINIT /* Create RPN for address 0 */
695 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
696 mtspr SPRN_MD_RPN, r8
697 lis r8, MI_Kp@h /* Set the protection mode */
698 mtspr SPRN_MI_AP, r8
699 mtspr SPRN_MD_AP, r8
701 /* Map another 8 MByte at the IMMR to get the processor
702 * internal registers (among other things).
703 */
704 #ifdef CONFIG_PIN_TLB
705 addi r10, r10, 0x0100
706 mtspr SPRN_MD_CTR, r10
707 #endif
708 mfspr r9, 638 /* Get current IMMR */
709 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
711 mr r8, r9 /* Create vaddr for TLB */
712 ori r8, r8, MD_EVALID /* Mark it valid */
713 mtspr SPRN_MD_EPN, r8
714 li r8, MD_PS8MEG /* Set 8M byte page */
715 ori r8, r8, MD_SVALID /* Make it valid */
716 mtspr SPRN_MD_TWC, r8
717 mr r8, r9 /* Create paddr for TLB */
718 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
719 mtspr SPRN_MD_RPN, r8
721 #ifdef CONFIG_PIN_TLB
722 /* Map two more 8M kernel data pages.
723 */
724 addi r10, r10, 0x0100
725 mtspr SPRN_MD_CTR, r10
727 lis r8, KERNELBASE@h /* Create vaddr for TLB */
728 addis r8, r8, 0x0080 /* Add 8M */
729 ori r8, r8, MI_EVALID /* Mark it valid */
730 mtspr SPRN_MD_EPN, r8
731 li r9, MI_PS8MEG /* Set 8M byte page */
732 ori r9, r9, MI_SVALID /* Make it valid */
733 mtspr SPRN_MD_TWC, r9
734 li r11, MI_BOOTINIT /* Create RPN for address 0 */
735 addis r11, r11, 0x0080 /* Add 8M */
736 mtspr SPRN_MD_RPN, r11
738 addis r8, r8, 0x0080 /* Add 8M */
739 mtspr SPRN_MD_EPN, r8
740 mtspr SPRN_MD_TWC, r9
741 addis r11, r11, 0x0080 /* Add 8M */
742 mtspr SPRN_MD_RPN, r11
743 #endif
745 /* Since the cache is enabled according to the information we
746 * just loaded into the TLB, invalidate and enable the caches here.
747 * We should probably check/set other modes....later.
748 */
749 lis r8, IDC_INVALL@h
750 mtspr SPRN_IC_CST, r8
751 mtspr SPRN_DC_CST, r8
752 lis r8, IDC_ENABLE@h
753 mtspr SPRN_IC_CST, r8
754 #ifdef CONFIG_8xx_COPYBACK
755 mtspr SPRN_DC_CST, r8
756 #else
757 /* For a debug option, I left this here to easily enable
758 * the write through cache mode
759 */
760 lis r8, DC_SFWT@h
761 mtspr SPRN_DC_CST, r8
762 lis r8, IDC_ENABLE@h
763 mtspr SPRN_DC_CST, r8
764 #endif
765 blr
768 /*
769 * Set up to use a given MMU context.
770 * r3 is context number, r4 is PGD pointer.
771 *
772 * We place the physical address of the new task page directory loaded
773 * into the MMU base register, and set the ASID compare register with
774 * the new "context."
775 */
776 _GLOBAL(set_context)
778 #ifdef CONFIG_BDI_SWITCH
779 /* Context switch the PTE pointer for the Abatron BDI2000.
780 * The PGDIR is passed as second argument.
781 */
782 lis r5, KERNELBASE@h
783 lwz r5, 0xf0(r5)
784 stw r4, 0x4(r5)
785 #endif
787 #ifdef CONFIG_8xx_CPU6
788 lis r6, cpu6_errata_word@h
789 ori r6, r6, cpu6_errata_word@l
790 tophys (r4, r4)
791 li r7, 0x3980
792 stw r7, 12(r6)
793 lwz r7, 12(r6)
794 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
795 li r7, 0x3380
796 stw r7, 12(r6)
797 lwz r7, 12(r6)
798 mtspr SPRN_M_CASID, r3 /* Update context */
799 #else
800 mtspr SPRN_M_CASID,r3 /* Update context */
801 tophys (r4, r4)
802 mtspr SPRN_M_TWB, r4 /* and pgd */
803 #endif
804 SYNC
805 blr
807 #ifdef CONFIG_8xx_CPU6
808 /* It's here because it is unique to the 8xx.
809 * It is important we get called with interrupts disabled. I used to
810 * do that, but it appears that all code that calls this already had
811 * interrupt disabled.
812 */
813 .globl set_dec_cpu6
814 set_dec_cpu6:
815 lis r7, cpu6_errata_word@h
816 ori r7, r7, cpu6_errata_word@l
817 li r4, 0x2c00
818 stw r4, 8(r7)
819 lwz r4, 8(r7)
820 mtspr 22, r3 /* Update Decrementer */
821 SYNC
822 blr
823 #endif
825 /*
826 * We put a few things here that have to be page-aligned.
827 * This stuff goes at the beginning of the data segment,
828 * which is page-aligned.
829 */
830 .data
831 .globl sdata
832 sdata:
833 .globl empty_zero_page
834 empty_zero_page:
835 .space 4096
837 .globl swapper_pg_dir
838 swapper_pg_dir:
839 .space 4096
841 /* Room for two PTE table poiners, usually the kernel and current user
842 * pointer to their respective root page table (pgdir).
843 */
844 abatron_pteptrs:
845 .space 8
847 #ifdef CONFIG_8xx_CPU6
848 .globl cpu6_errata_word
849 cpu6_errata_word:
850 .space 16
851 #endif