arch/powerpc/platforms/82xx/pq2ads.h

   1 /*
   2  * PQ2/mpc8260 board-specific stuff
   3  *
   4  * A collection of structures, addresses, and values associated with
   5  * the Freescale MPC8260ADS/MPC8266ADS-PCI boards.
   6  * Copied from the RPX-Classic and SBS8260 stuff.
   7  *
   8  * Author: Vitaly Bordug <vbordug@ru.mvista.com>
   9  *
  10  * Originally written by Dan Malek for Motorola MPC8260 family
  11  *
  12  * Copyright (c) 2001 Dan Malek <dan@embeddedalley.com>
  13  * Copyright (c) 2006 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  */
  20
  21 #ifdef __KERNEL__
  22 #ifndef __MACH_ADS8260_DEFS
  23 #define __MACH_ADS8260_DEFS
  24
  25 #include <linux/seq_file.h>
  26
  27 /* Backword-compatibility stuff for the drivers */
  28 #define CPM_MAP_ADDR            ((uint)0xf0000000)
  29 #define CPM_IRQ_OFFSET 0
  30
  31 /* The ADS8260 has 16, 32-bit wide control/status registers, accessed
  32  * only on word boundaries.
  33  * Not all are used (yet), or are interesting to us (yet).
  34  */
  35
  36 /* Things of interest in the CSR.
  37  */
  38 #define BCSR0_LED0              ((uint)0x02000000)      /* 0 == on */
  39 #define BCSR0_LED1              ((uint)0x01000000)      /* 0 == on */
  40 #define BCSR1_FETHIEN           ((uint)0x08000000)      /* 0 == enable*/
  41 #define BCSR1_FETH_RST          ((uint)0x04000000)      /* 0 == reset */
  42 #define BCSR1_RS232_EN1         ((uint)0x02000000)      /* 0 ==enable */
  43 #define BCSR1_RS232_EN2         ((uint)0x01000000)      /* 0 ==enable */
  44 #define BCSR3_FETHIEN2          ((uint)0x10000000)      /* 0 == enable*/
  45 #define BCSR3_FETH2_RST         ((uint)0x80000000)      /* 0 == reset */
  46
  47 /* cpm serial driver works with constants below */
  48
  49 #define SIU_INT_SMC1            ((uint)0x04+CPM_IRQ_OFFSET)
  50 #define SIU_INT_SMC2            ((uint)0x05+CPM_IRQ_OFFSET)
  51 #define SIU_INT_SCC1            ((uint)0x28+CPM_IRQ_OFFSET)
  52 #define SIU_INT_SCC2            ((uint)0x29+CPM_IRQ_OFFSET)
  53 #define SIU_INT_SCC3            ((uint)0x2a+CPM_IRQ_OFFSET)
  54 #define SIU_INT_SCC4            ((uint)0x2b+CPM_IRQ_OFFSET)
  55
  56 #endif /* __MACH_ADS8260_DEFS */
  57 #endif /* __KERNEL__ */