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kbuild: Fix instrumentation removal breakage on avr32
[wrt350n-kernel.git] / drivers / ata / ahci.c
blob27c8d56111c2959b8d7f6cb64b9dccd85cee8a39
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54 static void ahci_disable_alpm(struct ata_port *ap);
55
56 enum {
57 AHCI_PCI_BAR = 5,
58 AHCI_MAX_PORTS = 32,
59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
61 AHCI_USE_CLUSTERING = 1,
62 AHCI_MAX_CMDS = 32,
63 AHCI_CMD_SZ = 32,
64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
65 AHCI_RX_FIS_SZ = 256,
66 AHCI_CMD_TBL_CDB = 0x40,
67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
75 AHCI_CMD_PREFETCH = (1 << 7),
76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
82
83 board_ahci = 0,
84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
88
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
151 PORT_IRQ_PHYRDY |
152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
160
161 /* PORT_CMD bits */
162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
169 PORT_CMD_CLO = (1 << 3), /* Command list override */
170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
178
179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
188
189 /* ap->flags bits */
190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
196
197 ICH_MAP = 0x90, /* ICH MAP register */
198 };
199
200 struct ahci_cmd_hdr {
201 __le32 opts;
202 __le32 status;
203 __le32 tbl_addr;
204 __le32 tbl_addr_hi;
205 __le32 reserved[4];
206 };
207
208 struct ahci_sg {
209 __le32 addr;
210 __le32 addr_hi;
211 __le32 reserved;
212 __le32 flags_size;
213 };
214
215 struct ahci_host_priv {
216 unsigned int flags; /* AHCI_HFLAG_* */
217 u32 cap; /* cap to use */
218 u32 port_map; /* port map to use */
219 u32 saved_cap; /* saved initial cap */
220 u32 saved_port_map; /* saved initial port_map */
221 };
222
223 struct ahci_port_priv {
224 struct ata_link *active_link;
225 struct ahci_cmd_hdr *cmd_slot;
226 dma_addr_t cmd_slot_dma;
227 void *cmd_tbl;
228 dma_addr_t cmd_tbl_dma;
229 void *rx_fis;
230 dma_addr_t rx_fis_dma;
231 /* for NCQ spurious interrupt analysis */
232 unsigned int ncq_saw_d2h:1;
233 unsigned int ncq_saw_dmas:1;
234 unsigned int ncq_saw_sdb:1;
235 u32 intr_mask; /* interrupts to enable */
236 };
237
238 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
239 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
240 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
241 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
242 static void ahci_irq_clear(struct ata_port *ap);
243 static int ahci_port_start(struct ata_port *ap);
244 static void ahci_port_stop(struct ata_port *ap);
245 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
246 static void ahci_qc_prep(struct ata_queued_cmd *qc);
247 static u8 ahci_check_status(struct ata_port *ap);
248 static void ahci_freeze(struct ata_port *ap);
249 static void ahci_thaw(struct ata_port *ap);
250 static void ahci_pmp_attach(struct ata_port *ap);
251 static void ahci_pmp_detach(struct ata_port *ap);
252 static void ahci_error_handler(struct ata_port *ap);
253 static void ahci_vt8251_error_handler(struct ata_port *ap);
254 static void ahci_p5wdh_error_handler(struct ata_port *ap);
255 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
256 static int ahci_port_resume(struct ata_port *ap);
257 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
258 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
259 u32 opts);
260 #ifdef CONFIG_PM
261 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
262 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
263 static int ahci_pci_device_resume(struct pci_dev *pdev);
264 #endif
265
266 static struct class_device_attribute *ahci_shost_attrs[] = {
267 &class_device_attr_link_power_management_policy,
268 NULL
269 };
270
271 static struct scsi_host_template ahci_sht = {
272 .module = THIS_MODULE,
273 .name = DRV_NAME,
274 .ioctl = ata_scsi_ioctl,
275 .queuecommand = ata_scsi_queuecmd,
276 .change_queue_depth = ata_scsi_change_queue_depth,
277 .can_queue = AHCI_MAX_CMDS - 1,
278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = AHCI_MAX_SG,
280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = AHCI_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = AHCI_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
286 .slave_destroy = ata_scsi_slave_destroy,
287 .bios_param = ata_std_bios_param,
288 .shost_attrs = ahci_shost_attrs,
289 };
290
291 static const struct ata_port_operations ahci_ops = {
292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
298 .qc_defer = sata_pmp_qc_defer_cmd_switch,
299 .qc_prep = ahci_qc_prep,
300 .qc_issue = ahci_qc_issue,
301
302 .irq_clear = ahci_irq_clear,
303
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
306
307 .freeze = ahci_freeze,
308 .thaw = ahci_thaw,
309
310 .error_handler = ahci_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
312
313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
315
316 #ifdef CONFIG_PM
317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
319 #endif
320 .enable_pm = ahci_enable_alpm,
321 .disable_pm = ahci_disable_alpm,
322
323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
325 };
326
327 static const struct ata_port_operations ahci_vt8251_ops = {
328 .check_status = ahci_check_status,
329 .check_altstatus = ahci_check_status,
330 .dev_select = ata_noop_dev_select,
331
332 .tf_read = ahci_tf_read,
333
334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337
338 .irq_clear = ahci_irq_clear,
339
340 .scr_read = ahci_scr_read,
341 .scr_write = ahci_scr_write,
342
343 .freeze = ahci_freeze,
344 .thaw = ahci_thaw,
345
346 .error_handler = ahci_vt8251_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348
349 .pmp_attach = ahci_pmp_attach,
350 .pmp_detach = ahci_pmp_detach,
351
352 #ifdef CONFIG_PM
353 .port_suspend = ahci_port_suspend,
354 .port_resume = ahci_port_resume,
355 #endif
356
357 .port_start = ahci_port_start,
358 .port_stop = ahci_port_stop,
359 };
360
361 static const struct ata_port_operations ahci_p5wdh_ops = {
362 .check_status = ahci_check_status,
363 .check_altstatus = ahci_check_status,
364 .dev_select = ata_noop_dev_select,
365
366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
372 .irq_clear = ahci_irq_clear,
373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386 #ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389 #endif
390
391 .port_start = ahci_port_start,
392 .port_stop = ahci_port_stop,
393 };
394
395 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
396
397 static const struct ata_port_info ahci_port_info[] = {
398 /* board_ahci */
399 {
400 .flags = AHCI_FLAG_COMMON,
401 .link_flags = AHCI_LFLAG_COMMON,
402 .pio_mask = 0x1f, /* pio0-4 */
403 .udma_mask = ATA_UDMA6,
404 .port_ops = &ahci_ops,
405 },
406 /* board_ahci_vt8251 */
407 {
408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
409 .flags = AHCI_FLAG_COMMON,
410 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
411 .pio_mask = 0x1f, /* pio0-4 */
412 .udma_mask = ATA_UDMA6,
413 .port_ops = &ahci_vt8251_ops,
414 },
415 /* board_ahci_ign_iferr */
416 {
417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
419 .link_flags = AHCI_LFLAG_COMMON,
420 .pio_mask = 0x1f, /* pio0-4 */
421 .udma_mask = ATA_UDMA6,
422 .port_ops = &ahci_ops,
423 },
424 /* board_ahci_sb600 */
425 {
426 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
427 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
428 .flags = AHCI_FLAG_COMMON,
429 .link_flags = AHCI_LFLAG_COMMON,
430 .pio_mask = 0x1f, /* pio0-4 */
431 .udma_mask = ATA_UDMA6,
432 .port_ops = &ahci_ops,
433 },
434 /* board_ahci_mv */
435 {
436 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_MV_PATA),
438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
439 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
440 .link_flags = AHCI_LFLAG_COMMON,
441 .pio_mask = 0x1f, /* pio0-4 */
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &ahci_ops,
444 },
445 };
446
447 static const struct pci_device_id ahci_pci_tbl[] = {
448 /* Intel */
449 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
450 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
451 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
452 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
453 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
454 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
455 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
457 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
458 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
459 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
461 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
462 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
463 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
464 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
468 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
469 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
473 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
474 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
476 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
477 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
478 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
479 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
480
481 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
482 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
483 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
484
485 /* ATI */
486 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
487 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
489 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
490 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
491 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
492 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
493
494 /* VIA */
495 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
496 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
497
498 /* NVIDIA */
499 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
503 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
504 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
505 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
506 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
507 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
511 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
518 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
547 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
555
556 /* SiS */
557 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
558 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
559 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
560
561 /* Marvell */
562 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
563
564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
567
568 { } /* terminate list */
569 };
570
571
572 static struct pci_driver ahci_pci_driver = {
573 .name = DRV_NAME,
574 .id_table = ahci_pci_tbl,
575 .probe = ahci_init_one,
576 .remove = ata_pci_remove_one,
577 #ifdef CONFIG_PM
578 .suspend = ahci_pci_device_suspend,
579 .resume = ahci_pci_device_resume,
580 #endif
581 };
582
583
584 static inline int ahci_nr_ports(u32 cap)
585 {
586 return (cap & 0x1f) + 1;
587 }
588
589 static inline void __iomem *__ahci_port_base(struct ata_host *host,
590 unsigned int port_no)
591 {
592 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
593
594 return mmio + 0x100 + (port_no * 0x80);
595 }
596
597 static inline void __iomem *ahci_port_base(struct ata_port *ap)
598 {
599 return __ahci_port_base(ap->host, ap->port_no);
600 }
601
602 static void ahci_enable_ahci(void __iomem *mmio)
603 {
604 u32 tmp;
605
606 /* turn on AHCI_EN */
607 tmp = readl(mmio + HOST_CTL);
608 if (!(tmp & HOST_AHCI_EN)) {
609 tmp |= HOST_AHCI_EN;
610 writel(tmp, mmio + HOST_CTL);
611 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
612 WARN_ON(!(tmp & HOST_AHCI_EN));
613 }
614 }
615
616 /**
617 * ahci_save_initial_config - Save and fixup initial config values
618 * @pdev: target PCI device
619 * @hpriv: host private area to store config values
620 *
621 * Some registers containing configuration info might be setup by
622 * BIOS and might be cleared on reset. This function saves the
623 * initial values of those registers into @hpriv such that they
624 * can be restored after controller reset.
625 *
626 * If inconsistent, config values are fixed up by this function.
627 *
628 * LOCKING:
629 * None.
630 */
631 static void ahci_save_initial_config(struct pci_dev *pdev,
632 struct ahci_host_priv *hpriv)
633 {
634 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
635 u32 cap, port_map;
636 int i;
637
638 /* make sure AHCI mode is enabled before accessing CAP */
639 ahci_enable_ahci(mmio);
640
641 /* Values prefixed with saved_ are written back to host after
642 * reset. Values without are used for driver operation.
643 */
644 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
645 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
646
647 /* some chips have errata preventing 64bit use */
648 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
649 dev_printk(KERN_INFO, &pdev->dev,
650 "controller can't do 64bit DMA, forcing 32bit\n");
651 cap &= ~HOST_CAP_64;
652 }
653
654 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
655 dev_printk(KERN_INFO, &pdev->dev,
656 "controller can't do NCQ, turning off CAP_NCQ\n");
657 cap &= ~HOST_CAP_NCQ;
658 }
659
660 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
661 dev_printk(KERN_INFO, &pdev->dev,
662 "controller can't do PMP, turning off CAP_PMP\n");
663 cap &= ~HOST_CAP_PMP;
664 }
665
666 /*
667 * Temporary Marvell 6145 hack: PATA port presence
668 * is asserted through the standard AHCI port
669 * presence register, as bit 4 (counting from 0)
670 */
671 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
672 dev_printk(KERN_ERR, &pdev->dev,
673 "MV_AHCI HACK: port_map %x -> %x\n",
674 hpriv->port_map,
675 hpriv->port_map & 0xf);
676
677 port_map &= 0xf;
678 }
679
680 /* cross check port_map and cap.n_ports */
681 if (port_map) {
682 u32 tmp_port_map = port_map;
683 int n_ports = ahci_nr_ports(cap);
684
685 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
686 if (tmp_port_map & (1 << i)) {
687 n_ports--;
688 tmp_port_map &= ~(1 << i);
689 }
690 }
691
692 /* If n_ports and port_map are inconsistent, whine and
693 * clear port_map and let it be generated from n_ports.
694 */
695 if (n_ports || tmp_port_map) {
696 dev_printk(KERN_WARNING, &pdev->dev,
697 "nr_ports (%u) and implemented port map "
698 "(0x%x) don't match, using nr_ports\n",
699 ahci_nr_ports(cap), port_map);
700 port_map = 0;
701 }
702 }
703
704 /* fabricate port_map from cap.nr_ports */
705 if (!port_map) {
706 port_map = (1 << ahci_nr_ports(cap)) - 1;
707 dev_printk(KERN_WARNING, &pdev->dev,
708 "forcing PORTS_IMPL to 0x%x\n", port_map);
709
710 /* write the fixed up value to the PI register */
711 hpriv->saved_port_map = port_map;
712 }
713
714 /* record values to use during operation */
715 hpriv->cap = cap;
716 hpriv->port_map = port_map;
717 }
718
719 /**
720 * ahci_restore_initial_config - Restore initial config
721 * @host: target ATA host
722 *
723 * Restore initial config stored by ahci_save_initial_config().
724 *
725 * LOCKING:
726 * None.
727 */
728 static void ahci_restore_initial_config(struct ata_host *host)
729 {
730 struct ahci_host_priv *hpriv = host->private_data;
731 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
732
733 writel(hpriv->saved_cap, mmio + HOST_CAP);
734 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
735 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
736 }
737
738 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
739 {
740 static const int offset[] = {
741 [SCR_STATUS] = PORT_SCR_STAT,
742 [SCR_CONTROL] = PORT_SCR_CTL,
743 [SCR_ERROR] = PORT_SCR_ERR,
744 [SCR_ACTIVE] = PORT_SCR_ACT,
745 [SCR_NOTIFICATION] = PORT_SCR_NTF,
746 };
747 struct ahci_host_priv *hpriv = ap->host->private_data;
748
749 if (sc_reg < ARRAY_SIZE(offset) &&
750 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
751 return offset[sc_reg];
752 return 0;
753 }
754
755 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
756 {
757 void __iomem *port_mmio = ahci_port_base(ap);
758 int offset = ahci_scr_offset(ap, sc_reg);
759
760 if (offset) {
761 *val = readl(port_mmio + offset);
762 return 0;
763 }
764 return -EINVAL;
765 }
766
767 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
768 {
769 void __iomem *port_mmio = ahci_port_base(ap);
770 int offset = ahci_scr_offset(ap, sc_reg);
771
772 if (offset) {
773 writel(val, port_mmio + offset);
774 return 0;
775 }
776 return -EINVAL;
777 }
778
779 static void ahci_start_engine(struct ata_port *ap)
780 {
781 void __iomem *port_mmio = ahci_port_base(ap);
782 u32 tmp;
783
784 /* start DMA */
785 tmp = readl(port_mmio + PORT_CMD);
786 tmp |= PORT_CMD_START;
787 writel(tmp, port_mmio + PORT_CMD);
788 readl(port_mmio + PORT_CMD); /* flush */
789 }
790
791 static int ahci_stop_engine(struct ata_port *ap)
792 {
793 void __iomem *port_mmio = ahci_port_base(ap);
794 u32 tmp;
795
796 tmp = readl(port_mmio + PORT_CMD);
797
798 /* check if the HBA is idle */
799 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
800 return 0;
801
802 /* setting HBA to idle */
803 tmp &= ~PORT_CMD_START;
804 writel(tmp, port_mmio + PORT_CMD);
805
806 /* wait for engine to stop. This could be as long as 500 msec */
807 tmp = ata_wait_register(port_mmio + PORT_CMD,
808 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
809 if (tmp & PORT_CMD_LIST_ON)
810 return -EIO;
811
812 return 0;
813 }
814
815 static void ahci_start_fis_rx(struct ata_port *ap)
816 {
817 void __iomem *port_mmio = ahci_port_base(ap);
818 struct ahci_host_priv *hpriv = ap->host->private_data;
819 struct ahci_port_priv *pp = ap->private_data;
820 u32 tmp;
821
822 /* set FIS registers */
823 if (hpriv->cap & HOST_CAP_64)
824 writel((pp->cmd_slot_dma >> 16) >> 16,
825 port_mmio + PORT_LST_ADDR_HI);
826 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
827
828 if (hpriv->cap & HOST_CAP_64)
829 writel((pp->rx_fis_dma >> 16) >> 16,
830 port_mmio + PORT_FIS_ADDR_HI);
831 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
832
833 /* enable FIS reception */
834 tmp = readl(port_mmio + PORT_CMD);
835 tmp |= PORT_CMD_FIS_RX;
836 writel(tmp, port_mmio + PORT_CMD);
837
838 /* flush */
839 readl(port_mmio + PORT_CMD);
840 }
841
842 static int ahci_stop_fis_rx(struct ata_port *ap)
843 {
844 void __iomem *port_mmio = ahci_port_base(ap);
845 u32 tmp;
846
847 /* disable FIS reception */
848 tmp = readl(port_mmio + PORT_CMD);
849 tmp &= ~PORT_CMD_FIS_RX;
850 writel(tmp, port_mmio + PORT_CMD);
851
852 /* wait for completion, spec says 500ms, give it 1000 */
853 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
854 PORT_CMD_FIS_ON, 10, 1000);
855 if (tmp & PORT_CMD_FIS_ON)
856 return -EBUSY;
857
858 return 0;
859 }
860
861 static void ahci_power_up(struct ata_port *ap)
862 {
863 struct ahci_host_priv *hpriv = ap->host->private_data;
864 void __iomem *port_mmio = ahci_port_base(ap);
865 u32 cmd;
866
867 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
868
869 /* spin up device */
870 if (hpriv->cap & HOST_CAP_SSS) {
871 cmd |= PORT_CMD_SPIN_UP;
872 writel(cmd, port_mmio + PORT_CMD);
873 }
874
875 /* wake up link */
876 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
877 }
878
879 static void ahci_disable_alpm(struct ata_port *ap)
880 {
881 struct ahci_host_priv *hpriv = ap->host->private_data;
882 void __iomem *port_mmio = ahci_port_base(ap);
883 u32 cmd;
884 struct ahci_port_priv *pp = ap->private_data;
885
886 /* IPM bits should be disabled by libata-core */
887 /* get the existing command bits */
888 cmd = readl(port_mmio + PORT_CMD);
889
890 /* disable ALPM and ASP */
891 cmd &= ~PORT_CMD_ASP;
892 cmd &= ~PORT_CMD_ALPE;
893
894 /* force the interface back to active */
895 cmd |= PORT_CMD_ICC_ACTIVE;
896
897 /* write out new cmd value */
898 writel(cmd, port_mmio + PORT_CMD);
899 cmd = readl(port_mmio + PORT_CMD);
900
901 /* wait 10ms to be sure we've come out of any low power state */
902 msleep(10);
903
904 /* clear out any PhyRdy stuff from interrupt status */
905 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
906
907 /* go ahead and clean out PhyRdy Change from Serror too */
908 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
909
910 /*
911 * Clear flag to indicate that we should ignore all PhyRdy
912 * state changes
913 */
914 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
915
916 /*
917 * Enable interrupts on Phy Ready.
918 */
919 pp->intr_mask |= PORT_IRQ_PHYRDY;
920 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
921
922 /*
923 * don't change the link pm policy - we can be called
924 * just to turn of link pm temporarily
925 */
926 }
927
928 static int ahci_enable_alpm(struct ata_port *ap,
929 enum link_pm policy)
930 {
931 struct ahci_host_priv *hpriv = ap->host->private_data;
932 void __iomem *port_mmio = ahci_port_base(ap);
933 u32 cmd;
934 struct ahci_port_priv *pp = ap->private_data;
935 u32 asp;
936
937 /* Make sure the host is capable of link power management */
938 if (!(hpriv->cap & HOST_CAP_ALPM))
939 return -EINVAL;
940
941 switch (policy) {
942 case MAX_PERFORMANCE:
943 case NOT_AVAILABLE:
944 /*
945 * if we came here with NOT_AVAILABLE,
946 * it just means this is the first time we
947 * have tried to enable - default to max performance,
948 * and let the user go to lower power modes on request.
949 */
950 ahci_disable_alpm(ap);
951 return 0;
952 case MIN_POWER:
953 /* configure HBA to enter SLUMBER */
954 asp = PORT_CMD_ASP;
955 break;
956 case MEDIUM_POWER:
957 /* configure HBA to enter PARTIAL */
958 asp = 0;
959 break;
960 default:
961 return -EINVAL;
962 }
963
964 /*
965 * Disable interrupts on Phy Ready. This keeps us from
966 * getting woken up due to spurious phy ready interrupts
967 * TBD - Hot plug should be done via polling now, is
968 * that even supported?
969 */
970 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
971 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
972
973 /*
974 * Set a flag to indicate that we should ignore all PhyRdy
975 * state changes since these can happen now whenever we
976 * change link state
977 */
978 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
979
980 /* get the existing command bits */
981 cmd = readl(port_mmio + PORT_CMD);
982
983 /*
984 * Set ASP based on Policy
985 */
986 cmd |= asp;
987
988 /*
989 * Setting this bit will instruct the HBA to aggressively
990 * enter a lower power link state when it's appropriate and
991 * based on the value set above for ASP
992 */
993 cmd |= PORT_CMD_ALPE;
994
995 /* write out new cmd value */
996 writel(cmd, port_mmio + PORT_CMD);
997 cmd = readl(port_mmio + PORT_CMD);
998
999 /* IPM bits should be set by libata-core */
1000 return 0;
1001 }
1002
1003 #ifdef CONFIG_PM
1004 static void ahci_power_down(struct ata_port *ap)
1005 {
1006 struct ahci_host_priv *hpriv = ap->host->private_data;
1007 void __iomem *port_mmio = ahci_port_base(ap);
1008 u32 cmd, scontrol;
1009
1010 if (!(hpriv->cap & HOST_CAP_SSS))
1011 return;
1012
1013 /* put device into listen mode, first set PxSCTL.DET to 0 */
1014 scontrol = readl(port_mmio + PORT_SCR_CTL);
1015 scontrol &= ~0xf;
1016 writel(scontrol, port_mmio + PORT_SCR_CTL);
1017
1018 /* then set PxCMD.SUD to 0 */
1019 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1020 cmd &= ~PORT_CMD_SPIN_UP;
1021 writel(cmd, port_mmio + PORT_CMD);
1022 }
1023 #endif
1024
1025 static void ahci_start_port(struct ata_port *ap)
1026 {
1027 /* enable FIS reception */
1028 ahci_start_fis_rx(ap);
1029
1030 /* enable DMA */
1031 ahci_start_engine(ap);
1032 }
1033
1034 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1035 {
1036 int rc;
1037
1038 /* disable DMA */
1039 rc = ahci_stop_engine(ap);
1040 if (rc) {
1041 *emsg = "failed to stop engine";
1042 return rc;
1043 }
1044
1045 /* disable FIS reception */
1046 rc = ahci_stop_fis_rx(ap);
1047 if (rc) {
1048 *emsg = "failed stop FIS RX";
1049 return rc;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static int ahci_reset_controller(struct ata_host *host)
1056 {
1057 struct pci_dev *pdev = to_pci_dev(host->dev);
1058 struct ahci_host_priv *hpriv = host->private_data;
1059 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1060 u32 tmp;
1061
1062 /* we must be in AHCI mode, before using anything
1063 * AHCI-specific, such as HOST_RESET.
1064 */
1065 ahci_enable_ahci(mmio);
1066
1067 /* global controller reset */
1068 tmp = readl(mmio + HOST_CTL);
1069 if ((tmp & HOST_RESET) == 0) {
1070 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1071 readl(mmio + HOST_CTL); /* flush */
1072 }
1073
1074 /* reset must complete within 1 second, or
1075 * the hardware should be considered fried.
1076 */
1077 ssleep(1);
1078
1079 tmp = readl(mmio + HOST_CTL);
1080 if (tmp & HOST_RESET) {
1081 dev_printk(KERN_ERR, host->dev,
1082 "controller reset failed (0x%x)\n", tmp);
1083 return -EIO;
1084 }
1085
1086 /* turn on AHCI mode */
1087 ahci_enable_ahci(mmio);
1088
1089 /* some registers might be cleared on reset. restore initial values */
1090 ahci_restore_initial_config(host);
1091
1092 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1093 u16 tmp16;
1094
1095 /* configure PCS */
1096 pci_read_config_word(pdev, 0x92, &tmp16);
1097 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1098 tmp16 |= hpriv->port_map;
1099 pci_write_config_word(pdev, 0x92, tmp16);
1100 }
1101 }
1102
1103 return 0;
1104 }
1105
1106 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1107 int port_no, void __iomem *mmio,
1108 void __iomem *port_mmio)
1109 {
1110 const char *emsg = NULL;
1111 int rc;
1112 u32 tmp;
1113
1114 /* make sure port is not active */
1115 rc = ahci_deinit_port(ap, &emsg);
1116 if (rc)
1117 dev_printk(KERN_WARNING, &pdev->dev,
1118 "%s (%d)\n", emsg, rc);
1119
1120 /* clear SError */
1121 tmp = readl(port_mmio + PORT_SCR_ERR);
1122 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1123 writel(tmp, port_mmio + PORT_SCR_ERR);
1124
1125 /* clear port IRQ */
1126 tmp = readl(port_mmio + PORT_IRQ_STAT);
1127 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1128 if (tmp)
1129 writel(tmp, port_mmio + PORT_IRQ_STAT);
1130
1131 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1132 }
1133
1134 static void ahci_init_controller(struct ata_host *host)
1135 {
1136 struct ahci_host_priv *hpriv = host->private_data;
1137 struct pci_dev *pdev = to_pci_dev(host->dev);
1138 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1139 int i;
1140 void __iomem *port_mmio;
1141 u32 tmp;
1142
1143 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1144 port_mmio = __ahci_port_base(host, 4);
1145
1146 writel(0, port_mmio + PORT_IRQ_MASK);
1147
1148 /* clear port IRQ */
1149 tmp = readl(port_mmio + PORT_IRQ_STAT);
1150 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1151 if (tmp)
1152 writel(tmp, port_mmio + PORT_IRQ_STAT);
1153 }
1154
1155 for (i = 0; i < host->n_ports; i++) {
1156 struct ata_port *ap = host->ports[i];
1157
1158 port_mmio = ahci_port_base(ap);
1159 if (ata_port_is_dummy(ap))
1160 continue;
1161
1162 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1163 }
1164
1165 tmp = readl(mmio + HOST_CTL);
1166 VPRINTK("HOST_CTL 0x%x\n", tmp);
1167 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1168 tmp = readl(mmio + HOST_CTL);
1169 VPRINTK("HOST_CTL 0x%x\n", tmp);
1170 }
1171
1172 static unsigned int ahci_dev_classify(struct ata_port *ap)
1173 {
1174 void __iomem *port_mmio = ahci_port_base(ap);
1175 struct ata_taskfile tf;
1176 u32 tmp;
1177
1178 tmp = readl(port_mmio + PORT_SIG);
1179 tf.lbah = (tmp >> 24) & 0xff;
1180 tf.lbam = (tmp >> 16) & 0xff;
1181 tf.lbal = (tmp >> 8) & 0xff;
1182 tf.nsect = (tmp) & 0xff;
1183
1184 return ata_dev_classify(&tf);
1185 }
1186
1187 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1188 u32 opts)
1189 {
1190 dma_addr_t cmd_tbl_dma;
1191
1192 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1193
1194 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1195 pp->cmd_slot[tag].status = 0;
1196 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1197 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1198 }
1199
1200 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1201 {
1202 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1203 struct ahci_host_priv *hpriv = ap->host->private_data;
1204 u32 tmp;
1205 int busy, rc;
1206
1207 /* do we need to kick the port? */
1208 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1209 if (!busy && !force_restart)
1210 return 0;
1211
1212 /* stop engine */
1213 rc = ahci_stop_engine(ap);
1214 if (rc)
1215 goto out_restart;
1216
1217 /* need to do CLO? */
1218 if (!busy) {
1219 rc = 0;
1220 goto out_restart;
1221 }
1222
1223 if (!(hpriv->cap & HOST_CAP_CLO)) {
1224 rc = -EOPNOTSUPP;
1225 goto out_restart;
1226 }
1227
1228 /* perform CLO */
1229 tmp = readl(port_mmio + PORT_CMD);
1230 tmp |= PORT_CMD_CLO;
1231 writel(tmp, port_mmio + PORT_CMD);
1232
1233 rc = 0;
1234 tmp = ata_wait_register(port_mmio + PORT_CMD,
1235 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1236 if (tmp & PORT_CMD_CLO)
1237 rc = -EIO;
1238
1239 /* restart engine */
1240 out_restart:
1241 ahci_start_engine(ap);
1242 return rc;
1243 }
1244
1245 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1246 struct ata_taskfile *tf, int is_cmd, u16 flags,
1247 unsigned long timeout_msec)
1248 {
1249 const u32 cmd_fis_len = 5; /* five dwords */
1250 struct ahci_port_priv *pp = ap->private_data;
1251 void __iomem *port_mmio = ahci_port_base(ap);
1252 u8 *fis = pp->cmd_tbl;
1253 u32 tmp;
1254
1255 /* prep the command */
1256 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1257 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1258
1259 /* issue & wait */
1260 writel(1, port_mmio + PORT_CMD_ISSUE);
1261
1262 if (timeout_msec) {
1263 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1264 1, timeout_msec);
1265 if (tmp & 0x1) {
1266 ahci_kick_engine(ap, 1);
1267 return -EBUSY;
1268 }
1269 } else
1270 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1271
1272 return 0;
1273 }
1274
1275 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1276 int pmp, unsigned long deadline)
1277 {
1278 struct ata_port *ap = link->ap;
1279 const char *reason = NULL;
1280 unsigned long now, msecs;
1281 struct ata_taskfile tf;
1282 int rc;
1283
1284 DPRINTK("ENTER\n");
1285
1286 if (ata_link_offline(link)) {
1287 DPRINTK("PHY reports no device\n");
1288 *class = ATA_DEV_NONE;
1289 return 0;
1290 }
1291
1292 /* prepare for SRST (AHCI-1.1 10.4.1) */
1293 rc = ahci_kick_engine(ap, 1);
1294 if (rc && rc != -EOPNOTSUPP)
1295 ata_link_printk(link, KERN_WARNING,
1296 "failed to reset engine (errno=%d)\n", rc);
1297
1298 ata_tf_init(link->device, &tf);
1299
1300 /* issue the first D2H Register FIS */
1301 msecs = 0;
1302 now = jiffies;
1303 if (time_after(now, deadline))
1304 msecs = jiffies_to_msecs(deadline - now);
1305
1306 tf.ctl |= ATA_SRST;
1307 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1308 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1309 rc = -EIO;
1310 reason = "1st FIS failed";
1311 goto fail;
1312 }
1313
1314 /* spec says at least 5us, but be generous and sleep for 1ms */
1315 msleep(1);
1316
1317 /* issue the second D2H Register FIS */
1318 tf.ctl &= ~ATA_SRST;
1319 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1320
1321 /* wait a while before checking status */
1322 ata_wait_after_reset(ap, deadline);
1323
1324 rc = ata_wait_ready(ap, deadline);
1325 /* link occupied, -ENODEV too is an error */
1326 if (rc) {
1327 reason = "device not ready";
1328 goto fail;
1329 }
1330 *class = ahci_dev_classify(ap);
1331
1332 DPRINTK("EXIT, class=%u\n", *class);
1333 return 0;
1334
1335 fail:
1336 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1337 return rc;
1338 }
1339
1340 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1341 unsigned long deadline)
1342 {
1343 int pmp = 0;
1344
1345 if (link->ap->flags & ATA_FLAG_PMP)
1346 pmp = SATA_PMP_CTRL_PORT;
1347
1348 return ahci_do_softreset(link, class, pmp, deadline);
1349 }
1350
1351 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1352 unsigned long deadline)
1353 {
1354 struct ata_port *ap = link->ap;
1355 struct ahci_port_priv *pp = ap->private_data;
1356 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1357 struct ata_taskfile tf;
1358 int rc;
1359
1360 DPRINTK("ENTER\n");
1361
1362 ahci_stop_engine(ap);
1363
1364 /* clear D2H reception area to properly wait for D2H FIS */
1365 ata_tf_init(link->device, &tf);
1366 tf.command = 0x80;
1367 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1368
1369 rc = sata_std_hardreset(link, class, deadline);
1370
1371 ahci_start_engine(ap);
1372
1373 if (rc == 0 && ata_link_online(link))
1374 *class = ahci_dev_classify(ap);
1375 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1376 *class = ATA_DEV_NONE;
1377
1378 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1379 return rc;
1380 }
1381
1382 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1383 unsigned long deadline)
1384 {
1385 struct ata_port *ap = link->ap;
1386 u32 serror;
1387 int rc;
1388
1389 DPRINTK("ENTER\n");
1390
1391 ahci_stop_engine(ap);
1392
1393 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1394 deadline);
1395
1396 /* vt8251 needs SError cleared for the port to operate */
1397 ahci_scr_read(ap, SCR_ERROR, &serror);
1398 ahci_scr_write(ap, SCR_ERROR, serror);
1399
1400 ahci_start_engine(ap);
1401
1402 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1403
1404 /* vt8251 doesn't clear BSY on signature FIS reception,
1405 * request follow-up softreset.
1406 */
1407 return rc ?: -EAGAIN;
1408 }
1409
1410 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1411 unsigned long deadline)
1412 {
1413 struct ata_port *ap = link->ap;
1414 struct ahci_port_priv *pp = ap->private_data;
1415 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1416 struct ata_taskfile tf;
1417 int rc;
1418
1419 ahci_stop_engine(ap);
1420
1421 /* clear D2H reception area to properly wait for D2H FIS */
1422 ata_tf_init(link->device, &tf);
1423 tf.command = 0x80;
1424 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1425
1426 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1427 deadline);
1428
1429 ahci_start_engine(ap);
1430
1431 if (rc || ata_link_offline(link))
1432 return rc;
1433
1434 /* spec mandates ">= 2ms" before checking status */
1435 msleep(150);
1436
1437 /* The pseudo configuration device on SIMG4726 attached to
1438 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1439 * hardreset if no device is attached to the first downstream
1440 * port && the pseudo device locks up on SRST w/ PMP==0. To
1441 * work around this, wait for !BSY only briefly. If BSY isn't
1442 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1443 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1444 *
1445 * Wait for two seconds. Devices attached to downstream port
1446 * which can't process the following IDENTIFY after this will
1447 * have to be reset again. For most cases, this should
1448 * suffice while making probing snappish enough.
1449 */
1450 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1451 if (rc)
1452 ahci_kick_engine(ap, 0);
1453
1454 return 0;
1455 }
1456
1457 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1458 {
1459 struct ata_port *ap = link->ap;
1460 void __iomem *port_mmio = ahci_port_base(ap);
1461 u32 new_tmp, tmp;
1462
1463 ata_std_postreset(link, class);
1464
1465 /* Make sure port's ATAPI bit is set appropriately */
1466 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1467 if (*class == ATA_DEV_ATAPI)
1468 new_tmp |= PORT_CMD_ATAPI;
1469 else
1470 new_tmp &= ~PORT_CMD_ATAPI;
1471 if (new_tmp != tmp) {
1472 writel(new_tmp, port_mmio + PORT_CMD);
1473 readl(port_mmio + PORT_CMD); /* flush */
1474 }
1475 }
1476
1477 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1478 unsigned long deadline)
1479 {
1480 return ahci_do_softreset(link, class, link->pmp, deadline);
1481 }
1482
1483 static u8 ahci_check_status(struct ata_port *ap)
1484 {
1485 void __iomem *mmio = ap->ioaddr.cmd_addr;
1486
1487 return readl(mmio + PORT_TFDATA) & 0xFF;
1488 }
1489
1490 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1491 {
1492 struct ahci_port_priv *pp = ap->private_data;
1493 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1494
1495 ata_tf_from_fis(d2h_fis, tf);
1496 }
1497
1498 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1499 {
1500 struct scatterlist *sg;
1501 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1502 unsigned int si;
1503
1504 VPRINTK("ENTER\n");
1505
1506 /*
1507 * Next, the S/G list.
1508 */
1509 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1510 dma_addr_t addr = sg_dma_address(sg);
1511 u32 sg_len = sg_dma_len(sg);
1512
1513 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1514 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1515 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1516 }
1517
1518 return si;
1519 }
1520
1521 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1522 {
1523 struct ata_port *ap = qc->ap;
1524 struct ahci_port_priv *pp = ap->private_data;
1525 int is_atapi = ata_is_atapi(qc->tf.protocol);
1526 void *cmd_tbl;
1527 u32 opts;
1528 const u32 cmd_fis_len = 5; /* five dwords */
1529 unsigned int n_elem;
1530
1531 /*
1532 * Fill in command table information. First, the header,
1533 * a SATA Register - Host to Device command FIS.
1534 */
1535 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1536
1537 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1538 if (is_atapi) {
1539 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1540 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1541 }
1542
1543 n_elem = 0;
1544 if (qc->flags & ATA_QCFLAG_DMAMAP)
1545 n_elem = ahci_fill_sg(qc, cmd_tbl);
1546
1547 /*
1548 * Fill in command slot information.
1549 */
1550 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1551 if (qc->tf.flags & ATA_TFLAG_WRITE)
1552 opts |= AHCI_CMD_WRITE;
1553 if (is_atapi)
1554 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1555
1556 ahci_fill_cmd_slot(pp, qc->tag, opts);
1557 }
1558
1559 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1560 {
1561 struct ahci_host_priv *hpriv = ap->host->private_data;
1562 struct ahci_port_priv *pp = ap->private_data;
1563 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1564 struct ata_link *link = NULL;
1565 struct ata_queued_cmd *active_qc;
1566 struct ata_eh_info *active_ehi;
1567 u32 serror;
1568
1569 /* determine active link */
1570 ata_port_for_each_link(link, ap)
1571 if (ata_link_active(link))
1572 break;
1573 if (!link)
1574 link = &ap->link;
1575
1576 active_qc = ata_qc_from_tag(ap, link->active_tag);
1577 active_ehi = &link->eh_info;
1578
1579 /* record irq stat */
1580 ata_ehi_clear_desc(host_ehi);
1581 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1582
1583 /* AHCI needs SError cleared; otherwise, it might lock up */
1584 ahci_scr_read(ap, SCR_ERROR, &serror);
1585 ahci_scr_write(ap, SCR_ERROR, serror);
1586 host_ehi->serror |= serror;
1587
1588 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1589 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1590 irq_stat &= ~PORT_IRQ_IF_ERR;
1591
1592 if (irq_stat & PORT_IRQ_TF_ERR) {
1593 /* If qc is active, charge it; otherwise, the active
1594 * link. There's no active qc on NCQ errors. It will
1595 * be determined by EH by reading log page 10h.
1596 */
1597 if (active_qc)
1598 active_qc->err_mask |= AC_ERR_DEV;
1599 else
1600 active_ehi->err_mask |= AC_ERR_DEV;
1601
1602 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1603 host_ehi->serror &= ~SERR_INTERNAL;
1604 }
1605
1606 if (irq_stat & PORT_IRQ_UNK_FIS) {
1607 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1608
1609 active_ehi->err_mask |= AC_ERR_HSM;
1610 active_ehi->action |= ATA_EH_SOFTRESET;
1611 ata_ehi_push_desc(active_ehi,
1612 "unknown FIS %08x %08x %08x %08x" ,
1613 unk[0], unk[1], unk[2], unk[3]);
1614 }
1615
1616 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1617 active_ehi->err_mask |= AC_ERR_HSM;
1618 active_ehi->action |= ATA_EH_SOFTRESET;
1619 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1620 }
1621
1622 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1623 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1624 host_ehi->action |= ATA_EH_SOFTRESET;
1625 ata_ehi_push_desc(host_ehi, "host bus error");
1626 }
1627
1628 if (irq_stat & PORT_IRQ_IF_ERR) {
1629 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1630 host_ehi->action |= ATA_EH_SOFTRESET;
1631 ata_ehi_push_desc(host_ehi, "interface fatal error");
1632 }
1633
1634 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1635 ata_ehi_hotplugged(host_ehi);
1636 ata_ehi_push_desc(host_ehi, "%s",
1637 irq_stat & PORT_IRQ_CONNECT ?
1638 "connection status changed" : "PHY RDY changed");
1639 }
1640
1641 /* okay, let's hand over to EH */
1642
1643 if (irq_stat & PORT_IRQ_FREEZE)
1644 ata_port_freeze(ap);
1645 else
1646 ata_port_abort(ap);
1647 }
1648
1649 static void ahci_port_intr(struct ata_port *ap)
1650 {
1651 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1652 struct ata_eh_info *ehi = &ap->link.eh_info;
1653 struct ahci_port_priv *pp = ap->private_data;
1654 struct ahci_host_priv *hpriv = ap->host->private_data;
1655 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1656 u32 status, qc_active;
1657 int rc;
1658
1659 status = readl(port_mmio + PORT_IRQ_STAT);
1660 writel(status, port_mmio + PORT_IRQ_STAT);
1661
1662 /* ignore BAD_PMP while resetting */
1663 if (unlikely(resetting))
1664 status &= ~PORT_IRQ_BAD_PMP;
1665
1666 /* If we are getting PhyRdy, this is
1667 * just a power state change, we should
1668 * clear out this, plus the PhyRdy/Comm
1669 * Wake bits from Serror
1670 */
1671 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1672 (status & PORT_IRQ_PHYRDY)) {
1673 status &= ~PORT_IRQ_PHYRDY;
1674 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1675 }
1676
1677 if (unlikely(status & PORT_IRQ_ERROR)) {
1678 ahci_error_intr(ap, status);
1679 return;
1680 }
1681
1682 if (status & PORT_IRQ_SDB_FIS) {
1683 /* If SNotification is available, leave notification
1684 * handling to sata_async_notification(). If not,
1685 * emulate it by snooping SDB FIS RX area.
1686 *
1687 * Snooping FIS RX area is probably cheaper than
1688 * poking SNotification but some constrollers which
1689 * implement SNotification, ICH9 for example, don't
1690 * store AN SDB FIS into receive area.
1691 */
1692 if (hpriv->cap & HOST_CAP_SNTF)
1693 sata_async_notification(ap);
1694 else {
1695 /* If the 'N' bit in word 0 of the FIS is set,
1696 * we just received asynchronous notification.
1697 * Tell libata about it.
1698 */
1699 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1700 u32 f0 = le32_to_cpu(f[0]);
1701
1702 if (f0 & (1 << 15))
1703 sata_async_notification(ap);
1704 }
1705 }
1706
1707 /* pp->active_link is valid iff any command is in flight */
1708 if (ap->qc_active && pp->active_link->sactive)
1709 qc_active = readl(port_mmio + PORT_SCR_ACT);
1710 else
1711 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1712
1713 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1714
1715 /* while resetting, invalid completions are expected */
1716 if (unlikely(rc < 0 && !resetting)) {
1717 ehi->err_mask |= AC_ERR_HSM;
1718 ehi->action |= ATA_EH_SOFTRESET;
1719 ata_port_freeze(ap);
1720 }
1721 }
1722
1723 static void ahci_irq_clear(struct ata_port *ap)
1724 {
1725 /* TODO */
1726 }
1727
1728 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1729 {
1730 struct ata_host *host = dev_instance;
1731 struct ahci_host_priv *hpriv;
1732 unsigned int i, handled = 0;
1733 void __iomem *mmio;
1734 u32 irq_stat, irq_ack = 0;
1735
1736 VPRINTK("ENTER\n");
1737
1738 hpriv = host->private_data;
1739 mmio = host->iomap[AHCI_PCI_BAR];
1740
1741 /* sigh. 0xffffffff is a valid return from h/w */
1742 irq_stat = readl(mmio + HOST_IRQ_STAT);
1743 irq_stat &= hpriv->port_map;
1744 if (!irq_stat)
1745 return IRQ_NONE;
1746
1747 spin_lock(&host->lock);
1748
1749 for (i = 0; i < host->n_ports; i++) {
1750 struct ata_port *ap;
1751
1752 if (!(irq_stat & (1 << i)))
1753 continue;
1754
1755 ap = host->ports[i];
1756 if (ap) {
1757 ahci_port_intr(ap);
1758 VPRINTK("port %u\n", i);
1759 } else {
1760 VPRINTK("port %u (no irq)\n", i);
1761 if (ata_ratelimit())
1762 dev_printk(KERN_WARNING, host->dev,
1763 "interrupt on disabled port %u\n", i);
1764 }
1765
1766 irq_ack |= (1 << i);
1767 }
1768
1769 if (irq_ack) {
1770 writel(irq_ack, mmio + HOST_IRQ_STAT);
1771 handled = 1;
1772 }
1773
1774 spin_unlock(&host->lock);
1775
1776 VPRINTK("EXIT\n");
1777
1778 return IRQ_RETVAL(handled);
1779 }
1780
1781 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1782 {
1783 struct ata_port *ap = qc->ap;
1784 void __iomem *port_mmio = ahci_port_base(ap);
1785 struct ahci_port_priv *pp = ap->private_data;
1786
1787 /* Keep track of the currently active link. It will be used
1788 * in completion path to determine whether NCQ phase is in
1789 * progress.
1790 */
1791 pp->active_link = qc->dev->link;
1792
1793 if (qc->tf.protocol == ATA_PROT_NCQ)
1794 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1795 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1796 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1797
1798 return 0;
1799 }
1800
1801 static void ahci_freeze(struct ata_port *ap)
1802 {
1803 void __iomem *port_mmio = ahci_port_base(ap);
1804
1805 /* turn IRQ off */
1806 writel(0, port_mmio + PORT_IRQ_MASK);
1807 }
1808
1809 static void ahci_thaw(struct ata_port *ap)
1810 {
1811 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1812 void __iomem *port_mmio = ahci_port_base(ap);
1813 u32 tmp;
1814 struct ahci_port_priv *pp = ap->private_data;
1815
1816 /* clear IRQ */
1817 tmp = readl(port_mmio + PORT_IRQ_STAT);
1818 writel(tmp, port_mmio + PORT_IRQ_STAT);
1819 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1820
1821 /* turn IRQ back on */
1822 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1823 }
1824
1825 static void ahci_error_handler(struct ata_port *ap)
1826 {
1827 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1828 /* restart engine */
1829 ahci_stop_engine(ap);
1830 ahci_start_engine(ap);
1831 }
1832
1833 /* perform recovery */
1834 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1835 ahci_hardreset, ahci_postreset,
1836 sata_pmp_std_prereset, ahci_pmp_softreset,
1837 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1838 }
1839
1840 static void ahci_vt8251_error_handler(struct ata_port *ap)
1841 {
1842 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1843 /* restart engine */
1844 ahci_stop_engine(ap);
1845 ahci_start_engine(ap);
1846 }
1847
1848 /* perform recovery */
1849 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1850 ahci_postreset);
1851 }
1852
1853 static void ahci_p5wdh_error_handler(struct ata_port *ap)
1854 {
1855 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1856 /* restart engine */
1857 ahci_stop_engine(ap);
1858 ahci_start_engine(ap);
1859 }
1860
1861 /* perform recovery */
1862 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1863 ahci_postreset);
1864 }
1865
1866 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1867 {
1868 struct ata_port *ap = qc->ap;
1869
1870 /* make DMA engine forget about the failed command */
1871 if (qc->flags & ATA_QCFLAG_FAILED)
1872 ahci_kick_engine(ap, 1);
1873 }
1874
1875 static void ahci_pmp_attach(struct ata_port *ap)
1876 {
1877 void __iomem *port_mmio = ahci_port_base(ap);
1878 struct ahci_port_priv *pp = ap->private_data;
1879 u32 cmd;
1880
1881 cmd = readl(port_mmio + PORT_CMD);
1882 cmd |= PORT_CMD_PMP;
1883 writel(cmd, port_mmio + PORT_CMD);
1884
1885 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1886 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1887 }
1888
1889 static void ahci_pmp_detach(struct ata_port *ap)
1890 {
1891 void __iomem *port_mmio = ahci_port_base(ap);
1892 struct ahci_port_priv *pp = ap->private_data;
1893 u32 cmd;
1894
1895 cmd = readl(port_mmio + PORT_CMD);
1896 cmd &= ~PORT_CMD_PMP;
1897 writel(cmd, port_mmio + PORT_CMD);
1898
1899 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1900 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1901 }
1902
1903 static int ahci_port_resume(struct ata_port *ap)
1904 {
1905 ahci_power_up(ap);
1906 ahci_start_port(ap);
1907
1908 if (ap->nr_pmp_links)
1909 ahci_pmp_attach(ap);
1910 else
1911 ahci_pmp_detach(ap);
1912
1913 return 0;
1914 }
1915
1916 #ifdef CONFIG_PM
1917 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1918 {
1919 const char *emsg = NULL;
1920 int rc;
1921
1922 rc = ahci_deinit_port(ap, &emsg);
1923 if (rc == 0)
1924 ahci_power_down(ap);
1925 else {
1926 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1927 ahci_start_port(ap);
1928 }
1929
1930 return rc;
1931 }
1932
1933 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1934 {
1935 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1936 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1937 u32 ctl;
1938
1939 if (mesg.event == PM_EVENT_SUSPEND) {
1940 /* AHCI spec rev1.1 section 8.3.3:
1941 * Software must disable interrupts prior to requesting a
1942 * transition of the HBA to D3 state.
1943 */
1944 ctl = readl(mmio + HOST_CTL);
1945 ctl &= ~HOST_IRQ_EN;
1946 writel(ctl, mmio + HOST_CTL);
1947 readl(mmio + HOST_CTL); /* flush */
1948 }
1949
1950 return ata_pci_device_suspend(pdev, mesg);
1951 }
1952
1953 static int ahci_pci_device_resume(struct pci_dev *pdev)
1954 {
1955 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1956 int rc;
1957
1958 rc = ata_pci_device_do_resume(pdev);
1959 if (rc)
1960 return rc;
1961
1962 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1963 rc = ahci_reset_controller(host);
1964 if (rc)
1965 return rc;
1966
1967 ahci_init_controller(host);
1968 }
1969
1970 ata_host_resume(host);
1971
1972 return 0;
1973 }
1974 #endif
1975
1976 static int ahci_port_start(struct ata_port *ap)
1977 {
1978 struct device *dev = ap->host->dev;
1979 struct ahci_port_priv *pp;
1980 void *mem;
1981 dma_addr_t mem_dma;
1982 int rc;
1983
1984 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1985 if (!pp)
1986 return -ENOMEM;
1987
1988 rc = ata_pad_alloc(ap, dev);
1989 if (rc)
1990 return rc;
1991
1992 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1993 GFP_KERNEL);
1994 if (!mem)
1995 return -ENOMEM;
1996 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1997
1998 /*
1999 * First item in chunk of DMA memory: 32-slot command table,
2000 * 32 bytes each in size
2001 */
2002 pp->cmd_slot = mem;
2003 pp->cmd_slot_dma = mem_dma;
2004
2005 mem += AHCI_CMD_SLOT_SZ;
2006 mem_dma += AHCI_CMD_SLOT_SZ;
2007
2008 /*
2009 * Second item: Received-FIS area
2010 */
2011 pp->rx_fis = mem;
2012 pp->rx_fis_dma = mem_dma;
2013
2014 mem += AHCI_RX_FIS_SZ;
2015 mem_dma += AHCI_RX_FIS_SZ;
2016
2017 /*
2018 * Third item: data area for storing a single command
2019 * and its scatter-gather table
2020 */
2021 pp->cmd_tbl = mem;
2022 pp->cmd_tbl_dma = mem_dma;
2023
2024 /*
2025 * Save off initial list of interrupts to be enabled.
2026 * This could be changed later
2027 */
2028 pp->intr_mask = DEF_PORT_IRQ;
2029
2030 ap->private_data = pp;
2031
2032 /* engage engines, captain */
2033 return ahci_port_resume(ap);
2034 }
2035
2036 static void ahci_port_stop(struct ata_port *ap)
2037 {
2038 const char *emsg = NULL;
2039 int rc;
2040
2041 /* de-initialize port */
2042 rc = ahci_deinit_port(ap, &emsg);
2043 if (rc)
2044 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2045 }
2046
2047 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2048 {
2049 int rc;
2050
2051 if (using_dac &&
2052 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2053 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2054 if (rc) {
2055 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2056 if (rc) {
2057 dev_printk(KERN_ERR, &pdev->dev,
2058 "64-bit DMA enable failed\n");
2059 return rc;
2060 }
2061 }
2062 } else {
2063 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2064 if (rc) {
2065 dev_printk(KERN_ERR, &pdev->dev,
2066 "32-bit DMA enable failed\n");
2067 return rc;
2068 }
2069 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2070 if (rc) {
2071 dev_printk(KERN_ERR, &pdev->dev,
2072 "32-bit consistent DMA enable failed\n");
2073 return rc;
2074 }
2075 }
2076 return 0;
2077 }
2078
2079 static void ahci_print_info(struct ata_host *host)
2080 {
2081 struct ahci_host_priv *hpriv = host->private_data;
2082 struct pci_dev *pdev = to_pci_dev(host->dev);
2083 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2084 u32 vers, cap, impl, speed;
2085 const char *speed_s;
2086 u16 cc;
2087 const char *scc_s;
2088
2089 vers = readl(mmio + HOST_VERSION);
2090 cap = hpriv->cap;
2091 impl = hpriv->port_map;
2092
2093 speed = (cap >> 20) & 0xf;
2094 if (speed == 1)
2095 speed_s = "1.5";
2096 else if (speed == 2)
2097 speed_s = "3";
2098 else
2099 speed_s = "?";
2100
2101 pci_read_config_word(pdev, 0x0a, &cc);
2102 if (cc == PCI_CLASS_STORAGE_IDE)
2103 scc_s = "IDE";
2104 else if (cc == PCI_CLASS_STORAGE_SATA)
2105 scc_s = "SATA";
2106 else if (cc == PCI_CLASS_STORAGE_RAID)
2107 scc_s = "RAID";
2108 else
2109 scc_s = "unknown";
2110
2111 dev_printk(KERN_INFO, &pdev->dev,
2112 "AHCI %02x%02x.%02x%02x "
2113 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2114 ,
2115
2116 (vers >> 24) & 0xff,
2117 (vers >> 16) & 0xff,
2118 (vers >> 8) & 0xff,
2119 vers & 0xff,
2120
2121 ((cap >> 8) & 0x1f) + 1,
2122 (cap & 0x1f) + 1,
2123 speed_s,
2124 impl,
2125 scc_s);
2126
2127 dev_printk(KERN_INFO, &pdev->dev,
2128 "flags: "
2129 "%s%s%s%s%s%s%s"
2130 "%s%s%s%s%s%s%s\n"
2131 ,
2132
2133 cap & (1 << 31) ? "64bit " : "",
2134 cap & (1 << 30) ? "ncq " : "",
2135 cap & (1 << 29) ? "sntf " : "",
2136 cap & (1 << 28) ? "ilck " : "",
2137 cap & (1 << 27) ? "stag " : "",
2138 cap & (1 << 26) ? "pm " : "",
2139 cap & (1 << 25) ? "led " : "",
2140
2141 cap & (1 << 24) ? "clo " : "",
2142 cap & (1 << 19) ? "nz " : "",
2143 cap & (1 << 18) ? "only " : "",
2144 cap & (1 << 17) ? "pmp " : "",
2145 cap & (1 << 15) ? "pio " : "",
2146 cap & (1 << 14) ? "slum " : "",
2147 cap & (1 << 13) ? "part " : ""
2148 );
2149 }
2150
2151 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2152 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2153 * support PMP and the 4726 either directly exports the device
2154 * attached to the first downstream port or acts as a hardware storage
2155 * controller and emulate a single ATA device (can be RAID 0/1 or some
2156 * other configuration).
2157 *
2158 * When there's no device attached to the first downstream port of the
2159 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2160 * configure the 4726. However, ATA emulation of the device is very
2161 * lame. It doesn't send signature D2H Reg FIS after the initial
2162 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2163 *
2164 * The following function works around the problem by always using
2165 * hardreset on the port and not depending on receiving signature FIS
2166 * afterward. If signature FIS isn't received soon, ATA class is
2167 * assumed without follow-up softreset.
2168 */
2169 static void ahci_p5wdh_workaround(struct ata_host *host)
2170 {
2171 static struct dmi_system_id sysids[] = {
2172 {
2173 .ident = "P5W DH Deluxe",
2174 .matches = {
2175 DMI_MATCH(DMI_SYS_VENDOR,
2176 "ASUSTEK COMPUTER INC"),
2177 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2178 },
2179 },
2180 { }
2181 };
2182 struct pci_dev *pdev = to_pci_dev(host->dev);
2183
2184 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2185 dmi_check_system(sysids)) {
2186 struct ata_port *ap = host->ports[1];
2187
2188 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2189 "Deluxe on-board SIMG4726 workaround\n");
2190
2191 ap->ops = &ahci_p5wdh_ops;
2192 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2193 }
2194 }
2195
2196 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2197 {
2198 static int printed_version;
2199 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2200 const struct ata_port_info *ppi[] = { &pi, NULL };
2201 struct device *dev = &pdev->dev;
2202 struct ahci_host_priv *hpriv;
2203 struct ata_host *host;
2204 int i, rc;
2205
2206 VPRINTK("ENTER\n");
2207
2208 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2209
2210 if (!printed_version++)
2211 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2212
2213 /* acquire resources */
2214 rc = pcim_enable_device(pdev);
2215 if (rc)
2216 return rc;
2217
2218 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2219 if (rc == -EBUSY)
2220 pcim_pin_device(pdev);
2221 if (rc)
2222 return rc;
2223
2224 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2225 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2226 u8 map;
2227
2228 /* ICH6s share the same PCI ID for both piix and ahci
2229 * modes. Enabling ahci mode while MAP indicates
2230 * combined mode is a bad idea. Yield to ata_piix.
2231 */
2232 pci_read_config_byte(pdev, ICH_MAP, &map);
2233 if (map & 0x3) {
2234 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2235 "combined mode, can't enable AHCI mode\n");
2236 return -ENODEV;
2237 }
2238 }
2239
2240 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2241 if (!hpriv)
2242 return -ENOMEM;
2243 hpriv->flags |= (unsigned long)pi.private_data;
2244
2245 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2246 pci_intx(pdev, 1);
2247
2248 /* save initial config */
2249 ahci_save_initial_config(pdev, hpriv);
2250
2251 /* prepare host */
2252 if (hpriv->cap & HOST_CAP_NCQ)
2253 pi.flags |= ATA_FLAG_NCQ;
2254
2255 if (hpriv->cap & HOST_CAP_PMP)
2256 pi.flags |= ATA_FLAG_PMP;
2257
2258 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2259 if (!host)
2260 return -ENOMEM;
2261 host->iomap = pcim_iomap_table(pdev);
2262 host->private_data = hpriv;
2263
2264 for (i = 0; i < host->n_ports; i++) {
2265 struct ata_port *ap = host->ports[i];
2266 void __iomem *port_mmio = ahci_port_base(ap);
2267
2268 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2269 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2270 0x100 + ap->port_no * 0x80, "port");
2271
2272 /* set initial link pm policy */
2273 ap->pm_policy = NOT_AVAILABLE;
2274
2275 /* standard SATA port setup */
2276 if (hpriv->port_map & (1 << i))
2277 ap->ioaddr.cmd_addr = port_mmio;
2278
2279 /* disabled/not-implemented port */
2280 else
2281 ap->ops = &ata_dummy_port_ops;
2282 }
2283
2284 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2285 ahci_p5wdh_workaround(host);
2286
2287 /* initialize adapter */
2288 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2289 if (rc)
2290 return rc;
2291
2292 rc = ahci_reset_controller(host);
2293 if (rc)
2294 return rc;
2295
2296 ahci_init_controller(host);
2297 ahci_print_info(host);
2298
2299 pci_set_master(pdev);
2300 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2301 &ahci_sht);
2302 }
2303
2304 static int __init ahci_init(void)
2305 {
2306 return pci_register_driver(&ahci_pci_driver);
2307 }
2308
2309 static void __exit ahci_exit(void)
2310 {
2311 pci_unregister_driver(&ahci_pci_driver);
2312 }
2313
2314
2315 MODULE_AUTHOR("Jeff Garzik");
2316 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2317 MODULE_LICENSE("GPL");
2318 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2319 MODULE_VERSION(DRV_VERSION);
2320
2321 module_init(ahci_init);
2322 module_exit(ahci_exit);
WRT350N Kernel Patches