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kbuild: Fix instrumentation removal breakage on avr32
[wrt350n-kernel.git] / drivers / ata / pata_scc.c
blob55055b27524cfa9efd2771a96d1d44fe7dcc624b
1 /*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ata/ata_piix.c:
7 * Copyright 2003-2005 Red Hat Inc
8 * Copyright 2003-2005 Jeff Garzik
9 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
12 *
13 * and drivers/ata/ahci.c:
14 * Copyright 2004-2005 Red Hat, Inc.
15 *
16 * and drivers/ata/libata-core.c:
17 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
18 * Copyright 2003-2004 Jeff Garzik
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License along
31 * with this program; if not, write to the Free Software Foundation, Inc.,
32 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "pata_scc"
46 #define DRV_VERSION "0.3"
47
48 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
49
50 /* PCI BARs */
51 #define SCC_CTRL_BAR 0
52 #define SCC_BMID_BAR 1
53
54 /* offset of CTRL registers */
55 #define SCC_CTL_PIOSHT 0x000
56 #define SCC_CTL_PIOCT 0x004
57 #define SCC_CTL_MDMACT 0x008
58 #define SCC_CTL_MCRCST 0x00C
59 #define SCC_CTL_SDMACT 0x010
60 #define SCC_CTL_SCRCST 0x014
61 #define SCC_CTL_UDENVT 0x018
62 #define SCC_CTL_TDVHSEL 0x020
63 #define SCC_CTL_MODEREG 0x024
64 #define SCC_CTL_ECMODE 0xF00
65 #define SCC_CTL_MAEA0 0xF50
66 #define SCC_CTL_MAEC0 0xF54
67 #define SCC_CTL_CCKCTRL 0xFF0
68
69 /* offset of BMID registers */
70 #define SCC_DMA_CMD 0x000
71 #define SCC_DMA_STATUS 0x004
72 #define SCC_DMA_TABLE_OFS 0x008
73 #define SCC_DMA_INTMASK 0x010
74 #define SCC_DMA_INTST 0x014
75 #define SCC_DMA_PTERADD 0x018
76 #define SCC_REG_CMD_ADDR 0x020
77 #define SCC_REG_DATA 0x000
78 #define SCC_REG_ERR 0x004
79 #define SCC_REG_FEATURE 0x004
80 #define SCC_REG_NSECT 0x008
81 #define SCC_REG_LBAL 0x00C
82 #define SCC_REG_LBAM 0x010
83 #define SCC_REG_LBAH 0x014
84 #define SCC_REG_DEVICE 0x018
85 #define SCC_REG_STATUS 0x01C
86 #define SCC_REG_CMD 0x01C
87 #define SCC_REG_ALTSTATUS 0x020
88
89 /* register value */
90 #define TDVHSEL_MASTER 0x00000001
91 #define TDVHSEL_SLAVE 0x00000004
92
93 #define MODE_JCUSFEN 0x00000080
94
95 #define ECMODE_VALUE 0x01
96
97 #define CCKCTRL_ATARESET 0x00040000
98 #define CCKCTRL_BUFCNT 0x00020000
99 #define CCKCTRL_CRST 0x00010000
100 #define CCKCTRL_OCLKEN 0x00000100
101 #define CCKCTRL_ATACLKOEN 0x00000002
102 #define CCKCTRL_LCLKEN 0x00000001
103
104 #define QCHCD_IOS_SS 0x00000001
105
106 #define QCHSD_STPDIAG 0x00020000
107
108 #define INTMASK_MSK 0xD1000012
109 #define INTSTS_SERROR 0x80000000
110 #define INTSTS_PRERR 0x40000000
111 #define INTSTS_RERR 0x10000000
112 #define INTSTS_ICERR 0x01000000
113 #define INTSTS_BMSINT 0x00000010
114 #define INTSTS_BMHE 0x00000008
115 #define INTSTS_IOIRQS 0x00000004
116 #define INTSTS_INTRQ 0x00000002
117 #define INTSTS_ACTEINT 0x00000001
118
119
120 /* PIO transfer mode table */
121 /* JCHST */
122 static const unsigned long JCHSTtbl[2][7] = {
123 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
124 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
125 };
126
127 /* JCHHT */
128 static const unsigned long JCHHTtbl[2][7] = {
129 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
130 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
131 };
132
133 /* JCHCT */
134 static const unsigned long JCHCTtbl[2][7] = {
135 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
136 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
137 };
138
139 /* DMA transfer mode table */
140 /* JCHDCTM/JCHDCTS */
141 static const unsigned long JCHDCTxtbl[2][7] = {
142 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
143 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
144 };
145
146 /* JCSTWTM/JCSTWTS */
147 static const unsigned long JCSTWTxtbl[2][7] = {
148 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
149 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
150 };
151
152 /* JCTSS */
153 static const unsigned long JCTSStbl[2][7] = {
154 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
155 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
156 };
157
158 /* JCENVT */
159 static const unsigned long JCENVTtbl[2][7] = {
160 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
161 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
162 };
163
164 /* JCACTSELS/JCACTSELM */
165 static const unsigned long JCACTSELtbl[2][7] = {
166 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
167 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
168 };
169
170 static const struct pci_device_id scc_pci_tbl[] = {
171 {PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 { } /* terminate list */
174 };
175
176 /**
177 * scc_set_piomode - Initialize host controller PATA PIO timings
178 * @ap: Port whose timings we are configuring
179 * @adev: um
180 *
181 * Set PIO mode for device.
182 *
183 * LOCKING:
184 * None (inherited from caller).
185 */
186
187 static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
188 {
189 unsigned int pio = adev->pio_mode - XFER_PIO_0;
190 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
191 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
192 void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
193 void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
194 unsigned long reg;
195 int offset;
196
197 reg = in_be32(cckctrl_port);
198 if (reg & CCKCTRL_ATACLKOEN)
199 offset = 1; /* 133MHz */
200 else
201 offset = 0; /* 100MHz */
202
203 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
204 out_be32(piosht_port, reg);
205 reg = JCHCTtbl[offset][pio];
206 out_be32(pioct_port, reg);
207 }
208
209 /**
210 * scc_set_dmamode - Initialize host controller PATA DMA timings
211 * @ap: Port whose timings we are configuring
212 * @adev: um
213 * @udma: udma mode, 0 - 6
214 *
215 * Set UDMA mode for device.
216 *
217 * LOCKING:
218 * None (inherited from caller).
219 */
220
221 static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
222 {
223 unsigned int udma = adev->dma_mode;
224 unsigned int is_slave = (adev->devno != 0);
225 u8 speed = udma;
226 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
227 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
228 void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
229 void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
230 void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
231 void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
232 void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
233 void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
234 int offset, idx;
235
236 if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
237 offset = 1; /* 133MHz */
238 else
239 offset = 0; /* 100MHz */
240
241 if (speed >= XFER_UDMA_0)
242 idx = speed - XFER_UDMA_0;
243 else
244 return;
245
246 if (is_slave) {
247 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
248 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
249 out_be32(tdvhsel_port,
250 (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
251 } else {
252 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
253 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
254 out_be32(tdvhsel_port,
255 (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
256 }
257 out_be32(udenvt_port,
258 JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
259 }
260
261 unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
262 {
263 /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
264 if (adev->class == ATA_DEV_ATAPI &&
265 (mask & (0xE0 << ATA_SHIFT_UDMA))) {
266 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
267 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
268 }
269 return ata_pci_default_filter(adev, mask);
270 }
271
272 /**
273 * scc_tf_load - send taskfile registers to host controller
274 * @ap: Port to which output is sent
275 * @tf: ATA taskfile register set
276 *
277 * Note: Original code is ata_tf_load().
278 */
279
280 static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
281 {
282 struct ata_ioports *ioaddr = &ap->ioaddr;
283 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
284
285 if (tf->ctl != ap->last_ctl) {
286 out_be32(ioaddr->ctl_addr, tf->ctl);
287 ap->last_ctl = tf->ctl;
288 ata_wait_idle(ap);
289 }
290
291 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
292 out_be32(ioaddr->feature_addr, tf->hob_feature);
293 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
294 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
295 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
296 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
297 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
298 tf->hob_feature,
299 tf->hob_nsect,
300 tf->hob_lbal,
301 tf->hob_lbam,
302 tf->hob_lbah);
303 }
304
305 if (is_addr) {
306 out_be32(ioaddr->feature_addr, tf->feature);
307 out_be32(ioaddr->nsect_addr, tf->nsect);
308 out_be32(ioaddr->lbal_addr, tf->lbal);
309 out_be32(ioaddr->lbam_addr, tf->lbam);
310 out_be32(ioaddr->lbah_addr, tf->lbah);
311 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
312 tf->feature,
313 tf->nsect,
314 tf->lbal,
315 tf->lbam,
316 tf->lbah);
317 }
318
319 if (tf->flags & ATA_TFLAG_DEVICE) {
320 out_be32(ioaddr->device_addr, tf->device);
321 VPRINTK("device 0x%X\n", tf->device);
322 }
323
324 ata_wait_idle(ap);
325 }
326
327 /**
328 * scc_check_status - Read device status reg & clear interrupt
329 * @ap: port where the device is
330 *
331 * Note: Original code is ata_check_status().
332 */
333
334 static u8 scc_check_status (struct ata_port *ap)
335 {
336 return in_be32(ap->ioaddr.status_addr);
337 }
338
339 /**
340 * scc_tf_read - input device's ATA taskfile shadow registers
341 * @ap: Port from which input is read
342 * @tf: ATA taskfile register set for storing input
343 *
344 * Note: Original code is ata_tf_read().
345 */
346
347 static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
348 {
349 struct ata_ioports *ioaddr = &ap->ioaddr;
350
351 tf->command = scc_check_status(ap);
352 tf->feature = in_be32(ioaddr->error_addr);
353 tf->nsect = in_be32(ioaddr->nsect_addr);
354 tf->lbal = in_be32(ioaddr->lbal_addr);
355 tf->lbam = in_be32(ioaddr->lbam_addr);
356 tf->lbah = in_be32(ioaddr->lbah_addr);
357 tf->device = in_be32(ioaddr->device_addr);
358
359 if (tf->flags & ATA_TFLAG_LBA48) {
360 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
361 tf->hob_feature = in_be32(ioaddr->error_addr);
362 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
363 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
364 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
365 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
366 out_be32(ioaddr->ctl_addr, tf->ctl);
367 ap->last_ctl = tf->ctl;
368 }
369 }
370
371 /**
372 * scc_exec_command - issue ATA command to host controller
373 * @ap: port to which command is being issued
374 * @tf: ATA taskfile register set
375 *
376 * Note: Original code is ata_exec_command().
377 */
378
379 static void scc_exec_command (struct ata_port *ap,
380 const struct ata_taskfile *tf)
381 {
382 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
383
384 out_be32(ap->ioaddr.command_addr, tf->command);
385 ata_pause(ap);
386 }
387
388 /**
389 * scc_check_altstatus - Read device alternate status reg
390 * @ap: port where the device is
391 */
392
393 static u8 scc_check_altstatus (struct ata_port *ap)
394 {
395 return in_be32(ap->ioaddr.altstatus_addr);
396 }
397
398 /**
399 * scc_std_dev_select - Select device 0/1 on ATA bus
400 * @ap: ATA channel to manipulate
401 * @device: ATA device (numbered from zero) to select
402 *
403 * Note: Original code is ata_std_dev_select().
404 */
405
406 static void scc_std_dev_select (struct ata_port *ap, unsigned int device)
407 {
408 u8 tmp;
409
410 if (device == 0)
411 tmp = ATA_DEVICE_OBS;
412 else
413 tmp = ATA_DEVICE_OBS | ATA_DEV1;
414
415 out_be32(ap->ioaddr.device_addr, tmp);
416 ata_pause(ap);
417 }
418
419 /**
420 * scc_bmdma_setup - Set up PCI IDE BMDMA transaction
421 * @qc: Info associated with this ATA transaction.
422 *
423 * Note: Original code is ata_bmdma_setup().
424 */
425
426 static void scc_bmdma_setup (struct ata_queued_cmd *qc)
427 {
428 struct ata_port *ap = qc->ap;
429 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
430 u8 dmactl;
431 void __iomem *mmio = ap->ioaddr.bmdma_addr;
432
433 /* load PRD table addr */
434 out_be32(mmio + SCC_DMA_TABLE_OFS, ap->prd_dma);
435
436 /* specify data direction, triple-check start bit is clear */
437 dmactl = in_be32(mmio + SCC_DMA_CMD);
438 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
439 if (!rw)
440 dmactl |= ATA_DMA_WR;
441 out_be32(mmio + SCC_DMA_CMD, dmactl);
442
443 /* issue r/w command */
444 ap->ops->exec_command(ap, &qc->tf);
445 }
446
447 /**
448 * scc_bmdma_start - Start a PCI IDE BMDMA transaction
449 * @qc: Info associated with this ATA transaction.
450 *
451 * Note: Original code is ata_bmdma_start().
452 */
453
454 static void scc_bmdma_start (struct ata_queued_cmd *qc)
455 {
456 struct ata_port *ap = qc->ap;
457 u8 dmactl;
458 void __iomem *mmio = ap->ioaddr.bmdma_addr;
459
460 /* start host DMA transaction */
461 dmactl = in_be32(mmio + SCC_DMA_CMD);
462 out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
463 }
464
465 /**
466 * scc_devchk - PATA device presence detection
467 * @ap: ATA channel to examine
468 * @device: Device to examine (starting at zero)
469 *
470 * Note: Original code is ata_devchk().
471 */
472
473 static unsigned int scc_devchk (struct ata_port *ap,
474 unsigned int device)
475 {
476 struct ata_ioports *ioaddr = &ap->ioaddr;
477 u8 nsect, lbal;
478
479 ap->ops->dev_select(ap, device);
480
481 out_be32(ioaddr->nsect_addr, 0x55);
482 out_be32(ioaddr->lbal_addr, 0xaa);
483
484 out_be32(ioaddr->nsect_addr, 0xaa);
485 out_be32(ioaddr->lbal_addr, 0x55);
486
487 out_be32(ioaddr->nsect_addr, 0x55);
488 out_be32(ioaddr->lbal_addr, 0xaa);
489
490 nsect = in_be32(ioaddr->nsect_addr);
491 lbal = in_be32(ioaddr->lbal_addr);
492
493 if ((nsect == 0x55) && (lbal == 0xaa))
494 return 1; /* we found a device */
495
496 return 0; /* nothing found */
497 }
498
499 /**
500 * scc_bus_post_reset - PATA device post reset
501 *
502 * Note: Original code is ata_bus_post_reset().
503 */
504
505 static int scc_bus_post_reset(struct ata_port *ap, unsigned int devmask,
506 unsigned long deadline)
507 {
508 struct ata_ioports *ioaddr = &ap->ioaddr;
509 unsigned int dev0 = devmask & (1 << 0);
510 unsigned int dev1 = devmask & (1 << 1);
511 int rc;
512
513 /* if device 0 was found in ata_devchk, wait for its
514 * BSY bit to clear
515 */
516 if (dev0) {
517 rc = ata_wait_ready(ap, deadline);
518 if (rc && rc != -ENODEV)
519 return rc;
520 }
521
522 /* if device 1 was found in ata_devchk, wait for
523 * register access, then wait for BSY to clear
524 */
525 while (dev1) {
526 u8 nsect, lbal;
527
528 ap->ops->dev_select(ap, 1);
529 nsect = in_be32(ioaddr->nsect_addr);
530 lbal = in_be32(ioaddr->lbal_addr);
531 if ((nsect == 1) && (lbal == 1))
532 break;
533 if (time_after(jiffies, deadline))
534 return -EBUSY;
535 msleep(50); /* give drive a breather */
536 }
537 if (dev1) {
538 rc = ata_wait_ready(ap, deadline);
539 if (rc && rc != -ENODEV)
540 return rc;
541 }
542
543 /* is all this really necessary? */
544 ap->ops->dev_select(ap, 0);
545 if (dev1)
546 ap->ops->dev_select(ap, 1);
547 if (dev0)
548 ap->ops->dev_select(ap, 0);
549
550 return 0;
551 }
552
553 /**
554 * scc_bus_softreset - PATA device software reset
555 *
556 * Note: Original code is ata_bus_softreset().
557 */
558
559 static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
560 unsigned long deadline)
561 {
562 struct ata_ioports *ioaddr = &ap->ioaddr;
563
564 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
565
566 /* software reset. causes dev0 to be selected */
567 out_be32(ioaddr->ctl_addr, ap->ctl);
568 udelay(20);
569 out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
570 udelay(20);
571 out_be32(ioaddr->ctl_addr, ap->ctl);
572
573 /* wait a while before checking status */
574 ata_wait_after_reset(ap, deadline);
575
576 /* Before we perform post reset processing we want to see if
577 * the bus shows 0xFF because the odd clown forgets the D7
578 * pulldown resistor.
579 */
580 if (scc_check_status(ap) == 0xFF)
581 return 0;
582
583 scc_bus_post_reset(ap, devmask, deadline);
584
585 return 0;
586 }
587
588 /**
589 * scc_std_softreset - reset host port via ATA SRST
590 * @ap: port to reset
591 * @classes: resulting classes of attached devices
592 * @deadline: deadline jiffies for the operation
593 *
594 * Note: Original code is ata_std_softreset().
595 */
596
597 static int scc_std_softreset(struct ata_link *link, unsigned int *classes,
598 unsigned long deadline)
599 {
600 struct ata_port *ap = link->ap;
601 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
602 unsigned int devmask = 0, err_mask;
603 u8 err;
604
605 DPRINTK("ENTER\n");
606
607 if (ata_link_offline(link)) {
608 classes[0] = ATA_DEV_NONE;
609 goto out;
610 }
611
612 /* determine if device 0/1 are present */
613 if (scc_devchk(ap, 0))
614 devmask |= (1 << 0);
615 if (slave_possible && scc_devchk(ap, 1))
616 devmask |= (1 << 1);
617
618 /* select device 0 again */
619 ap->ops->dev_select(ap, 0);
620
621 /* issue bus reset */
622 DPRINTK("about to softreset, devmask=%x\n", devmask);
623 err_mask = scc_bus_softreset(ap, devmask, deadline);
624 if (err_mask) {
625 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
626 err_mask);
627 return -EIO;
628 }
629
630 /* determine by signature whether we have ATA or ATAPI devices */
631 classes[0] = ata_dev_try_classify(&ap->link.device[0],
632 devmask & (1 << 0), &err);
633 if (slave_possible && err != 0x81)
634 classes[1] = ata_dev_try_classify(&ap->link.device[1],
635 devmask & (1 << 1), &err);
636
637 out:
638 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
639 return 0;
640 }
641
642 /**
643 * scc_bmdma_stop - Stop PCI IDE BMDMA transfer
644 * @qc: Command we are ending DMA for
645 */
646
647 static void scc_bmdma_stop (struct ata_queued_cmd *qc)
648 {
649 struct ata_port *ap = qc->ap;
650 void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
651 void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
652 u32 reg;
653
654 while (1) {
655 reg = in_be32(bmid_base + SCC_DMA_INTST);
656
657 if (reg & INTSTS_SERROR) {
658 printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
659 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
660 out_be32(bmid_base + SCC_DMA_CMD,
661 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
662 continue;
663 }
664
665 if (reg & INTSTS_PRERR) {
666 u32 maea0, maec0;
667 maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
668 maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
669 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
670 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
671 out_be32(bmid_base + SCC_DMA_CMD,
672 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
673 continue;
674 }
675
676 if (reg & INTSTS_RERR) {
677 printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
678 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
679 out_be32(bmid_base + SCC_DMA_CMD,
680 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
681 continue;
682 }
683
684 if (reg & INTSTS_ICERR) {
685 out_be32(bmid_base + SCC_DMA_CMD,
686 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
687 printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
688 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
689 continue;
690 }
691
692 if (reg & INTSTS_BMSINT) {
693 unsigned int classes;
694 unsigned long deadline = jiffies + ATA_TMOUT_BOOT;
695 printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
696 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
697 /* TBD: SW reset */
698 scc_std_softreset(&ap->link, &classes, deadline);
699 continue;
700 }
701
702 if (reg & INTSTS_BMHE) {
703 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
704 continue;
705 }
706
707 if (reg & INTSTS_ACTEINT) {
708 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
709 continue;
710 }
711
712 if (reg & INTSTS_IOIRQS) {
713 out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
714 continue;
715 }
716 break;
717 }
718
719 /* clear start/stop bit */
720 out_be32(bmid_base + SCC_DMA_CMD,
721 in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
722
723 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
724 ata_altstatus(ap); /* dummy read */
725 }
726
727 /**
728 * scc_bmdma_status - Read PCI IDE BMDMA status
729 * @ap: Port associated with this ATA transaction.
730 */
731
732 static u8 scc_bmdma_status (struct ata_port *ap)
733 {
734 void __iomem *mmio = ap->ioaddr.bmdma_addr;
735 u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
736 u32 int_status = in_be32(mmio + SCC_DMA_INTST);
737 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
738 static int retry = 0;
739
740 /* return if IOS_SS is cleared */
741 if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
742 return host_stat;
743
744 /* errata A252,A308 workaround: Step4 */
745 if ((ata_altstatus(ap) & ATA_ERR) && (int_status & INTSTS_INTRQ))
746 return (host_stat | ATA_DMA_INTR);
747
748 /* errata A308 workaround Step5 */
749 if (int_status & INTSTS_IOIRQS) {
750 host_stat |= ATA_DMA_INTR;
751
752 /* We don't check ATAPI DMA because it is limited to UDMA4 */
753 if ((qc->tf.protocol == ATA_PROT_DMA &&
754 qc->dev->xfer_mode > XFER_UDMA_4)) {
755 if (!(int_status & INTSTS_ACTEINT)) {
756 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
757 ap->print_id);
758 host_stat |= ATA_DMA_ERR;
759 if (retry++)
760 ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
761 } else
762 retry = 0;
763 }
764 }
765
766 return host_stat;
767 }
768
769 /**
770 * scc_data_xfer - Transfer data by PIO
771 * @dev: device for this I/O
772 * @buf: data buffer
773 * @buflen: buffer length
774 * @rw: read/write
775 *
776 * Note: Original code is ata_data_xfer().
777 */
778
779 static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
780 unsigned int buflen, int rw)
781 {
782 struct ata_port *ap = dev->link->ap;
783 unsigned int words = buflen >> 1;
784 unsigned int i;
785 u16 *buf16 = (u16 *) buf;
786 void __iomem *mmio = ap->ioaddr.data_addr;
787
788 /* Transfer multiple of 2 bytes */
789 if (rw == READ)
790 for (i = 0; i < words; i++)
791 buf16[i] = le16_to_cpu(in_be32(mmio));
792 else
793 for (i = 0; i < words; i++)
794 out_be32(mmio, cpu_to_le16(buf16[i]));
795
796 /* Transfer trailing 1 byte, if any. */
797 if (unlikely(buflen & 0x01)) {
798 u16 align_buf[1] = { 0 };
799 unsigned char *trailing_buf = buf + buflen - 1;
800
801 if (rw == READ) {
802 align_buf[0] = le16_to_cpu(in_be32(mmio));
803 memcpy(trailing_buf, align_buf, 1);
804 } else {
805 memcpy(align_buf, trailing_buf, 1);
806 out_be32(mmio, cpu_to_le16(align_buf[0]));
807 }
808 words++;
809 }
810
811 return words << 1;
812 }
813
814 /**
815 * scc_irq_on - Enable interrupts on a port.
816 * @ap: Port on which interrupts are enabled.
817 *
818 * Note: Original code is ata_irq_on().
819 */
820
821 static u8 scc_irq_on (struct ata_port *ap)
822 {
823 struct ata_ioports *ioaddr = &ap->ioaddr;
824 u8 tmp;
825
826 ap->ctl &= ~ATA_NIEN;
827 ap->last_ctl = ap->ctl;
828
829 out_be32(ioaddr->ctl_addr, ap->ctl);
830 tmp = ata_wait_idle(ap);
831
832 ap->ops->irq_clear(ap);
833
834 return tmp;
835 }
836
837 /**
838 * scc_bmdma_freeze - Freeze BMDMA controller port
839 * @ap: port to freeze
840 *
841 * Note: Original code is ata_bmdma_freeze().
842 */
843
844 static void scc_bmdma_freeze (struct ata_port *ap)
845 {
846 struct ata_ioports *ioaddr = &ap->ioaddr;
847
848 ap->ctl |= ATA_NIEN;
849 ap->last_ctl = ap->ctl;
850
851 out_be32(ioaddr->ctl_addr, ap->ctl);
852
853 /* Under certain circumstances, some controllers raise IRQ on
854 * ATA_NIEN manipulation. Also, many controllers fail to mask
855 * previously pending IRQ on ATA_NIEN assertion. Clear it.
856 */
857 ata_chk_status(ap);
858
859 ap->ops->irq_clear(ap);
860 }
861
862 /**
863 * scc_pata_prereset - prepare for reset
864 * @ap: ATA port to be reset
865 * @deadline: deadline jiffies for the operation
866 */
867
868 static int scc_pata_prereset(struct ata_link *link, unsigned long deadline)
869 {
870 link->ap->cbl = ATA_CBL_PATA80;
871 return ata_std_prereset(link, deadline);
872 }
873
874 /**
875 * scc_std_postreset - standard postreset callback
876 * @ap: the target ata_port
877 * @classes: classes of attached devices
878 *
879 * Note: Original code is ata_std_postreset().
880 */
881
882 static void scc_std_postreset(struct ata_link *link, unsigned int *classes)
883 {
884 struct ata_port *ap = link->ap;
885
886 DPRINTK("ENTER\n");
887
888 /* is double-select really necessary? */
889 if (classes[0] != ATA_DEV_NONE)
890 ap->ops->dev_select(ap, 1);
891 if (classes[1] != ATA_DEV_NONE)
892 ap->ops->dev_select(ap, 0);
893
894 /* bail out if no device is present */
895 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
896 DPRINTK("EXIT, no device\n");
897 return;
898 }
899
900 /* set up device control */
901 if (ap->ioaddr.ctl_addr)
902 out_be32(ap->ioaddr.ctl_addr, ap->ctl);
903
904 DPRINTK("EXIT\n");
905 }
906
907 /**
908 * scc_error_handler - Stock error handler for BMDMA controller
909 * @ap: port to handle error for
910 */
911
912 static void scc_error_handler (struct ata_port *ap)
913 {
914 ata_bmdma_drive_eh(ap, scc_pata_prereset, scc_std_softreset, NULL,
915 scc_std_postreset);
916 }
917
918 /**
919 * scc_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
920 * @ap: Port associated with this ATA transaction.
921 *
922 * Note: Original code is ata_bmdma_irq_clear().
923 */
924
925 static void scc_bmdma_irq_clear (struct ata_port *ap)
926 {
927 void __iomem *mmio = ap->ioaddr.bmdma_addr;
928
929 if (!mmio)
930 return;
931
932 out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
933 }
934
935 /**
936 * scc_port_start - Set port up for dma.
937 * @ap: Port to initialize
938 *
939 * Allocate space for PRD table using ata_port_start().
940 * Set PRD table address for PTERADD. (PRD Transfer End Read)
941 */
942
943 static int scc_port_start (struct ata_port *ap)
944 {
945 void __iomem *mmio = ap->ioaddr.bmdma_addr;
946 int rc;
947
948 rc = ata_port_start(ap);
949 if (rc)
950 return rc;
951
952 out_be32(mmio + SCC_DMA_PTERADD, ap->prd_dma);
953 return 0;
954 }
955
956 /**
957 * scc_port_stop - Undo scc_port_start()
958 * @ap: Port to shut down
959 *
960 * Reset PTERADD.
961 */
962
963 static void scc_port_stop (struct ata_port *ap)
964 {
965 void __iomem *mmio = ap->ioaddr.bmdma_addr;
966
967 out_be32(mmio + SCC_DMA_PTERADD, 0);
968 }
969
970 static struct scsi_host_template scc_sht = {
971 .module = THIS_MODULE,
972 .name = DRV_NAME,
973 .ioctl = ata_scsi_ioctl,
974 .queuecommand = ata_scsi_queuecmd,
975 .can_queue = ATA_DEF_QUEUE,
976 .this_id = ATA_SHT_THIS_ID,
977 .sg_tablesize = LIBATA_MAX_PRD,
978 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
979 .emulated = ATA_SHT_EMULATED,
980 .use_clustering = ATA_SHT_USE_CLUSTERING,
981 .proc_name = DRV_NAME,
982 .dma_boundary = ATA_DMA_BOUNDARY,
983 .slave_configure = ata_scsi_slave_config,
984 .slave_destroy = ata_scsi_slave_destroy,
985 .bios_param = ata_std_bios_param,
986 };
987
988 static const struct ata_port_operations scc_pata_ops = {
989 .set_piomode = scc_set_piomode,
990 .set_dmamode = scc_set_dmamode,
991 .mode_filter = scc_mode_filter,
992
993 .tf_load = scc_tf_load,
994 .tf_read = scc_tf_read,
995 .exec_command = scc_exec_command,
996 .check_status = scc_check_status,
997 .check_altstatus = scc_check_altstatus,
998 .dev_select = scc_std_dev_select,
999
1000 .bmdma_setup = scc_bmdma_setup,
1001 .bmdma_start = scc_bmdma_start,
1002 .bmdma_stop = scc_bmdma_stop,
1003 .bmdma_status = scc_bmdma_status,
1004 .data_xfer = scc_data_xfer,
1005
1006 .qc_prep = ata_qc_prep,
1007 .qc_issue = ata_qc_issue_prot,
1008
1009 .freeze = scc_bmdma_freeze,
1010 .error_handler = scc_error_handler,
1011 .post_internal_cmd = scc_bmdma_stop,
1012
1013 .irq_clear = scc_bmdma_irq_clear,
1014 .irq_on = scc_irq_on,
1015
1016 .port_start = scc_port_start,
1017 .port_stop = scc_port_stop,
1018 };
1019
1020 static struct ata_port_info scc_port_info[] = {
1021 {
1022 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY,
1023 .pio_mask = 0x1f, /* pio0-4 */
1024 .mwdma_mask = 0x00,
1025 .udma_mask = ATA_UDMA6,
1026 .port_ops = &scc_pata_ops,
1027 },
1028 };
1029
1030 /**
1031 * scc_reset_controller - initialize SCC PATA controller.
1032 */
1033
1034 static int scc_reset_controller(struct ata_host *host)
1035 {
1036 void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
1037 void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
1038 void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
1039 void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
1040 void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
1041 void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
1042 void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
1043 u32 reg = 0;
1044
1045 out_be32(cckctrl_port, reg);
1046 reg |= CCKCTRL_ATACLKOEN;
1047 out_be32(cckctrl_port, reg);
1048 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
1049 out_be32(cckctrl_port, reg);
1050 reg |= CCKCTRL_CRST;
1051 out_be32(cckctrl_port, reg);
1052
1053 for (;;) {
1054 reg = in_be32(cckctrl_port);
1055 if (reg & CCKCTRL_CRST)
1056 break;
1057 udelay(5000);
1058 }
1059
1060 reg |= CCKCTRL_ATARESET;
1061 out_be32(cckctrl_port, reg);
1062 out_be32(ecmode_port, ECMODE_VALUE);
1063 out_be32(mode_port, MODE_JCUSFEN);
1064 out_be32(intmask_port, INTMASK_MSK);
1065
1066 if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
1067 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
1068 return -EIO;
1069 }
1070
1071 return 0;
1072 }
1073
1074 /**
1075 * scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1076 * @ioaddr: IO address structure to be initialized
1077 * @base: base address of BMID region
1078 */
1079
1080 static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1081 {
1082 ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1083 ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1084 ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1085 ioaddr->bmdma_addr = base;
1086 ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1087 ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1088 ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1089 ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1090 ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1091 ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1092 ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1093 ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1094 ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1095 ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1096 }
1097
1098 static int scc_host_init(struct ata_host *host)
1099 {
1100 struct pci_dev *pdev = to_pci_dev(host->dev);
1101 int rc;
1102
1103 rc = scc_reset_controller(host);
1104 if (rc)
1105 return rc;
1106
1107 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1108 if (rc)
1109 return rc;
1110 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1111 if (rc)
1112 return rc;
1113
1114 scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1115
1116 pci_set_master(pdev);
1117
1118 return 0;
1119 }
1120
1121 /**
1122 * scc_init_one - Register SCC PATA device with kernel services
1123 * @pdev: PCI device to register
1124 * @ent: Entry in scc_pci_tbl matching with @pdev
1125 *
1126 * LOCKING:
1127 * Inherited from PCI layer (may sleep).
1128 *
1129 * RETURNS:
1130 * Zero on success, or -ERRNO value.
1131 */
1132
1133 static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1134 {
1135 static int printed_version;
1136 unsigned int board_idx = (unsigned int) ent->driver_data;
1137 const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1138 struct ata_host *host;
1139 int rc;
1140
1141 if (!printed_version++)
1142 dev_printk(KERN_DEBUG, &pdev->dev,
1143 "version " DRV_VERSION "\n");
1144
1145 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1146 if (!host)
1147 return -ENOMEM;
1148
1149 rc = pcim_enable_device(pdev);
1150 if (rc)
1151 return rc;
1152
1153 rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1154 if (rc == -EBUSY)
1155 pcim_pin_device(pdev);
1156 if (rc)
1157 return rc;
1158 host->iomap = pcim_iomap_table(pdev);
1159
1160 ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1161 ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1162
1163 rc = scc_host_init(host);
1164 if (rc)
1165 return rc;
1166
1167 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
1168 &scc_sht);
1169 }
1170
1171 static struct pci_driver scc_pci_driver = {
1172 .name = DRV_NAME,
1173 .id_table = scc_pci_tbl,
1174 .probe = scc_init_one,
1175 .remove = ata_pci_remove_one,
1176 #ifdef CONFIG_PM
1177 .suspend = ata_pci_device_suspend,
1178 .resume = ata_pci_device_resume,
1179 #endif
1180 };
1181
1182 static int __init scc_init (void)
1183 {
1184 int rc;
1185
1186 DPRINTK("pci_register_driver\n");
1187 rc = pci_register_driver(&scc_pci_driver);
1188 if (rc)
1189 return rc;
1190
1191 DPRINTK("done\n");
1192 return 0;
1193 }
1194
1195 static void __exit scc_exit (void)
1196 {
1197 pci_unregister_driver(&scc_pci_driver);
1198 }
1199
1200 module_init(scc_init);
1201 module_exit(scc_exit);
1202
1203 MODULE_AUTHOR("Toshiba corp");
1204 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1205 MODULE_LICENSE("GPL");
1206 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1207 MODULE_VERSION(DRV_VERSION);
WRT350N Kernel Patches