drivers/ide/legacy/q40ide.c

   1 /*
   2  *  Q40 I/O port IDE Driver
   3  *
   4  *     (c) Richard Zidlicky
   5  *
   6  *  This file is subject to the terms and conditions of the GNU General Public
   7  *  License.  See the file COPYING in the main directory of this archive for
   8  *  more details.
   9  *
  10  *
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/mm.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/blkdev.h>
  17 #include <linux/hdreg.h>
  18
  19 #include <linux/ide.h>
  20
  21     /*
  22      *  Bases of the IDE interfaces
  23      */
  24
  25 #define Q40IDE_NUM_HWIFS        2
  26
  27 #define PCIDE_BASE1     0x1f0
  28 #define PCIDE_BASE2     0x170
  29 #define PCIDE_BASE3     0x1e8
  30 #define PCIDE_BASE4     0x168
  31 #define PCIDE_BASE5     0x1e0
  32 #define PCIDE_BASE6     0x160
  33
  34 static const unsigned long pcide_bases[Q40IDE_NUM_HWIFS] = {
  35     PCIDE_BASE1, PCIDE_BASE2, /* PCIDE_BASE3, PCIDE_BASE4  , PCIDE_BASE5,
  36     PCIDE_BASE6 */
  37 };
  38
  39
  40     /*
  41      *  Offsets from one of the above bases
  42      */
  43
  44 /* used to do addr translation here but it is easier to do in setup ports */
  45 /*#define IDE_OFF_B(x)  ((unsigned long)Q40_ISA_IO_B((IDE_##x##_OFFSET)))*/
  46
  47 #define IDE_OFF_B(x)    ((unsigned long)((IDE_##x##_OFFSET)))
  48 #define IDE_OFF_W(x)    ((unsigned long)((IDE_##x##_OFFSET)))
  49
  50 static const int pcide_offsets[IDE_NR_PORTS] = {
  51     IDE_OFF_W(DATA), IDE_OFF_B(ERROR), IDE_OFF_B(NSECTOR), IDE_OFF_B(SECTOR),
  52     IDE_OFF_B(LCYL), IDE_OFF_B(HCYL), 6 /*IDE_OFF_B(CURRENT)*/, IDE_OFF_B(STATUS),
  53     518/*IDE_OFF(CMD)*/
  54 };
  55
  56 static int q40ide_default_irq(unsigned long base)
  57 {
  58            switch (base) {
  59                     case 0x1f0: return 14;
  60                     case 0x170: return 15;
  61                     case 0x1e8: return 11;
  62                     default:
  63                         return 0;
  64            }
  65 }
  66
  67
  68 /*
  69  * This is very similar to ide_setup_ports except that addresses
  70  * are pretranslated for q40 ISA access
  71  */
  72 void q40_ide_setup_ports ( hw_regs_t *hw,
  73                         unsigned long base, int *offsets,
  74                         unsigned long ctrl, unsigned long intr,
  75                         ide_ack_intr_t *ack_intr,
  76 /*
  77  *                      ide_io_ops_t *iops,
  78  */
  79                         int irq)
  80 {
  81         int i;
  82
  83         memset(hw, 0, sizeof(hw_regs_t));
  84         for (i = 0; i < IDE_NR_PORTS; i++) {
  85                 /* BIG FAT WARNING:
  86                    assumption: only DATA port is ever used in 16 bit mode */
  87                 if ( i==0 )
  88                         hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]);
  89                 else
  90                         hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]);
  91         }
  92
  93         hw->irq = irq;
  94         hw->ack_intr = ack_intr;
  95 /*
  96  *      hw->iops = iops;
  97  */
  98 }
  99
 100
 101
 102 /*
 103  * the static array is needed to have the name reported in /proc/ioports,
 104  * hwif->name unfortunately isn't available yet
 105  */
 106 static const char *q40_ide_names[Q40IDE_NUM_HWIFS]={
 107         "ide0", "ide1"
 108 };
 109
 110 /*
 111  *  Probe for Q40 IDE interfaces
 112  */
 113
 114 static int __init q40ide_init(void)
 115 {
 116     int i;
 117     ide_hwif_t *hwif;
 118     const char *name;
 119     u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 120
 121     if (!MACH_IS_Q40)
 122       return -ENODEV;
 123
 124     printk(KERN_INFO "ide: Q40 IDE controller\n");
 125
 126     for (i = 0; i < Q40IDE_NUM_HWIFS; i++) {
 127         hw_regs_t hw;
 128
 129         name = q40_ide_names[i];
 130         if (!request_region(pcide_bases[i], 8, name)) {
 131                 printk("could not reserve ports %lx-%lx for %s\n",
 132                        pcide_bases[i],pcide_bases[i]+8,name);
 133                 continue;
 134         }
 135         if (!request_region(pcide_bases[i]+0x206, 1, name)) {
 136                 printk("could not reserve port %lx for %s\n",
 137                        pcide_bases[i]+0x206,name);
 138                 release_region(pcide_bases[i], 8);
 139                 continue;
 140         }
 141         q40_ide_setup_ports(&hw,(unsigned long) pcide_bases[i], (int *)pcide_offsets,
 142                         pcide_bases[i]+0x206,
 143                         0, NULL,
 144 //                      m68kide_iops,
 145                         q40ide_default_irq(pcide_bases[i]));
 146
 147         hwif = ide_find_port(hw.io_ports[IDE_DATA_OFFSET]);
 148         if (hwif) {
 149                 ide_init_port_data(hwif, hwif->index);
 150                 ide_init_port_hw(hwif, &hw);
 151                 hwif->mmio = 1;
 152
 153                 idx[i] = hwif->index;
 154         }
 155     }
 156
 157     ide_device_add(idx, NULL);
 158
 159     return 0;
 160 }
 161
 162 module_init(q40ide_init);