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kbuild: Fix instrumentation removal breakage on avr32
[wrt350n-kernel.git] / drivers / net / netxen / netxen_nic_hw.c
blob01355701bf8ecb9701d2f2d4b46186b774d1bf82
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
37
38
39 #include <net/ip.h>
40
41 struct netxen_recv_crb recv_crb_registers[] = {
42 /*
43 * Instance 0.
44 */
45 {
46 /* rcv_desc_crb: */
47 {
48 {
49 /* crb_rcv_producer_offset: */
50 NETXEN_NIC_REG(0x100),
51 /* crb_rcv_consumer_offset: */
52 NETXEN_NIC_REG(0x104),
53 /* crb_gloablrcv_ring: */
54 NETXEN_NIC_REG(0x108),
55 /* crb_rcv_ring_size */
56 NETXEN_NIC_REG(0x10c),
57
58 },
59 /* Jumbo frames */
60 {
61 /* crb_rcv_producer_offset: */
62 NETXEN_NIC_REG(0x110),
63 /* crb_rcv_consumer_offset: */
64 NETXEN_NIC_REG(0x114),
65 /* crb_gloablrcv_ring: */
66 NETXEN_NIC_REG(0x118),
67 /* crb_rcv_ring_size */
68 NETXEN_NIC_REG(0x11c),
69 },
70 /* LRO */
71 {
72 /* crb_rcv_producer_offset: */
73 NETXEN_NIC_REG(0x120),
74 /* crb_rcv_consumer_offset: */
75 NETXEN_NIC_REG(0x124),
76 /* crb_gloablrcv_ring: */
77 NETXEN_NIC_REG(0x128),
78 /* crb_rcv_ring_size */
79 NETXEN_NIC_REG(0x12c),
80 }
81 },
82 /* crb_rcvstatus_ring: */
83 NETXEN_NIC_REG(0x130),
84 /* crb_rcv_status_producer: */
85 NETXEN_NIC_REG(0x134),
86 /* crb_rcv_status_consumer: */
87 NETXEN_NIC_REG(0x138),
88 /* crb_rcvpeg_state: */
89 NETXEN_NIC_REG(0x13c),
90 /* crb_status_ring_size */
91 NETXEN_NIC_REG(0x140),
92
93 },
94 /*
95 * Instance 1,
96 */
97 {
98 /* rcv_desc_crb: */
99 {
100 {
101 /* crb_rcv_producer_offset: */
102 NETXEN_NIC_REG(0x144),
103 /* crb_rcv_consumer_offset: */
104 NETXEN_NIC_REG(0x148),
105 /* crb_globalrcv_ring: */
106 NETXEN_NIC_REG(0x14c),
107 /* crb_rcv_ring_size */
108 NETXEN_NIC_REG(0x150),
109
110 },
111 /* Jumbo frames */
112 {
113 /* crb_rcv_producer_offset: */
114 NETXEN_NIC_REG(0x154),
115 /* crb_rcv_consumer_offset: */
116 NETXEN_NIC_REG(0x158),
117 /* crb_globalrcv_ring: */
118 NETXEN_NIC_REG(0x15c),
119 /* crb_rcv_ring_size */
120 NETXEN_NIC_REG(0x160),
121 },
122 /* LRO */
123 {
124 /* crb_rcv_producer_offset: */
125 NETXEN_NIC_REG(0x164),
126 /* crb_rcv_consumer_offset: */
127 NETXEN_NIC_REG(0x168),
128 /* crb_globalrcv_ring: */
129 NETXEN_NIC_REG(0x16c),
130 /* crb_rcv_ring_size */
131 NETXEN_NIC_REG(0x170),
132 }
133
134 },
135 /* crb_rcvstatus_ring: */
136 NETXEN_NIC_REG(0x174),
137 /* crb_rcv_status_producer: */
138 NETXEN_NIC_REG(0x178),
139 /* crb_rcv_status_consumer: */
140 NETXEN_NIC_REG(0x17c),
141 /* crb_rcvpeg_state: */
142 NETXEN_NIC_REG(0x180),
143 /* crb_status_ring_size */
144 NETXEN_NIC_REG(0x184),
145 },
146 /*
147 * Instance 2,
148 */
149 {
150 {
151 {
152 /* crb_rcv_producer_offset: */
153 NETXEN_NIC_REG(0x1d8),
154 /* crb_rcv_consumer_offset: */
155 NETXEN_NIC_REG(0x1dc),
156 /* crb_gloablrcv_ring: */
157 NETXEN_NIC_REG(0x1f0),
158 /* crb_rcv_ring_size */
159 NETXEN_NIC_REG(0x1f4),
160 },
161 /* Jumbo frames */
162 {
163 /* crb_rcv_producer_offset: */
164 NETXEN_NIC_REG(0x1f8),
165 /* crb_rcv_consumer_offset: */
166 NETXEN_NIC_REG(0x1fc),
167 /* crb_gloablrcv_ring: */
168 NETXEN_NIC_REG(0x200),
169 /* crb_rcv_ring_size */
170 NETXEN_NIC_REG(0x204),
171 },
172 /* LRO */
173 {
174 /* crb_rcv_producer_offset: */
175 NETXEN_NIC_REG(0x208),
176 /* crb_rcv_consumer_offset: */
177 NETXEN_NIC_REG(0x20c),
178 /* crb_gloablrcv_ring: */
179 NETXEN_NIC_REG(0x210),
180 /* crb_rcv_ring_size */
181 NETXEN_NIC_REG(0x214),
182 }
183 },
184 /* crb_rcvstatus_ring: */
185 NETXEN_NIC_REG(0x218),
186 /* crb_rcv_status_producer: */
187 NETXEN_NIC_REG(0x21c),
188 /* crb_rcv_status_consumer: */
189 NETXEN_NIC_REG(0x220),
190 /* crb_rcvpeg_state: */
191 NETXEN_NIC_REG(0x224),
192 /* crb_status_ring_size */
193 NETXEN_NIC_REG(0x228),
194 },
195 /*
196 * Instance 3,
197 */
198 {
199 {
200 {
201 /* crb_rcv_producer_offset: */
202 NETXEN_NIC_REG(0x22c),
203 /* crb_rcv_consumer_offset: */
204 NETXEN_NIC_REG(0x230),
205 /* crb_gloablrcv_ring: */
206 NETXEN_NIC_REG(0x234),
207 /* crb_rcv_ring_size */
208 NETXEN_NIC_REG(0x238),
209 },
210 /* Jumbo frames */
211 {
212 /* crb_rcv_producer_offset: */
213 NETXEN_NIC_REG(0x23c),
214 /* crb_rcv_consumer_offset: */
215 NETXEN_NIC_REG(0x240),
216 /* crb_gloablrcv_ring: */
217 NETXEN_NIC_REG(0x244),
218 /* crb_rcv_ring_size */
219 NETXEN_NIC_REG(0x248),
220 },
221 /* LRO */
222 {
223 /* crb_rcv_producer_offset: */
224 NETXEN_NIC_REG(0x24c),
225 /* crb_rcv_consumer_offset: */
226 NETXEN_NIC_REG(0x250),
227 /* crb_gloablrcv_ring: */
228 NETXEN_NIC_REG(0x254),
229 /* crb_rcv_ring_size */
230 NETXEN_NIC_REG(0x258),
231 }
232 },
233 /* crb_rcvstatus_ring: */
234 NETXEN_NIC_REG(0x25c),
235 /* crb_rcv_status_producer: */
236 NETXEN_NIC_REG(0x260),
237 /* crb_rcv_status_consumer: */
238 NETXEN_NIC_REG(0x264),
239 /* crb_rcvpeg_state: */
240 NETXEN_NIC_REG(0x268),
241 /* crb_status_ring_size */
242 NETXEN_NIC_REG(0x26c),
243 },
244 };
245
246 static u64 ctx_addr_sig_regs[][3] = {
247 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
248 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
249 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
250 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
251 };
252 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
253 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
254 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
255
256
257 /* PCI Windowing for DDR regions. */
258
259 #define ADDR_IN_RANGE(addr, low, high) \
260 (((addr) <= (high)) && ((addr) >= (low)))
261
262 #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
263 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
264 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
265 #define NETXEN_MIN_MTU 64
266 #define NETXEN_ETH_FCS_SIZE 4
267 #define NETXEN_ENET_HEADER_SIZE 14
268 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
269 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
270 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
271 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
272
273 #define lower32(x) ((u32)((x) & 0xffffffff))
274 #define upper32(x) \
275 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
276
277 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
278 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
279 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
280 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
281
282 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
283
284 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
285 unsigned long long addr);
286 void netxen_free_hw_resources(struct netxen_adapter *adapter);
287
288 int netxen_nic_set_mac(struct net_device *netdev, void *p)
289 {
290 struct netxen_adapter *adapter = netdev_priv(netdev);
291 struct sockaddr *addr = p;
292
293 if (netif_running(netdev))
294 return -EBUSY;
295
296 if (!is_valid_ether_addr(addr->sa_data))
297 return -EADDRNOTAVAIL;
298
299 DPRINTK(INFO, "valid ether addr\n");
300 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
301
302 if (adapter->macaddr_set)
303 adapter->macaddr_set(adapter, addr->sa_data);
304
305 return 0;
306 }
307
308 /*
309 * netxen_nic_set_multi - Multicast
310 */
311 void netxen_nic_set_multi(struct net_device *netdev)
312 {
313 struct netxen_adapter *adapter = netdev_priv(netdev);
314 struct dev_mc_list *mc_ptr;
315
316 mc_ptr = netdev->mc_list;
317 if (netdev->flags & IFF_PROMISC) {
318 if (adapter->set_promisc)
319 adapter->set_promisc(adapter,
320 NETXEN_NIU_PROMISC_MODE);
321 } else {
322 if (adapter->unset_promisc)
323 adapter->unset_promisc(adapter,
324 NETXEN_NIU_NON_PROMISC_MODE);
325 }
326 }
327
328 /*
329 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
330 * @returns 0 on success, negative on failure
331 */
332 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
333 {
334 struct netxen_adapter *adapter = netdev_priv(netdev);
335 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
336
337 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
338 printk(KERN_ERR "%s: %s %d is not supported.\n",
339 netxen_nic_driver_name, netdev->name, mtu);
340 return -EINVAL;
341 }
342
343 if (adapter->set_mtu)
344 adapter->set_mtu(adapter, mtu);
345 netdev->mtu = mtu;
346
347 return 0;
348 }
349
350 /*
351 * check if the firmware has been downloaded and ready to run and
352 * setup the address for the descriptors in the adapter
353 */
354 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
355 {
356 struct netxen_hardware_context *hw = &adapter->ahw;
357 u32 state = 0;
358 void *addr;
359 int loops = 0, err = 0;
360 int ctx, ring;
361 struct netxen_recv_context *recv_ctx;
362 struct netxen_rcv_desc_ctx *rcv_desc;
363 int func_id = adapter->portnum;
364
365 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
366 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
367 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
368 pci_base_offset(adapter, NETXEN_CRB_CAM));
369 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
370 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
371
372
373 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
374 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
375 loops = 0;
376 state = 0;
377 /* Window 1 call */
378 state = readl(NETXEN_CRB_NORMALIZE(adapter,
379 recv_crb_registers[ctx].
380 crb_rcvpeg_state));
381 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
382 msleep(1);
383 /* Window 1 call */
384 state = readl(NETXEN_CRB_NORMALIZE(adapter,
385 recv_crb_registers
386 [ctx].
387 crb_rcvpeg_state));
388 loops++;
389 }
390 if (loops >= 20) {
391 printk(KERN_ERR "Rcv Peg initialization not complete:"
392 "%x.\n", state);
393 err = -EIO;
394 return err;
395 }
396 }
397 adapter->intr_scheme = readl(
398 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
399 printk(KERN_NOTICE "%s: FW capabilities:0x%x\n", netxen_nic_driver_name,
400 adapter->intr_scheme);
401 DPRINTK(INFO, "Receive Peg ready too. starting stuff\n");
402
403 addr = netxen_alloc(adapter->ahw.pdev,
404 sizeof(struct netxen_ring_ctx) +
405 sizeof(uint32_t),
406 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
407 &adapter->ctx_desc_pdev);
408
409 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
410 (unsigned long long) adapter->ctx_desc_phys_addr);
411 if (addr == NULL) {
412 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
413 err = -ENOMEM;
414 return err;
415 }
416 memset(addr, 0, sizeof(struct netxen_ring_ctx));
417 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
418 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
419 adapter->ctx_desc->cmd_consumer_offset =
420 cpu_to_le64(adapter->ctx_desc_phys_addr +
421 sizeof(struct netxen_ring_ctx));
422 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
423 sizeof(struct netxen_ring_ctx));
424
425 addr = netxen_alloc(adapter->ahw.pdev,
426 sizeof(struct cmd_desc_type0) *
427 adapter->max_tx_desc_count,
428 (dma_addr_t *) & hw->cmd_desc_phys_addr,
429 &adapter->ahw.cmd_desc_pdev);
430 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
431 (unsigned long long) hw->cmd_desc_phys_addr);
432
433 if (addr == NULL) {
434 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
435 netxen_free_hw_resources(adapter);
436 return -ENOMEM;
437 }
438
439 adapter->ctx_desc->cmd_ring_addr =
440 cpu_to_le64(hw->cmd_desc_phys_addr);
441 adapter->ctx_desc->cmd_ring_size =
442 cpu_to_le32(adapter->max_tx_desc_count);
443
444 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
445
446 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
447 recv_ctx = &adapter->recv_ctx[ctx];
448
449 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
450 rcv_desc = &recv_ctx->rcv_desc[ring];
451 addr = netxen_alloc(adapter->ahw.pdev,
452 RCV_DESC_RINGSIZE,
453 &rcv_desc->phys_addr,
454 &rcv_desc->phys_pdev);
455 if (addr == NULL) {
456 DPRINTK(ERR, "bad return from "
457 "pci_alloc_consistent\n");
458 netxen_free_hw_resources(adapter);
459 err = -ENOMEM;
460 return err;
461 }
462 rcv_desc->desc_head = (struct rcv_desc *)addr;
463 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
464 cpu_to_le64(rcv_desc->phys_addr);
465 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
466 cpu_to_le32(rcv_desc->max_rx_desc_count);
467 }
468
469 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
470 &recv_ctx->rcv_status_desc_phys_addr,
471 &recv_ctx->rcv_status_desc_pdev);
472 if (addr == NULL) {
473 DPRINTK(ERR, "bad return from"
474 " pci_alloc_consistent\n");
475 netxen_free_hw_resources(adapter);
476 err = -ENOMEM;
477 return err;
478 }
479 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
480 adapter->ctx_desc->sts_ring_addr =
481 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
482 adapter->ctx_desc->sts_ring_size =
483 cpu_to_le32(adapter->max_rx_desc_count);
484
485 }
486 /* Window = 1 */
487
488 writel(lower32(adapter->ctx_desc_phys_addr),
489 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
490 writel(upper32(adapter->ctx_desc_phys_addr),
491 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
492 writel(NETXEN_CTX_SIGNATURE | func_id,
493 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
494 return err;
495 }
496
497 void netxen_free_hw_resources(struct netxen_adapter *adapter)
498 {
499 struct netxen_recv_context *recv_ctx;
500 struct netxen_rcv_desc_ctx *rcv_desc;
501 int ctx, ring;
502
503 if (adapter->ctx_desc != NULL) {
504 pci_free_consistent(adapter->ctx_desc_pdev,
505 sizeof(struct netxen_ring_ctx) +
506 sizeof(uint32_t),
507 adapter->ctx_desc,
508 adapter->ctx_desc_phys_addr);
509 adapter->ctx_desc = NULL;
510 }
511
512 if (adapter->ahw.cmd_desc_head != NULL) {
513 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
514 sizeof(struct cmd_desc_type0) *
515 adapter->max_tx_desc_count,
516 adapter->ahw.cmd_desc_head,
517 adapter->ahw.cmd_desc_phys_addr);
518 adapter->ahw.cmd_desc_head = NULL;
519 }
520
521 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
522 recv_ctx = &adapter->recv_ctx[ctx];
523 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
524 rcv_desc = &recv_ctx->rcv_desc[ring];
525
526 if (rcv_desc->desc_head != NULL) {
527 pci_free_consistent(rcv_desc->phys_pdev,
528 RCV_DESC_RINGSIZE,
529 rcv_desc->desc_head,
530 rcv_desc->phys_addr);
531 rcv_desc->desc_head = NULL;
532 }
533 }
534
535 if (recv_ctx->rcv_status_desc_head != NULL) {
536 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
537 STATUS_DESC_RINGSIZE,
538 recv_ctx->rcv_status_desc_head,
539 recv_ctx->
540 rcv_status_desc_phys_addr);
541 recv_ctx->rcv_status_desc_head = NULL;
542 }
543 }
544 }
545
546 void netxen_tso_check(struct netxen_adapter *adapter,
547 struct cmd_desc_type0 *desc, struct sk_buff *skb)
548 {
549 if (desc->mss) {
550 desc->total_hdr_length = (sizeof(struct ethhdr) +
551 ip_hdrlen(skb) + tcp_hdrlen(skb));
552 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
553 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
554 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
555 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
556 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
557 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
558 } else {
559 return;
560 }
561 }
562 desc->tcp_hdr_offset = skb_transport_offset(skb);
563 desc->ip_hdr_offset = skb_network_offset(skb);
564 }
565
566 int netxen_is_flash_supported(struct netxen_adapter *adapter)
567 {
568 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
569 int addr, val01, val02, i, j;
570
571 /* if the flash size less than 4Mb, make huge war cry and die */
572 for (j = 1; j < 4; j++) {
573 addr = j * NETXEN_NIC_WINDOW_MARGIN;
574 for (i = 0; i < ARRAY_SIZE(locs); i++) {
575 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
576 && netxen_rom_fast_read(adapter, (addr + locs[i]),
577 &val02) == 0) {
578 if (val01 == val02)
579 return -1;
580 } else
581 return -1;
582 }
583 }
584
585 return 0;
586 }
587
588 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
589 int size, __le32 * buf)
590 {
591 int i, addr;
592 __le32 *ptr32;
593 u32 v;
594
595 addr = base;
596 ptr32 = buf;
597 for (i = 0; i < size / sizeof(u32); i++) {
598 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
599 return -1;
600 *ptr32 = cpu_to_le32(v);
601 ptr32++;
602 addr += sizeof(u32);
603 }
604 if ((char *)buf + size > (char *)ptr32) {
605 __le32 local;
606 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
607 return -1;
608 local = cpu_to_le32(v);
609 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
610 }
611
612 return 0;
613 }
614
615 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
616 {
617 __le32 *pmac = (__le32 *) & mac[0];
618
619 if (netxen_get_flash_block(adapter,
620 NETXEN_USER_START +
621 offsetof(struct netxen_new_user_info,
622 mac_addr),
623 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
624 return -1;
625 }
626 if (*mac == cpu_to_le64(~0ULL)) {
627 if (netxen_get_flash_block(adapter,
628 NETXEN_USER_START_OLD +
629 offsetof(struct netxen_user_old_info,
630 mac_addr),
631 FLASH_NUM_PORTS * sizeof(u64),
632 pmac) == -1)
633 return -1;
634 if (*mac == cpu_to_le64(~0ULL))
635 return -1;
636 }
637 return 0;
638 }
639
640 /*
641 * Changes the CRB window to the specified window.
642 */
643 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
644 {
645 void __iomem *offset;
646 u32 tmp;
647 int count = 0;
648
649 if (adapter->curr_window == wndw)
650 return;
651 switch(adapter->ahw.pci_func) {
652 case 0:
653 offset = PCI_OFFSET_SECOND_RANGE(adapter,
654 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
655 break;
656 case 1:
657 offset = PCI_OFFSET_SECOND_RANGE(adapter,
658 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
659 break;
660 case 2:
661 offset = PCI_OFFSET_SECOND_RANGE(adapter,
662 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
663 break;
664 case 3:
665 offset = PCI_OFFSET_SECOND_RANGE(adapter,
666 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
667 break;
668 default:
669 printk(KERN_INFO "Changing the window for PCI function "
670 "%d\n", adapter->ahw.pci_func);
671 offset = PCI_OFFSET_SECOND_RANGE(adapter,
672 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
673 break;
674 }
675 /*
676 * Move the CRB window.
677 * We need to write to the "direct access" region of PCI
678 * to avoid a race condition where the window register has
679 * not been successfully written across CRB before the target
680 * register address is received by PCI. The direct region bypasses
681 * the CRB bus.
682 */
683
684 if (wndw & 0x1)
685 wndw = NETXEN_WINDOW_ONE;
686
687 writel(wndw, offset);
688
689 /* MUST make sure window is set before we forge on... */
690 while ((tmp = readl(offset)) != wndw) {
691 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
692 "registered properly: 0x%08x.\n",
693 netxen_nic_driver_name, __FUNCTION__, tmp);
694 mdelay(1);
695 if (count >= 10)
696 break;
697 count++;
698 }
699
700 if (wndw == NETXEN_WINDOW_ONE)
701 adapter->curr_window = 1;
702 else
703 adapter->curr_window = 0;
704 }
705
706 int netxen_load_firmware(struct netxen_adapter *adapter)
707 {
708 int i;
709 u32 data, size = 0;
710 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
711 u64 off;
712 void __iomem *addr;
713
714 size = NETXEN_FIRMWARE_LEN;
715 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
716
717 for (i = 0; i < size; i++) {
718 int retries = 10;
719 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
720 return -EIO;
721
722 off = netxen_nic_pci_set_window(adapter, memaddr);
723 addr = pci_base_offset(adapter, off);
724 writel(data, addr);
725 do {
726 if (readl(addr) == data)
727 break;
728 msleep(100);
729 writel(data, addr);
730 } while (--retries);
731 if (!retries) {
732 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
733 netxen_nic_driver_name, memaddr);
734 return -EIO;
735 }
736 flashaddr += 4;
737 memaddr += 4;
738 }
739 udelay(100);
740 /* make sure Casper is powered on */
741 writel(0x3fff,
742 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
743 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
744
745 return 0;
746 }
747
748 int
749 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
750 int len)
751 {
752 void __iomem *addr;
753
754 if (ADDR_IN_WINDOW1(off)) {
755 addr = NETXEN_CRB_NORMALIZE(adapter, off);
756 } else { /* Window 0 */
757 addr = pci_base_offset(adapter, off);
758 netxen_nic_pci_change_crbwindow(adapter, 0);
759 }
760
761 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
762 " data %llx len %d\n",
763 pci_base(adapter, off), off, addr,
764 *(unsigned long long *)data, len);
765 if (!addr) {
766 netxen_nic_pci_change_crbwindow(adapter, 1);
767 return 1;
768 }
769
770 switch (len) {
771 case 1:
772 writeb(*(u8 *) data, addr);
773 break;
774 case 2:
775 writew(*(u16 *) data, addr);
776 break;
777 case 4:
778 writel(*(u32 *) data, addr);
779 break;
780 case 8:
781 writeq(*(u64 *) data, addr);
782 break;
783 default:
784 DPRINTK(INFO,
785 "writing data %lx to offset %llx, num words=%d\n",
786 *(unsigned long *)data, off, (len >> 3));
787
788 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
789 (len >> 3));
790 break;
791 }
792 if (!ADDR_IN_WINDOW1(off))
793 netxen_nic_pci_change_crbwindow(adapter, 1);
794
795 return 0;
796 }
797
798 int
799 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
800 int len)
801 {
802 void __iomem *addr;
803
804 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
805 addr = NETXEN_CRB_NORMALIZE(adapter, off);
806 } else { /* Window 0 */
807 addr = pci_base_offset(adapter, off);
808 netxen_nic_pci_change_crbwindow(adapter, 0);
809 }
810
811 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
812 pci_base(adapter, off), off, addr);
813 if (!addr) {
814 netxen_nic_pci_change_crbwindow(adapter, 1);
815 return 1;
816 }
817 switch (len) {
818 case 1:
819 *(u8 *) data = readb(addr);
820 break;
821 case 2:
822 *(u16 *) data = readw(addr);
823 break;
824 case 4:
825 *(u32 *) data = readl(addr);
826 break;
827 case 8:
828 *(u64 *) data = readq(addr);
829 break;
830 default:
831 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
832 (len >> 3));
833 break;
834 }
835 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
836
837 if (!ADDR_IN_WINDOW1(off))
838 netxen_nic_pci_change_crbwindow(adapter, 1);
839
840 return 0;
841 }
842
843 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
844 { /* Only for window 1 */
845 void __iomem *addr;
846
847 addr = NETXEN_CRB_NORMALIZE(adapter, off);
848 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
849 pci_base(adapter, off), off, addr, val);
850 writel(val, addr);
851
852 }
853
854 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
855 { /* Only for window 1 */
856 void __iomem *addr;
857 int val;
858
859 addr = NETXEN_CRB_NORMALIZE(adapter, off);
860 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
861 pci_base(adapter, off), off, addr);
862 val = readl(addr);
863 writel(val, addr);
864
865 return val;
866 }
867
868 /* Change the window to 0, write and change back to window 1. */
869 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
870 {
871 void __iomem *addr;
872
873 netxen_nic_pci_change_crbwindow(adapter, 0);
874 addr = pci_base_offset(adapter, index);
875 writel(value, addr);
876 netxen_nic_pci_change_crbwindow(adapter, 1);
877 }
878
879 /* Change the window to 0, read and change back to window 1. */
880 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
881 {
882 void __iomem *addr;
883
884 addr = pci_base_offset(adapter, index);
885
886 netxen_nic_pci_change_crbwindow(adapter, 0);
887 *value = readl(addr);
888 netxen_nic_pci_change_crbwindow(adapter, 1);
889 }
890
891 static int netxen_pci_set_window_warning_count;
892
893 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
894 unsigned long long addr)
895 {
896 static int ddr_mn_window = -1;
897 static int qdr_sn_window = -1;
898 int window;
899
900 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
901 /* DDR network side */
902 addr -= NETXEN_ADDR_DDR_NET;
903 window = (addr >> 25) & 0x3ff;
904 if (ddr_mn_window != window) {
905 ddr_mn_window = window;
906 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
907 NETXEN_PCIX_PH_REG
908 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
909 /* MUST make sure window is set before we forge on... */
910 readl(PCI_OFFSET_SECOND_RANGE(adapter,
911 NETXEN_PCIX_PH_REG
912 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
913 }
914 addr -= (window * NETXEN_WINDOW_ONE);
915 addr += NETXEN_PCI_DDR_NET;
916 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
917 addr -= NETXEN_ADDR_OCM0;
918 addr += NETXEN_PCI_OCM0;
919 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
920 addr -= NETXEN_ADDR_OCM1;
921 addr += NETXEN_PCI_OCM1;
922 } else
923 if (ADDR_IN_RANGE
924 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
925 /* QDR network side */
926 addr -= NETXEN_ADDR_QDR_NET;
927 window = (addr >> 22) & 0x3f;
928 if (qdr_sn_window != window) {
929 qdr_sn_window = window;
930 writel((window << 22),
931 PCI_OFFSET_SECOND_RANGE(adapter,
932 NETXEN_PCIX_PH_REG
933 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
934 /* MUST make sure window is set before we forge on... */
935 readl(PCI_OFFSET_SECOND_RANGE(adapter,
936 NETXEN_PCIX_PH_REG
937 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
938 }
939 addr -= (window * 0x400000);
940 addr += NETXEN_PCI_QDR_NET;
941 } else {
942 /*
943 * peg gdb frequently accesses memory that doesn't exist,
944 * this limits the chit chat so debugging isn't slowed down.
945 */
946 if ((netxen_pci_set_window_warning_count++ < 8)
947 || (netxen_pci_set_window_warning_count % 64 == 0))
948 printk("%s: Warning:netxen_nic_pci_set_window()"
949 " Unknown address range!\n",
950 netxen_nic_driver_name);
951
952 }
953 return addr;
954 }
955
956 #if 0
957 int
958 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
959 {
960 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
961 printk(KERN_ERR "%s: erase pxe failed\n",
962 netxen_nic_driver_name);
963 return -1;
964 }
965 return 0;
966 }
967 #endif /* 0 */
968
969 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
970 {
971 int rv = 0;
972 int addr = NETXEN_BRDCFG_START;
973 struct netxen_board_info *boardinfo;
974 int index;
975 u32 *ptr32;
976
977 boardinfo = &adapter->ahw.boardcfg;
978 ptr32 = (u32 *) boardinfo;
979
980 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
981 index++) {
982 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
983 return -EIO;
984 }
985 ptr32++;
986 addr += sizeof(u32);
987 }
988 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
989 printk("%s: ERROR reading %s board config."
990 " Read %x, expected %x\n", netxen_nic_driver_name,
991 netxen_nic_driver_name,
992 boardinfo->magic, NETXEN_BDINFO_MAGIC);
993 rv = -1;
994 }
995 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
996 printk("%s: Unknown board config version."
997 " Read %x, expected %x\n", netxen_nic_driver_name,
998 boardinfo->header_version, NETXEN_BDINFO_VERSION);
999 rv = -1;
1000 }
1001
1002 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
1003 switch ((netxen_brdtype_t) boardinfo->board_type) {
1004 case NETXEN_BRDTYPE_P2_SB35_4G:
1005 adapter->ahw.board_type = NETXEN_NIC_GBE;
1006 break;
1007 case NETXEN_BRDTYPE_P2_SB31_10G:
1008 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1009 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1010 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1011 adapter->ahw.board_type = NETXEN_NIC_XGBE;
1012 break;
1013 case NETXEN_BRDTYPE_P1_BD:
1014 case NETXEN_BRDTYPE_P1_SB:
1015 case NETXEN_BRDTYPE_P1_SMAX:
1016 case NETXEN_BRDTYPE_P1_SOCK:
1017 adapter->ahw.board_type = NETXEN_NIC_GBE;
1018 break;
1019 default:
1020 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
1021 boardinfo->board_type);
1022 break;
1023 }
1024
1025 return rv;
1026 }
1027
1028 /* NIU access sections */
1029
1030 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1031 {
1032 netxen_nic_write_w0(adapter,
1033 NETXEN_NIU_GB_MAX_FRAME_SIZE(
1034 physical_port[adapter->portnum]), new_mtu);
1035 return 0;
1036 }
1037
1038 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1039 {
1040 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1041 if (physical_port[adapter->portnum] == 0)
1042 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1043 new_mtu);
1044 else
1045 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
1046 new_mtu);
1047 return 0;
1048 }
1049
1050 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1051 {
1052 netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]);
1053 }
1054
1055 void
1056 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
1057 int data)
1058 {
1059 void __iomem *addr;
1060
1061 if (ADDR_IN_WINDOW1(off)) {
1062 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1063 } else {
1064 netxen_nic_pci_change_crbwindow(adapter, 0);
1065 addr = pci_base_offset(adapter, off);
1066 writel(data, addr);
1067 netxen_nic_pci_change_crbwindow(adapter, 1);
1068 }
1069 }
1070
1071 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1072 {
1073 __u32 status;
1074 __u32 autoneg;
1075 __u32 mode;
1076
1077 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1078 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1079 if (adapter->phy_read
1080 && adapter->
1081 phy_read(adapter,
1082 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1083 &status) == 0) {
1084 if (netxen_get_phy_link(status)) {
1085 switch (netxen_get_phy_speed(status)) {
1086 case 0:
1087 adapter->link_speed = SPEED_10;
1088 break;
1089 case 1:
1090 adapter->link_speed = SPEED_100;
1091 break;
1092 case 2:
1093 adapter->link_speed = SPEED_1000;
1094 break;
1095 default:
1096 adapter->link_speed = -1;
1097 break;
1098 }
1099 switch (netxen_get_phy_duplex(status)) {
1100 case 0:
1101 adapter->link_duplex = DUPLEX_HALF;
1102 break;
1103 case 1:
1104 adapter->link_duplex = DUPLEX_FULL;
1105 break;
1106 default:
1107 adapter->link_duplex = -1;
1108 break;
1109 }
1110 if (adapter->phy_read
1111 && adapter->
1112 phy_read(adapter,
1113 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1114 &autoneg) != 0)
1115 adapter->link_autoneg = autoneg;
1116 } else
1117 goto link_down;
1118 } else {
1119 link_down:
1120 adapter->link_speed = -1;
1121 adapter->link_duplex = -1;
1122 }
1123 }
1124 }
1125
1126 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1127 {
1128 int valid = 1;
1129 u32 fw_major = 0;
1130 u32 fw_minor = 0;
1131 u32 fw_build = 0;
1132 char brd_name[NETXEN_MAX_SHORT_NAME];
1133 struct netxen_new_user_info user_info;
1134 int i, addr = NETXEN_USER_START;
1135 __le32 *ptr32;
1136
1137 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1138 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
1139 printk
1140 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
1141 board_info->magic, NETXEN_BDINFO_MAGIC);
1142 valid = 0;
1143 }
1144 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
1145 printk("NetXen Unknown board config version."
1146 " Read %x, expected %x\n",
1147 board_info->header_version, NETXEN_BDINFO_VERSION);
1148 valid = 0;
1149 }
1150 if (valid) {
1151 ptr32 = (u32 *) & user_info;
1152 for (i = 0;
1153 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
1154 i++) {
1155 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1156 printk("%s: ERROR reading %s board userarea.\n",
1157 netxen_nic_driver_name,
1158 netxen_nic_driver_name);
1159 return;
1160 }
1161 ptr32++;
1162 addr += sizeof(u32);
1163 }
1164 get_brd_name_by_type(board_info->board_type, brd_name);
1165
1166 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1167 brd_name, user_info.serial_num, board_info->chip_id);
1168
1169 printk("NetXen %s Board #%d, Chip id 0x%x\n",
1170 board_info->board_type == 0x0b ? "XGB" : "GBE",
1171 board_info->board_num, board_info->chip_id);
1172 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1173 NETXEN_FW_VERSION_MAJOR));
1174 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1175 NETXEN_FW_VERSION_MINOR));
1176 fw_build =
1177 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1178
1179 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1180 fw_build);
1181 }
1182 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1183 printk(KERN_ERR "The mismatch in driver version and firmware "
1184 "version major number\n"
1185 "Driver version major number = %d \t"
1186 "Firmware version major number = %d \n",
1187 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1188 adapter->driver_mismatch = 1;
1189 }
1190 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1191 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1192 printk(KERN_ERR "The mismatch in driver version and firmware "
1193 "version minor number\n"
1194 "Driver version minor number = %d \t"
1195 "Firmware version minor number = %d \n",
1196 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1197 adapter->driver_mismatch = 1;
1198 }
1199 if (adapter->driver_mismatch)
1200 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1201 fw_major, fw_minor);
1202 }
1203
WRT350N Kernel Patches