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x86: disable BTS ptrace extensions for now
[wrt350n-kernel.git] / drivers / mtd / nand / nand_base.c
blob7acb1a0e7409fbf950a06e97f8e58b3a1be38559
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/compatmac.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <asm/io.h>
50
51 #ifdef CONFIG_MTD_PARTITIONS
52 #include <linux/mtd/partitions.h>
53 #endif
54
55 /* Define default oob placement schemes for large and small page devices */
56 static struct nand_ecclayout nand_oob_8 = {
57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
64 };
65
66 static struct nand_ecclayout nand_oob_16 = {
67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
72 };
73
74 static struct nand_ecclayout nand_oob_64 = {
75 .eccbytes = 24,
76 .eccpos = {
77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
83 };
84
85 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
86 int new_state);
87
88 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
89 struct mtd_oob_ops *ops);
90
91 /*
92 * For devices which display every fart in the system on a separate LED. Is
93 * compiled away when LED support is disabled.
94 */
95 DEFINE_LED_TRIGGER(nand_led_trigger);
96
97 /**
98 * nand_release_device - [GENERIC] release chip
99 * @mtd: MTD device structure
100 *
101 * Deselect, release chip lock and wake up anyone waiting on the device
102 */
103 static void nand_release_device(struct mtd_info *mtd)
104 {
105 struct nand_chip *chip = mtd->priv;
106
107 /* De-select the NAND device */
108 chip->select_chip(mtd, -1);
109
110 /* Release the controller and the chip */
111 spin_lock(&chip->controller->lock);
112 chip->controller->active = NULL;
113 chip->state = FL_READY;
114 wake_up(&chip->controller->wq);
115 spin_unlock(&chip->controller->lock);
116 }
117
118 /**
119 * nand_read_byte - [DEFAULT] read one byte from the chip
120 * @mtd: MTD device structure
121 *
122 * Default read function for 8bit buswith
123 */
124 static uint8_t nand_read_byte(struct mtd_info *mtd)
125 {
126 struct nand_chip *chip = mtd->priv;
127 return readb(chip->IO_ADDR_R);
128 }
129
130 /**
131 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
132 * @mtd: MTD device structure
133 *
134 * Default read function for 16bit buswith with
135 * endianess conversion
136 */
137 static uint8_t nand_read_byte16(struct mtd_info *mtd)
138 {
139 struct nand_chip *chip = mtd->priv;
140 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
141 }
142
143 /**
144 * nand_read_word - [DEFAULT] read one word from the chip
145 * @mtd: MTD device structure
146 *
147 * Default read function for 16bit buswith without
148 * endianess conversion
149 */
150 static u16 nand_read_word(struct mtd_info *mtd)
151 {
152 struct nand_chip *chip = mtd->priv;
153 return readw(chip->IO_ADDR_R);
154 }
155
156 /**
157 * nand_select_chip - [DEFAULT] control CE line
158 * @mtd: MTD device structure
159 * @chipnr: chipnumber to select, -1 for deselect
160 *
161 * Default select function for 1 chip devices.
162 */
163 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
164 {
165 struct nand_chip *chip = mtd->priv;
166
167 switch (chipnr) {
168 case -1:
169 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
170 break;
171 case 0:
172 break;
173
174 default:
175 BUG();
176 }
177 }
178
179 /**
180 * nand_write_buf - [DEFAULT] write buffer to chip
181 * @mtd: MTD device structure
182 * @buf: data buffer
183 * @len: number of bytes to write
184 *
185 * Default write function for 8bit buswith
186 */
187 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
188 {
189 int i;
190 struct nand_chip *chip = mtd->priv;
191
192 for (i = 0; i < len; i++)
193 writeb(buf[i], chip->IO_ADDR_W);
194 }
195
196 /**
197 * nand_read_buf - [DEFAULT] read chip data into buffer
198 * @mtd: MTD device structure
199 * @buf: buffer to store date
200 * @len: number of bytes to read
201 *
202 * Default read function for 8bit buswith
203 */
204 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
205 {
206 int i;
207 struct nand_chip *chip = mtd->priv;
208
209 for (i = 0; i < len; i++)
210 buf[i] = readb(chip->IO_ADDR_R);
211 }
212
213 /**
214 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
215 * @mtd: MTD device structure
216 * @buf: buffer containing the data to compare
217 * @len: number of bytes to compare
218 *
219 * Default verify function for 8bit buswith
220 */
221 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
222 {
223 int i;
224 struct nand_chip *chip = mtd->priv;
225
226 for (i = 0; i < len; i++)
227 if (buf[i] != readb(chip->IO_ADDR_R))
228 return -EFAULT;
229 return 0;
230 }
231
232 /**
233 * nand_write_buf16 - [DEFAULT] write buffer to chip
234 * @mtd: MTD device structure
235 * @buf: data buffer
236 * @len: number of bytes to write
237 *
238 * Default write function for 16bit buswith
239 */
240 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
241 {
242 int i;
243 struct nand_chip *chip = mtd->priv;
244 u16 *p = (u16 *) buf;
245 len >>= 1;
246
247 for (i = 0; i < len; i++)
248 writew(p[i], chip->IO_ADDR_W);
249
250 }
251
252 /**
253 * nand_read_buf16 - [DEFAULT] read chip data into buffer
254 * @mtd: MTD device structure
255 * @buf: buffer to store date
256 * @len: number of bytes to read
257 *
258 * Default read function for 16bit buswith
259 */
260 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
261 {
262 int i;
263 struct nand_chip *chip = mtd->priv;
264 u16 *p = (u16 *) buf;
265 len >>= 1;
266
267 for (i = 0; i < len; i++)
268 p[i] = readw(chip->IO_ADDR_R);
269 }
270
271 /**
272 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
273 * @mtd: MTD device structure
274 * @buf: buffer containing the data to compare
275 * @len: number of bytes to compare
276 *
277 * Default verify function for 16bit buswith
278 */
279 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
280 {
281 int i;
282 struct nand_chip *chip = mtd->priv;
283 u16 *p = (u16 *) buf;
284 len >>= 1;
285
286 for (i = 0; i < len; i++)
287 if (p[i] != readw(chip->IO_ADDR_R))
288 return -EFAULT;
289
290 return 0;
291 }
292
293 /**
294 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
295 * @mtd: MTD device structure
296 * @ofs: offset from device start
297 * @getchip: 0, if the chip is already selected
298 *
299 * Check, if the block is bad.
300 */
301 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
302 {
303 int page, chipnr, res = 0;
304 struct nand_chip *chip = mtd->priv;
305 u16 bad;
306
307 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
308
309 if (getchip) {
310 chipnr = (int)(ofs >> chip->chip_shift);
311
312 nand_get_device(chip, mtd, FL_READING);
313
314 /* Select the NAND device */
315 chip->select_chip(mtd, chipnr);
316 }
317
318 if (chip->options & NAND_BUSWIDTH_16) {
319 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
320 page);
321 bad = cpu_to_le16(chip->read_word(mtd));
322 if (chip->badblockpos & 0x1)
323 bad >>= 8;
324 if ((bad & 0xFF) != 0xff)
325 res = 1;
326 } else {
327 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
328 if (chip->read_byte(mtd) != 0xff)
329 res = 1;
330 }
331
332 if (getchip)
333 nand_release_device(mtd);
334
335 return res;
336 }
337
338 /**
339 * nand_default_block_markbad - [DEFAULT] mark a block bad
340 * @mtd: MTD device structure
341 * @ofs: offset from device start
342 *
343 * This is the default implementation, which can be overridden by
344 * a hardware specific driver.
345 */
346 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
347 {
348 struct nand_chip *chip = mtd->priv;
349 uint8_t buf[2] = { 0, 0 };
350 int block, ret;
351
352 /* Get block number */
353 block = (int)(ofs >> chip->bbt_erase_shift);
354 if (chip->bbt)
355 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
356
357 /* Do we have a flash based bad block table ? */
358 if (chip->options & NAND_USE_FLASH_BBT)
359 ret = nand_update_bbt(mtd, ofs);
360 else {
361 /* We write two bytes, so we dont have to mess with 16 bit
362 * access
363 */
364 nand_get_device(chip, mtd, FL_WRITING);
365 ofs += mtd->oobsize;
366 chip->ops.len = chip->ops.ooblen = 2;
367 chip->ops.datbuf = NULL;
368 chip->ops.oobbuf = buf;
369 chip->ops.ooboffs = chip->badblockpos & ~0x01;
370
371 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
372 nand_release_device(mtd);
373 }
374 if (!ret)
375 mtd->ecc_stats.badblocks++;
376
377 return ret;
378 }
379
380 /**
381 * nand_check_wp - [GENERIC] check if the chip is write protected
382 * @mtd: MTD device structure
383 * Check, if the device is write protected
384 *
385 * The function expects, that the device is already selected
386 */
387 static int nand_check_wp(struct mtd_info *mtd)
388 {
389 struct nand_chip *chip = mtd->priv;
390 /* Check the WP bit */
391 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
392 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
393 }
394
395 /**
396 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
397 * @mtd: MTD device structure
398 * @ofs: offset from device start
399 * @getchip: 0, if the chip is already selected
400 * @allowbbt: 1, if its allowed to access the bbt area
401 *
402 * Check, if the block is bad. Either by reading the bad block table or
403 * calling of the scan function.
404 */
405 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
406 int allowbbt)
407 {
408 struct nand_chip *chip = mtd->priv;
409
410 if (!chip->bbt)
411 return chip->block_bad(mtd, ofs, getchip);
412
413 /* Return info from the table */
414 return nand_isbad_bbt(mtd, ofs, allowbbt);
415 }
416
417 /*
418 * Wait for the ready pin, after a command
419 * The timeout is catched later.
420 */
421 void nand_wait_ready(struct mtd_info *mtd)
422 {
423 struct nand_chip *chip = mtd->priv;
424 unsigned long timeo = jiffies + 2;
425
426 led_trigger_event(nand_led_trigger, LED_FULL);
427 /* wait until command is processed or timeout occures */
428 do {
429 if (chip->dev_ready(mtd))
430 break;
431 touch_softlockup_watchdog();
432 } while (time_before(jiffies, timeo));
433 led_trigger_event(nand_led_trigger, LED_OFF);
434 }
435 EXPORT_SYMBOL_GPL(nand_wait_ready);
436
437 /**
438 * nand_command - [DEFAULT] Send command to NAND device
439 * @mtd: MTD device structure
440 * @command: the command to be sent
441 * @column: the column address for this command, -1 if none
442 * @page_addr: the page address for this command, -1 if none
443 *
444 * Send command to NAND device. This function is used for small page
445 * devices (256/512 Bytes per page)
446 */
447 static void nand_command(struct mtd_info *mtd, unsigned int command,
448 int column, int page_addr)
449 {
450 register struct nand_chip *chip = mtd->priv;
451 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
452
453 /*
454 * Write out the command to the device.
455 */
456 if (command == NAND_CMD_SEQIN) {
457 int readcmd;
458
459 if (column >= mtd->writesize) {
460 /* OOB area */
461 column -= mtd->writesize;
462 readcmd = NAND_CMD_READOOB;
463 } else if (column < 256) {
464 /* First 256 bytes --> READ0 */
465 readcmd = NAND_CMD_READ0;
466 } else {
467 column -= 256;
468 readcmd = NAND_CMD_READ1;
469 }
470 chip->cmd_ctrl(mtd, readcmd, ctrl);
471 ctrl &= ~NAND_CTRL_CHANGE;
472 }
473 chip->cmd_ctrl(mtd, command, ctrl);
474
475 /*
476 * Address cycle, when necessary
477 */
478 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
479 /* Serially input address */
480 if (column != -1) {
481 /* Adjust columns for 16 bit buswidth */
482 if (chip->options & NAND_BUSWIDTH_16)
483 column >>= 1;
484 chip->cmd_ctrl(mtd, column, ctrl);
485 ctrl &= ~NAND_CTRL_CHANGE;
486 }
487 if (page_addr != -1) {
488 chip->cmd_ctrl(mtd, page_addr, ctrl);
489 ctrl &= ~NAND_CTRL_CHANGE;
490 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
491 /* One more address cycle for devices > 32MiB */
492 if (chip->chipsize > (32 << 20))
493 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
494 }
495 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
496
497 /*
498 * program and erase have their own busy handlers
499 * status and sequential in needs no delay
500 */
501 switch (command) {
502
503 case NAND_CMD_PAGEPROG:
504 case NAND_CMD_ERASE1:
505 case NAND_CMD_ERASE2:
506 case NAND_CMD_SEQIN:
507 case NAND_CMD_STATUS:
508 return;
509
510 case NAND_CMD_RESET:
511 if (chip->dev_ready)
512 break;
513 udelay(chip->chip_delay);
514 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
515 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
516 chip->cmd_ctrl(mtd,
517 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
518 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
519 return;
520
521 /* This applies to read commands */
522 default:
523 /*
524 * If we don't have access to the busy pin, we apply the given
525 * command delay
526 */
527 if (!chip->dev_ready) {
528 udelay(chip->chip_delay);
529 return;
530 }
531 }
532 /* Apply this short delay always to ensure that we do wait tWB in
533 * any case on any machine. */
534 ndelay(100);
535
536 nand_wait_ready(mtd);
537 }
538
539 /**
540 * nand_command_lp - [DEFAULT] Send command to NAND large page device
541 * @mtd: MTD device structure
542 * @command: the command to be sent
543 * @column: the column address for this command, -1 if none
544 * @page_addr: the page address for this command, -1 if none
545 *
546 * Send command to NAND device. This is the version for the new large page
547 * devices We dont have the separate regions as we have in the small page
548 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
549 */
550 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
551 int column, int page_addr)
552 {
553 register struct nand_chip *chip = mtd->priv;
554
555 /* Emulate NAND_CMD_READOOB */
556 if (command == NAND_CMD_READOOB) {
557 column += mtd->writesize;
558 command = NAND_CMD_READ0;
559 }
560
561 /* Command latch cycle */
562 chip->cmd_ctrl(mtd, command & 0xff,
563 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
564
565 if (column != -1 || page_addr != -1) {
566 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
567
568 /* Serially input address */
569 if (column != -1) {
570 /* Adjust columns for 16 bit buswidth */
571 if (chip->options & NAND_BUSWIDTH_16)
572 column >>= 1;
573 chip->cmd_ctrl(mtd, column, ctrl);
574 ctrl &= ~NAND_CTRL_CHANGE;
575 chip->cmd_ctrl(mtd, column >> 8, ctrl);
576 }
577 if (page_addr != -1) {
578 chip->cmd_ctrl(mtd, page_addr, ctrl);
579 chip->cmd_ctrl(mtd, page_addr >> 8,
580 NAND_NCE | NAND_ALE);
581 /* One more address cycle for devices > 128MiB */
582 if (chip->chipsize > (128 << 20))
583 chip->cmd_ctrl(mtd, page_addr >> 16,
584 NAND_NCE | NAND_ALE);
585 }
586 }
587 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
588
589 /*
590 * program and erase have their own busy handlers
591 * status, sequential in, and deplete1 need no delay
592 */
593 switch (command) {
594
595 case NAND_CMD_CACHEDPROG:
596 case NAND_CMD_PAGEPROG:
597 case NAND_CMD_ERASE1:
598 case NAND_CMD_ERASE2:
599 case NAND_CMD_SEQIN:
600 case NAND_CMD_RNDIN:
601 case NAND_CMD_STATUS:
602 case NAND_CMD_DEPLETE1:
603 return;
604
605 /*
606 * read error status commands require only a short delay
607 */
608 case NAND_CMD_STATUS_ERROR:
609 case NAND_CMD_STATUS_ERROR0:
610 case NAND_CMD_STATUS_ERROR1:
611 case NAND_CMD_STATUS_ERROR2:
612 case NAND_CMD_STATUS_ERROR3:
613 udelay(chip->chip_delay);
614 return;
615
616 case NAND_CMD_RESET:
617 if (chip->dev_ready)
618 break;
619 udelay(chip->chip_delay);
620 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
621 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
622 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
623 NAND_NCE | NAND_CTRL_CHANGE);
624 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
625 return;
626
627 case NAND_CMD_RNDOUT:
628 /* No ready / busy check necessary */
629 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
630 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
631 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
632 NAND_NCE | NAND_CTRL_CHANGE);
633 return;
634
635 case NAND_CMD_READ0:
636 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
637 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
638 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
639 NAND_NCE | NAND_CTRL_CHANGE);
640
641 /* This applies to read commands */
642 default:
643 /*
644 * If we don't have access to the busy pin, we apply the given
645 * command delay
646 */
647 if (!chip->dev_ready) {
648 udelay(chip->chip_delay);
649 return;
650 }
651 }
652
653 /* Apply this short delay always to ensure that we do wait tWB in
654 * any case on any machine. */
655 ndelay(100);
656
657 nand_wait_ready(mtd);
658 }
659
660 /**
661 * nand_get_device - [GENERIC] Get chip for selected access
662 * @chip: the nand chip descriptor
663 * @mtd: MTD device structure
664 * @new_state: the state which is requested
665 *
666 * Get the device and lock it for exclusive access
667 */
668 static int
669 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
670 {
671 spinlock_t *lock = &chip->controller->lock;
672 wait_queue_head_t *wq = &chip->controller->wq;
673 DECLARE_WAITQUEUE(wait, current);
674 retry:
675 spin_lock(lock);
676
677 /* Hardware controller shared among independend devices */
678 /* Hardware controller shared among independend devices */
679 if (!chip->controller->active)
680 chip->controller->active = chip;
681
682 if (chip->controller->active == chip && chip->state == FL_READY) {
683 chip->state = new_state;
684 spin_unlock(lock);
685 return 0;
686 }
687 if (new_state == FL_PM_SUSPENDED) {
688 spin_unlock(lock);
689 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
690 }
691 set_current_state(TASK_UNINTERRUPTIBLE);
692 add_wait_queue(wq, &wait);
693 spin_unlock(lock);
694 schedule();
695 remove_wait_queue(wq, &wait);
696 goto retry;
697 }
698
699 /**
700 * nand_wait - [DEFAULT] wait until the command is done
701 * @mtd: MTD device structure
702 * @chip: NAND chip structure
703 *
704 * Wait for command done. This applies to erase and program only
705 * Erase can take up to 400ms and program up to 20ms according to
706 * general NAND and SmartMedia specs
707 */
708 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
709 {
710
711 unsigned long timeo = jiffies;
712 int status, state = chip->state;
713
714 if (state == FL_ERASING)
715 timeo += (HZ * 400) / 1000;
716 else
717 timeo += (HZ * 20) / 1000;
718
719 led_trigger_event(nand_led_trigger, LED_FULL);
720
721 /* Apply this short delay always to ensure that we do wait tWB in
722 * any case on any machine. */
723 ndelay(100);
724
725 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
726 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
727 else
728 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
729
730 while (time_before(jiffies, timeo)) {
731 if (chip->dev_ready) {
732 if (chip->dev_ready(mtd))
733 break;
734 } else {
735 if (chip->read_byte(mtd) & NAND_STATUS_READY)
736 break;
737 }
738 cond_resched();
739 }
740 led_trigger_event(nand_led_trigger, LED_OFF);
741
742 status = (int)chip->read_byte(mtd);
743 return status;
744 }
745
746 /**
747 * nand_read_page_raw - [Intern] read raw page data without ecc
748 * @mtd: mtd info structure
749 * @chip: nand chip info structure
750 * @buf: buffer to store read data
751 */
752 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
753 uint8_t *buf)
754 {
755 chip->read_buf(mtd, buf, mtd->writesize);
756 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
757 return 0;
758 }
759
760 /**
761 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
762 * @mtd: mtd info structure
763 * @chip: nand chip info structure
764 * @buf: buffer to store read data
765 */
766 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
767 uint8_t *buf)
768 {
769 int i, eccsize = chip->ecc.size;
770 int eccbytes = chip->ecc.bytes;
771 int eccsteps = chip->ecc.steps;
772 uint8_t *p = buf;
773 uint8_t *ecc_calc = chip->buffers->ecccalc;
774 uint8_t *ecc_code = chip->buffers->ecccode;
775 uint32_t *eccpos = chip->ecc.layout->eccpos;
776
777 chip->ecc.read_page_raw(mtd, chip, buf);
778
779 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
780 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
781
782 for (i = 0; i < chip->ecc.total; i++)
783 ecc_code[i] = chip->oob_poi[eccpos[i]];
784
785 eccsteps = chip->ecc.steps;
786 p = buf;
787
788 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
789 int stat;
790
791 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
792 if (stat < 0)
793 mtd->ecc_stats.failed++;
794 else
795 mtd->ecc_stats.corrected += stat;
796 }
797 return 0;
798 }
799
800 /**
801 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
802 * @mtd: mtd info structure
803 * @chip: nand chip info structure
804 * @buf: buffer to store read data
805 *
806 * Not for syndrome calculating ecc controllers which need a special oob layout
807 */
808 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
809 uint8_t *buf)
810 {
811 int i, eccsize = chip->ecc.size;
812 int eccbytes = chip->ecc.bytes;
813 int eccsteps = chip->ecc.steps;
814 uint8_t *p = buf;
815 uint8_t *ecc_calc = chip->buffers->ecccalc;
816 uint8_t *ecc_code = chip->buffers->ecccode;
817 uint32_t *eccpos = chip->ecc.layout->eccpos;
818
819 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
820 chip->ecc.hwctl(mtd, NAND_ECC_READ);
821 chip->read_buf(mtd, p, eccsize);
822 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
823 }
824 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
825
826 for (i = 0; i < chip->ecc.total; i++)
827 ecc_code[i] = chip->oob_poi[eccpos[i]];
828
829 eccsteps = chip->ecc.steps;
830 p = buf;
831
832 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
833 int stat;
834
835 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
836 if (stat < 0)
837 mtd->ecc_stats.failed++;
838 else
839 mtd->ecc_stats.corrected += stat;
840 }
841 return 0;
842 }
843
844 /**
845 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
846 * @mtd: mtd info structure
847 * @chip: nand chip info structure
848 * @buf: buffer to store read data
849 *
850 * The hw generator calculates the error syndrome automatically. Therefor
851 * we need a special oob layout and handling.
852 */
853 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
854 uint8_t *buf)
855 {
856 int i, eccsize = chip->ecc.size;
857 int eccbytes = chip->ecc.bytes;
858 int eccsteps = chip->ecc.steps;
859 uint8_t *p = buf;
860 uint8_t *oob = chip->oob_poi;
861
862 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
863 int stat;
864
865 chip->ecc.hwctl(mtd, NAND_ECC_READ);
866 chip->read_buf(mtd, p, eccsize);
867
868 if (chip->ecc.prepad) {
869 chip->read_buf(mtd, oob, chip->ecc.prepad);
870 oob += chip->ecc.prepad;
871 }
872
873 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
874 chip->read_buf(mtd, oob, eccbytes);
875 stat = chip->ecc.correct(mtd, p, oob, NULL);
876
877 if (stat < 0)
878 mtd->ecc_stats.failed++;
879 else
880 mtd->ecc_stats.corrected += stat;
881
882 oob += eccbytes;
883
884 if (chip->ecc.postpad) {
885 chip->read_buf(mtd, oob, chip->ecc.postpad);
886 oob += chip->ecc.postpad;
887 }
888 }
889
890 /* Calculate remaining oob bytes */
891 i = mtd->oobsize - (oob - chip->oob_poi);
892 if (i)
893 chip->read_buf(mtd, oob, i);
894
895 return 0;
896 }
897
898 /**
899 * nand_transfer_oob - [Internal] Transfer oob to client buffer
900 * @chip: nand chip structure
901 * @oob: oob destination address
902 * @ops: oob ops structure
903 * @len: size of oob to transfer
904 */
905 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
906 struct mtd_oob_ops *ops, size_t len)
907 {
908 switch(ops->mode) {
909
910 case MTD_OOB_PLACE:
911 case MTD_OOB_RAW:
912 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
913 return oob + len;
914
915 case MTD_OOB_AUTO: {
916 struct nand_oobfree *free = chip->ecc.layout->oobfree;
917 uint32_t boffs = 0, roffs = ops->ooboffs;
918 size_t bytes = 0;
919
920 for(; free->length && len; free++, len -= bytes) {
921 /* Read request not from offset 0 ? */
922 if (unlikely(roffs)) {
923 if (roffs >= free->length) {
924 roffs -= free->length;
925 continue;
926 }
927 boffs = free->offset + roffs;
928 bytes = min_t(size_t, len,
929 (free->length - roffs));
930 roffs = 0;
931 } else {
932 bytes = min_t(size_t, len, free->length);
933 boffs = free->offset;
934 }
935 memcpy(oob, chip->oob_poi + boffs, bytes);
936 oob += bytes;
937 }
938 return oob;
939 }
940 default:
941 BUG();
942 }
943 return NULL;
944 }
945
946 /**
947 * nand_do_read_ops - [Internal] Read data with ECC
948 *
949 * @mtd: MTD device structure
950 * @from: offset to read from
951 * @ops: oob ops structure
952 *
953 * Internal function. Called with chip held.
954 */
955 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
956 struct mtd_oob_ops *ops)
957 {
958 int chipnr, page, realpage, col, bytes, aligned;
959 struct nand_chip *chip = mtd->priv;
960 struct mtd_ecc_stats stats;
961 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
962 int sndcmd = 1;
963 int ret = 0;
964 uint32_t readlen = ops->len;
965 uint32_t oobreadlen = ops->ooblen;
966 uint8_t *bufpoi, *oob, *buf;
967
968 stats = mtd->ecc_stats;
969
970 chipnr = (int)(from >> chip->chip_shift);
971 chip->select_chip(mtd, chipnr);
972
973 realpage = (int)(from >> chip->page_shift);
974 page = realpage & chip->pagemask;
975
976 col = (int)(from & (mtd->writesize - 1));
977
978 buf = ops->datbuf;
979 oob = ops->oobbuf;
980
981 while(1) {
982 bytes = min(mtd->writesize - col, readlen);
983 aligned = (bytes == mtd->writesize);
984
985 /* Is the current page in the buffer ? */
986 if (realpage != chip->pagebuf || oob) {
987 bufpoi = aligned ? buf : chip->buffers->databuf;
988
989 if (likely(sndcmd)) {
990 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
991 sndcmd = 0;
992 }
993
994 /* Now read the page into the buffer */
995 if (unlikely(ops->mode == MTD_OOB_RAW))
996 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
997 else
998 ret = chip->ecc.read_page(mtd, chip, bufpoi);
999 if (ret < 0)
1000 break;
1001
1002 /* Transfer not aligned data */
1003 if (!aligned) {
1004 chip->pagebuf = realpage;
1005 memcpy(buf, chip->buffers->databuf + col, bytes);
1006 }
1007
1008 buf += bytes;
1009
1010 if (unlikely(oob)) {
1011 /* Raw mode does data:oob:data:oob */
1012 if (ops->mode != MTD_OOB_RAW) {
1013 int toread = min(oobreadlen,
1014 chip->ecc.layout->oobavail);
1015 if (toread) {
1016 oob = nand_transfer_oob(chip,
1017 oob, ops, toread);
1018 oobreadlen -= toread;
1019 }
1020 } else
1021 buf = nand_transfer_oob(chip,
1022 buf, ops, mtd->oobsize);
1023 }
1024
1025 if (!(chip->options & NAND_NO_READRDY)) {
1026 /*
1027 * Apply delay or wait for ready/busy pin. Do
1028 * this before the AUTOINCR check, so no
1029 * problems arise if a chip which does auto
1030 * increment is marked as NOAUTOINCR by the
1031 * board driver.
1032 */
1033 if (!chip->dev_ready)
1034 udelay(chip->chip_delay);
1035 else
1036 nand_wait_ready(mtd);
1037 }
1038 } else {
1039 memcpy(buf, chip->buffers->databuf + col, bytes);
1040 buf += bytes;
1041 }
1042
1043 readlen -= bytes;
1044
1045 if (!readlen)
1046 break;
1047
1048 /* For subsequent reads align to page boundary. */
1049 col = 0;
1050 /* Increment page address */
1051 realpage++;
1052
1053 page = realpage & chip->pagemask;
1054 /* Check, if we cross a chip boundary */
1055 if (!page) {
1056 chipnr++;
1057 chip->select_chip(mtd, -1);
1058 chip->select_chip(mtd, chipnr);
1059 }
1060
1061 /* Check, if the chip supports auto page increment
1062 * or if we have hit a block boundary.
1063 */
1064 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1065 sndcmd = 1;
1066 }
1067
1068 ops->retlen = ops->len - (size_t) readlen;
1069 if (oob)
1070 ops->oobretlen = ops->ooblen - oobreadlen;
1071
1072 if (ret)
1073 return ret;
1074
1075 if (mtd->ecc_stats.failed - stats.failed)
1076 return -EBADMSG;
1077
1078 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1079 }
1080
1081 /**
1082 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1083 * @mtd: MTD device structure
1084 * @from: offset to read from
1085 * @len: number of bytes to read
1086 * @retlen: pointer to variable to store the number of read bytes
1087 * @buf: the databuffer to put data
1088 *
1089 * Get hold of the chip and call nand_do_read
1090 */
1091 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1092 size_t *retlen, uint8_t *buf)
1093 {
1094 struct nand_chip *chip = mtd->priv;
1095 int ret;
1096
1097 /* Do not allow reads past end of device */
1098 if ((from + len) > mtd->size)
1099 return -EINVAL;
1100 if (!len)
1101 return 0;
1102
1103 nand_get_device(chip, mtd, FL_READING);
1104
1105 chip->ops.len = len;
1106 chip->ops.datbuf = buf;
1107 chip->ops.oobbuf = NULL;
1108
1109 ret = nand_do_read_ops(mtd, from, &chip->ops);
1110
1111 *retlen = chip->ops.retlen;
1112
1113 nand_release_device(mtd);
1114
1115 return ret;
1116 }
1117
1118 /**
1119 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1120 * @mtd: mtd info structure
1121 * @chip: nand chip info structure
1122 * @page: page number to read
1123 * @sndcmd: flag whether to issue read command or not
1124 */
1125 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1126 int page, int sndcmd)
1127 {
1128 if (sndcmd) {
1129 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1130 sndcmd = 0;
1131 }
1132 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1133 return sndcmd;
1134 }
1135
1136 /**
1137 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1138 * with syndromes
1139 * @mtd: mtd info structure
1140 * @chip: nand chip info structure
1141 * @page: page number to read
1142 * @sndcmd: flag whether to issue read command or not
1143 */
1144 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1145 int page, int sndcmd)
1146 {
1147 uint8_t *buf = chip->oob_poi;
1148 int length = mtd->oobsize;
1149 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1150 int eccsize = chip->ecc.size;
1151 uint8_t *bufpoi = buf;
1152 int i, toread, sndrnd = 0, pos;
1153
1154 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1155 for (i = 0; i < chip->ecc.steps; i++) {
1156 if (sndrnd) {
1157 pos = eccsize + i * (eccsize + chunk);
1158 if (mtd->writesize > 512)
1159 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1160 else
1161 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1162 } else
1163 sndrnd = 1;
1164 toread = min_t(int, length, chunk);
1165 chip->read_buf(mtd, bufpoi, toread);
1166 bufpoi += toread;
1167 length -= toread;
1168 }
1169 if (length > 0)
1170 chip->read_buf(mtd, bufpoi, length);
1171
1172 return 1;
1173 }
1174
1175 /**
1176 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1177 * @mtd: mtd info structure
1178 * @chip: nand chip info structure
1179 * @page: page number to write
1180 */
1181 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1182 int page)
1183 {
1184 int status = 0;
1185 const uint8_t *buf = chip->oob_poi;
1186 int length = mtd->oobsize;
1187
1188 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1189 chip->write_buf(mtd, buf, length);
1190 /* Send command to program the OOB data */
1191 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1192
1193 status = chip->waitfunc(mtd, chip);
1194
1195 return status & NAND_STATUS_FAIL ? -EIO : 0;
1196 }
1197
1198 /**
1199 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1200 * with syndrome - only for large page flash !
1201 * @mtd: mtd info structure
1202 * @chip: nand chip info structure
1203 * @page: page number to write
1204 */
1205 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1206 struct nand_chip *chip, int page)
1207 {
1208 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1209 int eccsize = chip->ecc.size, length = mtd->oobsize;
1210 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1211 const uint8_t *bufpoi = chip->oob_poi;
1212
1213 /*
1214 * data-ecc-data-ecc ... ecc-oob
1215 * or
1216 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1217 */
1218 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1219 pos = steps * (eccsize + chunk);
1220 steps = 0;
1221 } else
1222 pos = eccsize;
1223
1224 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1225 for (i = 0; i < steps; i++) {
1226 if (sndcmd) {
1227 if (mtd->writesize <= 512) {
1228 uint32_t fill = 0xFFFFFFFF;
1229
1230 len = eccsize;
1231 while (len > 0) {
1232 int num = min_t(int, len, 4);
1233 chip->write_buf(mtd, (uint8_t *)&fill,
1234 num);
1235 len -= num;
1236 }
1237 } else {
1238 pos = eccsize + i * (eccsize + chunk);
1239 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1240 }
1241 } else
1242 sndcmd = 1;
1243 len = min_t(int, length, chunk);
1244 chip->write_buf(mtd, bufpoi, len);
1245 bufpoi += len;
1246 length -= len;
1247 }
1248 if (length > 0)
1249 chip->write_buf(mtd, bufpoi, length);
1250
1251 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1252 status = chip->waitfunc(mtd, chip);
1253
1254 return status & NAND_STATUS_FAIL ? -EIO : 0;
1255 }
1256
1257 /**
1258 * nand_do_read_oob - [Intern] NAND read out-of-band
1259 * @mtd: MTD device structure
1260 * @from: offset to read from
1261 * @ops: oob operations description structure
1262 *
1263 * NAND read out-of-band data from the spare area
1264 */
1265 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1266 struct mtd_oob_ops *ops)
1267 {
1268 int page, realpage, chipnr, sndcmd = 1;
1269 struct nand_chip *chip = mtd->priv;
1270 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1271 int readlen = ops->ooblen;
1272 int len;
1273 uint8_t *buf = ops->oobbuf;
1274
1275 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1276 (unsigned long long)from, readlen);
1277
1278 if (ops->mode == MTD_OOB_AUTO)
1279 len = chip->ecc.layout->oobavail;
1280 else
1281 len = mtd->oobsize;
1282
1283 if (unlikely(ops->ooboffs >= len)) {
1284 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1285 "Attempt to start read outside oob\n");
1286 return -EINVAL;
1287 }
1288
1289 /* Do not allow reads past end of device */
1290 if (unlikely(from >= mtd->size ||
1291 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1292 (from >> chip->page_shift)) * len)) {
1293 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1294 "Attempt read beyond end of device\n");
1295 return -EINVAL;
1296 }
1297
1298 chipnr = (int)(from >> chip->chip_shift);
1299 chip->select_chip(mtd, chipnr);
1300
1301 /* Shift to get page */
1302 realpage = (int)(from >> chip->page_shift);
1303 page = realpage & chip->pagemask;
1304
1305 while(1) {
1306 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1307
1308 len = min(len, readlen);
1309 buf = nand_transfer_oob(chip, buf, ops, len);
1310
1311 if (!(chip->options & NAND_NO_READRDY)) {
1312 /*
1313 * Apply delay or wait for ready/busy pin. Do this
1314 * before the AUTOINCR check, so no problems arise if a
1315 * chip which does auto increment is marked as
1316 * NOAUTOINCR by the board driver.
1317 */
1318 if (!chip->dev_ready)
1319 udelay(chip->chip_delay);
1320 else
1321 nand_wait_ready(mtd);
1322 }
1323
1324 readlen -= len;
1325 if (!readlen)
1326 break;
1327
1328 /* Increment page address */
1329 realpage++;
1330
1331 page = realpage & chip->pagemask;
1332 /* Check, if we cross a chip boundary */
1333 if (!page) {
1334 chipnr++;
1335 chip->select_chip(mtd, -1);
1336 chip->select_chip(mtd, chipnr);
1337 }
1338
1339 /* Check, if the chip supports auto page increment
1340 * or if we have hit a block boundary.
1341 */
1342 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1343 sndcmd = 1;
1344 }
1345
1346 ops->oobretlen = ops->ooblen;
1347 return 0;
1348 }
1349
1350 /**
1351 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1352 * @mtd: MTD device structure
1353 * @from: offset to read from
1354 * @ops: oob operation description structure
1355 *
1356 * NAND read data and/or out-of-band data
1357 */
1358 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1359 struct mtd_oob_ops *ops)
1360 {
1361 struct nand_chip *chip = mtd->priv;
1362 int ret = -ENOTSUPP;
1363
1364 ops->retlen = 0;
1365
1366 /* Do not allow reads past end of device */
1367 if (ops->datbuf && (from + ops->len) > mtd->size) {
1368 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1369 "Attempt read beyond end of device\n");
1370 return -EINVAL;
1371 }
1372
1373 nand_get_device(chip, mtd, FL_READING);
1374
1375 switch(ops->mode) {
1376 case MTD_OOB_PLACE:
1377 case MTD_OOB_AUTO:
1378 case MTD_OOB_RAW:
1379 break;
1380
1381 default:
1382 goto out;
1383 }
1384
1385 if (!ops->datbuf)
1386 ret = nand_do_read_oob(mtd, from, ops);
1387 else
1388 ret = nand_do_read_ops(mtd, from, ops);
1389
1390 out:
1391 nand_release_device(mtd);
1392 return ret;
1393 }
1394
1395
1396 /**
1397 * nand_write_page_raw - [Intern] raw page write function
1398 * @mtd: mtd info structure
1399 * @chip: nand chip info structure
1400 * @buf: data buffer
1401 */
1402 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1403 const uint8_t *buf)
1404 {
1405 chip->write_buf(mtd, buf, mtd->writesize);
1406 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1407 }
1408
1409 /**
1410 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1411 * @mtd: mtd info structure
1412 * @chip: nand chip info structure
1413 * @buf: data buffer
1414 */
1415 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1416 const uint8_t *buf)
1417 {
1418 int i, eccsize = chip->ecc.size;
1419 int eccbytes = chip->ecc.bytes;
1420 int eccsteps = chip->ecc.steps;
1421 uint8_t *ecc_calc = chip->buffers->ecccalc;
1422 const uint8_t *p = buf;
1423 uint32_t *eccpos = chip->ecc.layout->eccpos;
1424
1425 /* Software ecc calculation */
1426 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1427 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1428
1429 for (i = 0; i < chip->ecc.total; i++)
1430 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1431
1432 chip->ecc.write_page_raw(mtd, chip, buf);
1433 }
1434
1435 /**
1436 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1437 * @mtd: mtd info structure
1438 * @chip: nand chip info structure
1439 * @buf: data buffer
1440 */
1441 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1442 const uint8_t *buf)
1443 {
1444 int i, eccsize = chip->ecc.size;
1445 int eccbytes = chip->ecc.bytes;
1446 int eccsteps = chip->ecc.steps;
1447 uint8_t *ecc_calc = chip->buffers->ecccalc;
1448 const uint8_t *p = buf;
1449 uint32_t *eccpos = chip->ecc.layout->eccpos;
1450
1451 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1452 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1453 chip->write_buf(mtd, p, eccsize);
1454 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1455 }
1456
1457 for (i = 0; i < chip->ecc.total; i++)
1458 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1459
1460 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1461 }
1462
1463 /**
1464 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1465 * @mtd: mtd info structure
1466 * @chip: nand chip info structure
1467 * @buf: data buffer
1468 *
1469 * The hw generator calculates the error syndrome automatically. Therefor
1470 * we need a special oob layout and handling.
1471 */
1472 static void nand_write_page_syndrome(struct mtd_info *mtd,
1473 struct nand_chip *chip, const uint8_t *buf)
1474 {
1475 int i, eccsize = chip->ecc.size;
1476 int eccbytes = chip->ecc.bytes;
1477 int eccsteps = chip->ecc.steps;
1478 const uint8_t *p = buf;
1479 uint8_t *oob = chip->oob_poi;
1480
1481 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1482
1483 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1484 chip->write_buf(mtd, p, eccsize);
1485
1486 if (chip->ecc.prepad) {
1487 chip->write_buf(mtd, oob, chip->ecc.prepad);
1488 oob += chip->ecc.prepad;
1489 }
1490
1491 chip->ecc.calculate(mtd, p, oob);
1492 chip->write_buf(mtd, oob, eccbytes);
1493 oob += eccbytes;
1494
1495 if (chip->ecc.postpad) {
1496 chip->write_buf(mtd, oob, chip->ecc.postpad);
1497 oob += chip->ecc.postpad;
1498 }
1499 }
1500
1501 /* Calculate remaining oob bytes */
1502 i = mtd->oobsize - (oob - chip->oob_poi);
1503 if (i)
1504 chip->write_buf(mtd, oob, i);
1505 }
1506
1507 /**
1508 * nand_write_page - [REPLACEABLE] write one page
1509 * @mtd: MTD device structure
1510 * @chip: NAND chip descriptor
1511 * @buf: the data to write
1512 * @page: page number to write
1513 * @cached: cached programming
1514 * @raw: use _raw version of write_page
1515 */
1516 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1517 const uint8_t *buf, int page, int cached, int raw)
1518 {
1519 int status;
1520
1521 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1522
1523 if (unlikely(raw))
1524 chip->ecc.write_page_raw(mtd, chip, buf);
1525 else
1526 chip->ecc.write_page(mtd, chip, buf);
1527
1528 /*
1529 * Cached progamming disabled for now, Not sure if its worth the
1530 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1531 */
1532 cached = 0;
1533
1534 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1535
1536 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1537 status = chip->waitfunc(mtd, chip);
1538 /*
1539 * See if operation failed and additional status checks are
1540 * available
1541 */
1542 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1543 status = chip->errstat(mtd, chip, FL_WRITING, status,
1544 page);
1545
1546 if (status & NAND_STATUS_FAIL)
1547 return -EIO;
1548 } else {
1549 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1550 status = chip->waitfunc(mtd, chip);
1551 }
1552
1553 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1554 /* Send command to read back the data */
1555 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1556
1557 if (chip->verify_buf(mtd, buf, mtd->writesize))
1558 return -EIO;
1559 #endif
1560 return 0;
1561 }
1562
1563 /**
1564 * nand_fill_oob - [Internal] Transfer client buffer to oob
1565 * @chip: nand chip structure
1566 * @oob: oob data buffer
1567 * @ops: oob ops structure
1568 */
1569 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1570 struct mtd_oob_ops *ops)
1571 {
1572 size_t len = ops->ooblen;
1573
1574 switch(ops->mode) {
1575
1576 case MTD_OOB_PLACE:
1577 case MTD_OOB_RAW:
1578 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1579 return oob + len;
1580
1581 case MTD_OOB_AUTO: {
1582 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1583 uint32_t boffs = 0, woffs = ops->ooboffs;
1584 size_t bytes = 0;
1585
1586 for(; free->length && len; free++, len -= bytes) {
1587 /* Write request not from offset 0 ? */
1588 if (unlikely(woffs)) {
1589 if (woffs >= free->length) {
1590 woffs -= free->length;
1591 continue;
1592 }
1593 boffs = free->offset + woffs;
1594 bytes = min_t(size_t, len,
1595 (free->length - woffs));
1596 woffs = 0;
1597 } else {
1598 bytes = min_t(size_t, len, free->length);
1599 boffs = free->offset;
1600 }
1601 memcpy(chip->oob_poi + boffs, oob, bytes);
1602 oob += bytes;
1603 }
1604 return oob;
1605 }
1606 default:
1607 BUG();
1608 }
1609 return NULL;
1610 }
1611
1612 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1613
1614 /**
1615 * nand_do_write_ops - [Internal] NAND write with ECC
1616 * @mtd: MTD device structure
1617 * @to: offset to write to
1618 * @ops: oob operations description structure
1619 *
1620 * NAND write with ECC
1621 */
1622 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1623 struct mtd_oob_ops *ops)
1624 {
1625 int chipnr, realpage, page, blockmask, column;
1626 struct nand_chip *chip = mtd->priv;
1627 uint32_t writelen = ops->len;
1628 uint8_t *oob = ops->oobbuf;
1629 uint8_t *buf = ops->datbuf;
1630 int ret, subpage;
1631
1632 ops->retlen = 0;
1633 if (!writelen)
1634 return 0;
1635
1636 /* reject writes, which are not page aligned */
1637 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1638 printk(KERN_NOTICE "nand_write: "
1639 "Attempt to write not page aligned data\n");
1640 return -EINVAL;
1641 }
1642
1643 column = to & (mtd->writesize - 1);
1644 subpage = column || (writelen & (mtd->writesize - 1));
1645
1646 if (subpage && oob)
1647 return -EINVAL;
1648
1649 chipnr = (int)(to >> chip->chip_shift);
1650 chip->select_chip(mtd, chipnr);
1651
1652 /* Check, if it is write protected */
1653 if (nand_check_wp(mtd))
1654 return -EIO;
1655
1656 realpage = (int)(to >> chip->page_shift);
1657 page = realpage & chip->pagemask;
1658 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1659
1660 /* Invalidate the page cache, when we write to the cached page */
1661 if (to <= (chip->pagebuf << chip->page_shift) &&
1662 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1663 chip->pagebuf = -1;
1664
1665 /* If we're not given explicit OOB data, let it be 0xFF */
1666 if (likely(!oob))
1667 memset(chip->oob_poi, 0xff, mtd->oobsize);
1668
1669 while(1) {
1670 int bytes = mtd->writesize;
1671 int cached = writelen > bytes && page != blockmask;
1672 uint8_t *wbuf = buf;
1673
1674 /* Partial page write ? */
1675 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1676 cached = 0;
1677 bytes = min_t(int, bytes - column, (int) writelen);
1678 chip->pagebuf = -1;
1679 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1680 memcpy(&chip->buffers->databuf[column], buf, bytes);
1681 wbuf = chip->buffers->databuf;
1682 }
1683
1684 if (unlikely(oob))
1685 oob = nand_fill_oob(chip, oob, ops);
1686
1687 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1688 (ops->mode == MTD_OOB_RAW));
1689 if (ret)
1690 break;
1691
1692 writelen -= bytes;
1693 if (!writelen)
1694 break;
1695
1696 column = 0;
1697 buf += bytes;
1698 realpage++;
1699
1700 page = realpage & chip->pagemask;
1701 /* Check, if we cross a chip boundary */
1702 if (!page) {
1703 chipnr++;
1704 chip->select_chip(mtd, -1);
1705 chip->select_chip(mtd, chipnr);
1706 }
1707 }
1708
1709 ops->retlen = ops->len - writelen;
1710 if (unlikely(oob))
1711 ops->oobretlen = ops->ooblen;
1712 return ret;
1713 }
1714
1715 /**
1716 * nand_write - [MTD Interface] NAND write with ECC
1717 * @mtd: MTD device structure
1718 * @to: offset to write to
1719 * @len: number of bytes to write
1720 * @retlen: pointer to variable to store the number of written bytes
1721 * @buf: the data to write
1722 *
1723 * NAND write with ECC
1724 */
1725 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1726 size_t *retlen, const uint8_t *buf)
1727 {
1728 struct nand_chip *chip = mtd->priv;
1729 int ret;
1730
1731 /* Do not allow reads past end of device */
1732 if ((to + len) > mtd->size)
1733 return -EINVAL;
1734 if (!len)
1735 return 0;
1736
1737 nand_get_device(chip, mtd, FL_WRITING);
1738
1739 chip->ops.len = len;
1740 chip->ops.datbuf = (uint8_t *)buf;
1741 chip->ops.oobbuf = NULL;
1742
1743 ret = nand_do_write_ops(mtd, to, &chip->ops);
1744
1745 *retlen = chip->ops.retlen;
1746
1747 nand_release_device(mtd);
1748
1749 return ret;
1750 }
1751
1752 /**
1753 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1754 * @mtd: MTD device structure
1755 * @to: offset to write to
1756 * @ops: oob operation description structure
1757 *
1758 * NAND write out-of-band
1759 */
1760 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1761 struct mtd_oob_ops *ops)
1762 {
1763 int chipnr, page, status, len;
1764 struct nand_chip *chip = mtd->priv;
1765
1766 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1767 (unsigned int)to, (int)ops->ooblen);
1768
1769 if (ops->mode == MTD_OOB_AUTO)
1770 len = chip->ecc.layout->oobavail;
1771 else
1772 len = mtd->oobsize;
1773
1774 /* Do not allow write past end of page */
1775 if ((ops->ooboffs + ops->ooblen) > len) {
1776 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1777 "Attempt to write past end of page\n");
1778 return -EINVAL;
1779 }
1780
1781 if (unlikely(ops->ooboffs >= len)) {
1782 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1783 "Attempt to start write outside oob\n");
1784 return -EINVAL;
1785 }
1786
1787 /* Do not allow reads past end of device */
1788 if (unlikely(to >= mtd->size ||
1789 ops->ooboffs + ops->ooblen >
1790 ((mtd->size >> chip->page_shift) -
1791 (to >> chip->page_shift)) * len)) {
1792 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1793 "Attempt write beyond end of device\n");
1794 return -EINVAL;
1795 }
1796
1797 chipnr = (int)(to >> chip->chip_shift);
1798 chip->select_chip(mtd, chipnr);
1799
1800 /* Shift to get page */
1801 page = (int)(to >> chip->page_shift);
1802
1803 /*
1804 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1805 * of my DiskOnChip 2000 test units) will clear the whole data page too
1806 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1807 * it in the doc2000 driver in August 1999. dwmw2.
1808 */
1809 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1810
1811 /* Check, if it is write protected */
1812 if (nand_check_wp(mtd))
1813 return -EROFS;
1814
1815 /* Invalidate the page cache, if we write to the cached page */
1816 if (page == chip->pagebuf)
1817 chip->pagebuf = -1;
1818
1819 memset(chip->oob_poi, 0xff, mtd->oobsize);
1820 nand_fill_oob(chip, ops->oobbuf, ops);
1821 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1822 memset(chip->oob_poi, 0xff, mtd->oobsize);
1823
1824 if (status)
1825 return status;
1826
1827 ops->oobretlen = ops->ooblen;
1828
1829 return 0;
1830 }
1831
1832 /**
1833 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1834 * @mtd: MTD device structure
1835 * @to: offset to write to
1836 * @ops: oob operation description structure
1837 */
1838 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1839 struct mtd_oob_ops *ops)
1840 {
1841 struct nand_chip *chip = mtd->priv;
1842 int ret = -ENOTSUPP;
1843
1844 ops->retlen = 0;
1845
1846 /* Do not allow writes past end of device */
1847 if (ops->datbuf && (to + ops->len) > mtd->size) {
1848 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1849 "Attempt read beyond end of device\n");
1850 return -EINVAL;
1851 }
1852
1853 nand_get_device(chip, mtd, FL_WRITING);
1854
1855 switch(ops->mode) {
1856 case MTD_OOB_PLACE:
1857 case MTD_OOB_AUTO:
1858 case MTD_OOB_RAW:
1859 break;
1860
1861 default:
1862 goto out;
1863 }
1864
1865 if (!ops->datbuf)
1866 ret = nand_do_write_oob(mtd, to, ops);
1867 else
1868 ret = nand_do_write_ops(mtd, to, ops);
1869
1870 out:
1871 nand_release_device(mtd);
1872 return ret;
1873 }
1874
1875 /**
1876 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1877 * @mtd: MTD device structure
1878 * @page: the page address of the block which will be erased
1879 *
1880 * Standard erase command for NAND chips
1881 */
1882 static void single_erase_cmd(struct mtd_info *mtd, int page)
1883 {
1884 struct nand_chip *chip = mtd->priv;
1885 /* Send commands to erase a block */
1886 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1887 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1888 }
1889
1890 /**
1891 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1892 * @mtd: MTD device structure
1893 * @page: the page address of the block which will be erased
1894 *
1895 * AND multi block erase command function
1896 * Erase 4 consecutive blocks
1897 */
1898 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1899 {
1900 struct nand_chip *chip = mtd->priv;
1901 /* Send commands to erase a block */
1902 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1903 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1904 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1905 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1906 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1907 }
1908
1909 /**
1910 * nand_erase - [MTD Interface] erase block(s)
1911 * @mtd: MTD device structure
1912 * @instr: erase instruction
1913 *
1914 * Erase one ore more blocks
1915 */
1916 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1917 {
1918 return nand_erase_nand(mtd, instr, 0);
1919 }
1920
1921 #define BBT_PAGE_MASK 0xffffff3f
1922 /**
1923 * nand_erase_nand - [Internal] erase block(s)
1924 * @mtd: MTD device structure
1925 * @instr: erase instruction
1926 * @allowbbt: allow erasing the bbt area
1927 *
1928 * Erase one ore more blocks
1929 */
1930 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1931 int allowbbt)
1932 {
1933 int page, len, status, pages_per_block, ret, chipnr;
1934 struct nand_chip *chip = mtd->priv;
1935 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1936 unsigned int bbt_masked_page = 0xffffffff;
1937
1938 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1939 (unsigned int)instr->addr, (unsigned int)instr->len);
1940
1941 /* Start address must align on block boundary */
1942 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1943 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1944 return -EINVAL;
1945 }
1946
1947 /* Length must align on block boundary */
1948 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1949 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1950 "Length not block aligned\n");
1951 return -EINVAL;
1952 }
1953
1954 /* Do not allow erase past end of device */
1955 if ((instr->len + instr->addr) > mtd->size) {
1956 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1957 "Erase past end of device\n");
1958 return -EINVAL;
1959 }
1960
1961 instr->fail_addr = 0xffffffff;
1962
1963 /* Grab the lock and see if the device is available */
1964 nand_get_device(chip, mtd, FL_ERASING);
1965
1966 /* Shift to get first page */
1967 page = (int)(instr->addr >> chip->page_shift);
1968 chipnr = (int)(instr->addr >> chip->chip_shift);
1969
1970 /* Calculate pages in each block */
1971 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1972
1973 /* Select the NAND device */
1974 chip->select_chip(mtd, chipnr);
1975
1976 /* Check, if it is write protected */
1977 if (nand_check_wp(mtd)) {
1978 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1979 "Device is write protected!!!\n");
1980 instr->state = MTD_ERASE_FAILED;
1981 goto erase_exit;
1982 }
1983
1984 /*
1985 * If BBT requires refresh, set the BBT page mask to see if the BBT
1986 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1987 * can not be matched. This is also done when the bbt is actually
1988 * erased to avoid recusrsive updates
1989 */
1990 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1991 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1992
1993 /* Loop through the pages */
1994 len = instr->len;
1995
1996 instr->state = MTD_ERASING;
1997
1998 while (len) {
1999 /*
2000 * heck if we have a bad block, we do not erase bad blocks !
2001 */
2002 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2003 chip->page_shift, 0, allowbbt)) {
2004 printk(KERN_WARNING "nand_erase: attempt to erase a "
2005 "bad block at page 0x%08x\n", page);
2006 instr->state = MTD_ERASE_FAILED;
2007 goto erase_exit;
2008 }
2009
2010 /*
2011 * Invalidate the page cache, if we erase the block which
2012 * contains the current cached page
2013 */
2014 if (page <= chip->pagebuf && chip->pagebuf <
2015 (page + pages_per_block))
2016 chip->pagebuf = -1;
2017
2018 chip->erase_cmd(mtd, page & chip->pagemask);
2019
2020 status = chip->waitfunc(mtd, chip);
2021
2022 /*
2023 * See if operation failed and additional status checks are
2024 * available
2025 */
2026 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2027 status = chip->errstat(mtd, chip, FL_ERASING,
2028 status, page);
2029
2030 /* See if block erase succeeded */
2031 if (status & NAND_STATUS_FAIL) {
2032 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
2033 "Failed erase, page 0x%08x\n", page);
2034 instr->state = MTD_ERASE_FAILED;
2035 instr->fail_addr = (page << chip->page_shift);
2036 goto erase_exit;
2037 }
2038
2039 /*
2040 * If BBT requires refresh, set the BBT rewrite flag to the
2041 * page being erased
2042 */
2043 if (bbt_masked_page != 0xffffffff &&
2044 (page & BBT_PAGE_MASK) == bbt_masked_page)
2045 rewrite_bbt[chipnr] = (page << chip->page_shift);
2046
2047 /* Increment page address and decrement length */
2048 len -= (1 << chip->phys_erase_shift);
2049 page += pages_per_block;
2050
2051 /* Check, if we cross a chip boundary */
2052 if (len && !(page & chip->pagemask)) {
2053 chipnr++;
2054 chip->select_chip(mtd, -1);
2055 chip->select_chip(mtd, chipnr);
2056
2057 /*
2058 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2059 * page mask to see if this BBT should be rewritten
2060 */
2061 if (bbt_masked_page != 0xffffffff &&
2062 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2063 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2064 BBT_PAGE_MASK;
2065 }
2066 }
2067 instr->state = MTD_ERASE_DONE;
2068
2069 erase_exit:
2070
2071 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2072
2073 /* Deselect and wake up anyone waiting on the device */
2074 nand_release_device(mtd);
2075
2076 /* Do call back function */
2077 if (!ret)
2078 mtd_erase_callback(instr);
2079
2080 /*
2081 * If BBT requires refresh and erase was successful, rewrite any
2082 * selected bad block tables
2083 */
2084 if (bbt_masked_page == 0xffffffff || ret)
2085 return ret;
2086
2087 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2088 if (!rewrite_bbt[chipnr])
2089 continue;
2090 /* update the BBT for chip */
2091 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2092 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2093 chip->bbt_td->pages[chipnr]);
2094 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2095 }
2096
2097 /* Return more or less happy */
2098 return ret;
2099 }
2100
2101 /**
2102 * nand_sync - [MTD Interface] sync
2103 * @mtd: MTD device structure
2104 *
2105 * Sync is actually a wait for chip ready function
2106 */
2107 static void nand_sync(struct mtd_info *mtd)
2108 {
2109 struct nand_chip *chip = mtd->priv;
2110
2111 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2112
2113 /* Grab the lock and see if the device is available */
2114 nand_get_device(chip, mtd, FL_SYNCING);
2115 /* Release it and go back */
2116 nand_release_device(mtd);
2117 }
2118
2119 /**
2120 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2121 * @mtd: MTD device structure
2122 * @offs: offset relative to mtd start
2123 */
2124 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2125 {
2126 /* Check for invalid offset */
2127 if (offs > mtd->size)
2128 return -EINVAL;
2129
2130 return nand_block_checkbad(mtd, offs, 1, 0);
2131 }
2132
2133 /**
2134 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2135 * @mtd: MTD device structure
2136 * @ofs: offset relative to mtd start
2137 */
2138 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2139 {
2140 struct nand_chip *chip = mtd->priv;
2141 int ret;
2142
2143 if ((ret = nand_block_isbad(mtd, ofs))) {
2144 /* If it was bad already, return success and do nothing. */
2145 if (ret > 0)
2146 return 0;
2147 return ret;
2148 }
2149
2150 return chip->block_markbad(mtd, ofs);
2151 }
2152
2153 /**
2154 * nand_suspend - [MTD Interface] Suspend the NAND flash
2155 * @mtd: MTD device structure
2156 */
2157 static int nand_suspend(struct mtd_info *mtd)
2158 {
2159 struct nand_chip *chip = mtd->priv;
2160
2161 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2162 }
2163
2164 /**
2165 * nand_resume - [MTD Interface] Resume the NAND flash
2166 * @mtd: MTD device structure
2167 */
2168 static void nand_resume(struct mtd_info *mtd)
2169 {
2170 struct nand_chip *chip = mtd->priv;
2171
2172 if (chip->state == FL_PM_SUSPENDED)
2173 nand_release_device(mtd);
2174 else
2175 printk(KERN_ERR "nand_resume() called for a chip which is not "
2176 "in suspended state\n");
2177 }
2178
2179 /*
2180 * Set default functions
2181 */
2182 static void nand_set_defaults(struct nand_chip *chip, int busw)
2183 {
2184 /* check for proper chip_delay setup, set 20us if not */
2185 if (!chip->chip_delay)
2186 chip->chip_delay = 20;
2187
2188 /* check, if a user supplied command function given */
2189 if (chip->cmdfunc == NULL)
2190 chip->cmdfunc = nand_command;
2191
2192 /* check, if a user supplied wait function given */
2193 if (chip->waitfunc == NULL)
2194 chip->waitfunc = nand_wait;
2195
2196 if (!chip->select_chip)
2197 chip->select_chip = nand_select_chip;
2198 if (!chip->read_byte)
2199 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2200 if (!chip->read_word)
2201 chip->read_word = nand_read_word;
2202 if (!chip->block_bad)
2203 chip->block_bad = nand_block_bad;
2204 if (!chip->block_markbad)
2205 chip->block_markbad = nand_default_block_markbad;
2206 if (!chip->write_buf)
2207 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2208 if (!chip->read_buf)
2209 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2210 if (!chip->verify_buf)
2211 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2212 if (!chip->scan_bbt)
2213 chip->scan_bbt = nand_default_bbt;
2214
2215 if (!chip->controller) {
2216 chip->controller = &chip->hwcontrol;
2217 spin_lock_init(&chip->controller->lock);
2218 init_waitqueue_head(&chip->controller->wq);
2219 }
2220
2221 }
2222
2223 /*
2224 * Get the flash and manufacturer id and lookup if the type is supported
2225 */
2226 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2227 struct nand_chip *chip,
2228 int busw, int *maf_id)
2229 {
2230 struct nand_flash_dev *type = NULL;
2231 int i, dev_id, maf_idx;
2232
2233 /* Select the device */
2234 chip->select_chip(mtd, 0);
2235
2236 /* Send the command for reading device ID */
2237 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2238
2239 /* Read manufacturer and device IDs */
2240 *maf_id = chip->read_byte(mtd);
2241 dev_id = chip->read_byte(mtd);
2242
2243 /* Lookup the flash id */
2244 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2245 if (dev_id == nand_flash_ids[i].id) {
2246 type = &nand_flash_ids[i];
2247 break;
2248 }
2249 }
2250
2251 if (!type)
2252 return ERR_PTR(-ENODEV);
2253
2254 if (!mtd->name)
2255 mtd->name = type->name;
2256
2257 chip->chipsize = type->chipsize << 20;
2258
2259 /* Newer devices have all the information in additional id bytes */
2260 if (!type->pagesize) {
2261 int extid;
2262 /* The 3rd id byte holds MLC / multichip data */
2263 chip->cellinfo = chip->read_byte(mtd);
2264 /* The 4th id byte is the important one */
2265 extid = chip->read_byte(mtd);
2266 /* Calc pagesize */
2267 mtd->writesize = 1024 << (extid & 0x3);
2268 extid >>= 2;
2269 /* Calc oobsize */
2270 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2271 extid >>= 2;
2272 /* Calc blocksize. Blocksize is multiples of 64KiB */
2273 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2274 extid >>= 2;
2275 /* Get buswidth information */
2276 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2277
2278 } else {
2279 /*
2280 * Old devices have chip data hardcoded in the device id table
2281 */
2282 mtd->erasesize = type->erasesize;
2283 mtd->writesize = type->pagesize;
2284 mtd->oobsize = mtd->writesize / 32;
2285 busw = type->options & NAND_BUSWIDTH_16;
2286 }
2287
2288 /* Try to identify manufacturer */
2289 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2290 if (nand_manuf_ids[maf_idx].id == *maf_id)
2291 break;
2292 }
2293
2294 /*
2295 * Check, if buswidth is correct. Hardware drivers should set
2296 * chip correct !
2297 */
2298 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2299 printk(KERN_INFO "NAND device: Manufacturer ID:"
2300 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2301 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2302 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2303 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2304 busw ? 16 : 8);
2305 return ERR_PTR(-EINVAL);
2306 }
2307
2308 /* Calculate the address shift from the page size */
2309 chip->page_shift = ffs(mtd->writesize) - 1;
2310 /* Convert chipsize to number of pages per chip -1. */
2311 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2312
2313 chip->bbt_erase_shift = chip->phys_erase_shift =
2314 ffs(mtd->erasesize) - 1;
2315 chip->chip_shift = ffs(chip->chipsize) - 1;
2316
2317 /* Set the bad block position */
2318 chip->badblockpos = mtd->writesize > 512 ?
2319 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2320
2321 /* Get chip options, preserve non chip based options */
2322 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2323 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2324
2325 /*
2326 * Set chip as a default. Board drivers can override it, if necessary
2327 */
2328 chip->options |= NAND_NO_AUTOINCR;
2329
2330 /* Check if chip is a not a samsung device. Do not clear the
2331 * options for chips which are not having an extended id.
2332 */
2333 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2334 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2335
2336 /* Check for AND chips with 4 page planes */
2337 if (chip->options & NAND_4PAGE_ARRAY)
2338 chip->erase_cmd = multi_erase_cmd;
2339 else
2340 chip->erase_cmd = single_erase_cmd;
2341
2342 /* Do not replace user supplied command function ! */
2343 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2344 chip->cmdfunc = nand_command_lp;
2345
2346 printk(KERN_INFO "NAND device: Manufacturer ID:"
2347 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2348 nand_manuf_ids[maf_idx].name, type->name);
2349
2350 return type;
2351 }
2352
2353 /**
2354 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2355 * @mtd: MTD device structure
2356 * @maxchips: Number of chips to scan for
2357 *
2358 * This is the first phase of the normal nand_scan() function. It
2359 * reads the flash ID and sets up MTD fields accordingly.
2360 *
2361 * The mtd->owner field must be set to the module of the caller.
2362 */
2363 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2364 {
2365 int i, busw, nand_maf_id;
2366 struct nand_chip *chip = mtd->priv;
2367 struct nand_flash_dev *type;
2368
2369 /* Get buswidth to select the correct functions */
2370 busw = chip->options & NAND_BUSWIDTH_16;
2371 /* Set the default functions */
2372 nand_set_defaults(chip, busw);
2373
2374 /* Read the flash type */
2375 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2376
2377 if (IS_ERR(type)) {
2378 printk(KERN_WARNING "No NAND device found!!!\n");
2379 chip->select_chip(mtd, -1);
2380 return PTR_ERR(type);
2381 }
2382
2383 /* Check for a chip array */
2384 for (i = 1; i < maxchips; i++) {
2385 chip->select_chip(mtd, i);
2386 /* Send the command for reading device ID */
2387 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2388 /* Read manufacturer and device IDs */
2389 if (nand_maf_id != chip->read_byte(mtd) ||
2390 type->id != chip->read_byte(mtd))
2391 break;
2392 }
2393 if (i > 1)
2394 printk(KERN_INFO "%d NAND chips detected\n", i);
2395
2396 /* Store the number of chips and calc total size for mtd */
2397 chip->numchips = i;
2398 mtd->size = i * chip->chipsize;
2399
2400 return 0;
2401 }
2402
2403
2404 /**
2405 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2406 * @mtd: MTD device structure
2407 * @maxchips: Number of chips to scan for
2408 *
2409 * This is the second phase of the normal nand_scan() function. It
2410 * fills out all the uninitialized function pointers with the defaults
2411 * and scans for a bad block table if appropriate.
2412 */
2413 int nand_scan_tail(struct mtd_info *mtd)
2414 {
2415 int i;
2416 struct nand_chip *chip = mtd->priv;
2417
2418 if (!(chip->options & NAND_OWN_BUFFERS))
2419 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2420 if (!chip->buffers)
2421 return -ENOMEM;
2422
2423 /* Set the internal oob buffer location, just after the page data */
2424 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2425
2426 /*
2427 * If no default placement scheme is given, select an appropriate one
2428 */
2429 if (!chip->ecc.layout) {
2430 switch (mtd->oobsize) {
2431 case 8:
2432 chip->ecc.layout = &nand_oob_8;
2433 break;
2434 case 16:
2435 chip->ecc.layout = &nand_oob_16;
2436 break;
2437 case 64:
2438 chip->ecc.layout = &nand_oob_64;
2439 break;
2440 default:
2441 printk(KERN_WARNING "No oob scheme defined for "
2442 "oobsize %d\n", mtd->oobsize);
2443 BUG();
2444 }
2445 }
2446
2447 if (!chip->write_page)
2448 chip->write_page = nand_write_page;
2449
2450 /*
2451 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2452 * selected and we have 256 byte pagesize fallback to software ECC
2453 */
2454 if (!chip->ecc.read_page_raw)
2455 chip->ecc.read_page_raw = nand_read_page_raw;
2456 if (!chip->ecc.write_page_raw)
2457 chip->ecc.write_page_raw = nand_write_page_raw;
2458
2459 switch (chip->ecc.mode) {
2460 case NAND_ECC_HW:
2461 /* Use standard hwecc read page function ? */
2462 if (!chip->ecc.read_page)
2463 chip->ecc.read_page = nand_read_page_hwecc;
2464 if (!chip->ecc.write_page)
2465 chip->ecc.write_page = nand_write_page_hwecc;
2466 if (!chip->ecc.read_oob)
2467 chip->ecc.read_oob = nand_read_oob_std;
2468 if (!chip->ecc.write_oob)
2469 chip->ecc.write_oob = nand_write_oob_std;
2470
2471 case NAND_ECC_HW_SYNDROME:
2472 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2473 !chip->ecc.hwctl) &&
2474 (!chip->ecc.read_page ||
2475 chip->ecc.read_page == nand_read_page_hwecc ||
2476 !chip->ecc.write_page ||
2477 chip->ecc.write_page == nand_write_page_hwecc)) {
2478 printk(KERN_WARNING "No ECC functions supplied, "
2479 "Hardware ECC not possible\n");
2480 BUG();
2481 }
2482 /* Use standard syndrome read/write page function ? */
2483 if (!chip->ecc.read_page)
2484 chip->ecc.read_page = nand_read_page_syndrome;
2485 if (!chip->ecc.write_page)
2486 chip->ecc.write_page = nand_write_page_syndrome;
2487 if (!chip->ecc.read_oob)
2488 chip->ecc.read_oob = nand_read_oob_syndrome;
2489 if (!chip->ecc.write_oob)
2490 chip->ecc.write_oob = nand_write_oob_syndrome;
2491
2492 if (mtd->writesize >= chip->ecc.size)
2493 break;
2494 printk(KERN_WARNING "%d byte HW ECC not possible on "
2495 "%d byte page size, fallback to SW ECC\n",
2496 chip->ecc.size, mtd->writesize);
2497 chip->ecc.mode = NAND_ECC_SOFT;
2498
2499 case NAND_ECC_SOFT:
2500 chip->ecc.calculate = nand_calculate_ecc;
2501 chip->ecc.correct = nand_correct_data;
2502 chip->ecc.read_page = nand_read_page_swecc;
2503 chip->ecc.write_page = nand_write_page_swecc;
2504 chip->ecc.read_oob = nand_read_oob_std;
2505 chip->ecc.write_oob = nand_write_oob_std;
2506 chip->ecc.size = 256;
2507 chip->ecc.bytes = 3;
2508 break;
2509
2510 case NAND_ECC_NONE:
2511 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2512 "This is not recommended !!\n");
2513 chip->ecc.read_page = nand_read_page_raw;
2514 chip->ecc.write_page = nand_write_page_raw;
2515 chip->ecc.read_oob = nand_read_oob_std;
2516 chip->ecc.write_oob = nand_write_oob_std;
2517 chip->ecc.size = mtd->writesize;
2518 chip->ecc.bytes = 0;
2519 break;
2520
2521 default:
2522 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2523 chip->ecc.mode);
2524 BUG();
2525 }
2526
2527 /*
2528 * The number of bytes available for a client to place data into
2529 * the out of band area
2530 */
2531 chip->ecc.layout->oobavail = 0;
2532 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2533 chip->ecc.layout->oobavail +=
2534 chip->ecc.layout->oobfree[i].length;
2535 mtd->oobavail = chip->ecc.layout->oobavail;
2536
2537 /*
2538 * Set the number of read / write steps for one page depending on ECC
2539 * mode
2540 */
2541 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2542 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2543 printk(KERN_WARNING "Invalid ecc parameters\n");
2544 BUG();
2545 }
2546 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2547
2548 /*
2549 * Allow subpage writes up to ecc.steps. Not possible for MLC
2550 * FLASH.
2551 */
2552 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2553 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2554 switch(chip->ecc.steps) {
2555 case 2:
2556 mtd->subpage_sft = 1;
2557 break;
2558 case 4:
2559 case 8:
2560 mtd->subpage_sft = 2;
2561 break;
2562 }
2563 }
2564 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2565
2566 /* Initialize state */
2567 chip->state = FL_READY;
2568
2569 /* De-select the device */
2570 chip->select_chip(mtd, -1);
2571
2572 /* Invalidate the pagebuffer reference */
2573 chip->pagebuf = -1;
2574
2575 /* Fill in remaining MTD driver data */
2576 mtd->type = MTD_NANDFLASH;
2577 mtd->flags = MTD_CAP_NANDFLASH;
2578 mtd->erase = nand_erase;
2579 mtd->point = NULL;
2580 mtd->unpoint = NULL;
2581 mtd->read = nand_read;
2582 mtd->write = nand_write;
2583 mtd->read_oob = nand_read_oob;
2584 mtd->write_oob = nand_write_oob;
2585 mtd->sync = nand_sync;
2586 mtd->lock = NULL;
2587 mtd->unlock = NULL;
2588 mtd->suspend = nand_suspend;
2589 mtd->resume = nand_resume;
2590 mtd->block_isbad = nand_block_isbad;
2591 mtd->block_markbad = nand_block_markbad;
2592
2593 /* propagate ecc.layout to mtd_info */
2594 mtd->ecclayout = chip->ecc.layout;
2595
2596 /* Check, if we should skip the bad block table scan */
2597 if (chip->options & NAND_SKIP_BBTSCAN)
2598 return 0;
2599
2600 /* Build bad block table */
2601 return chip->scan_bbt(mtd);
2602 }
2603
2604 /* module_text_address() isn't exported, and it's mostly a pointless
2605 test if this is a module _anyway_ -- they'd have to try _really_ hard
2606 to call us from in-kernel code if the core NAND support is modular. */
2607 #ifdef MODULE
2608 #define caller_is_module() (1)
2609 #else
2610 #define caller_is_module() \
2611 module_text_address((unsigned long)__builtin_return_address(0))
2612 #endif
2613
2614 /**
2615 * nand_scan - [NAND Interface] Scan for the NAND device
2616 * @mtd: MTD device structure
2617 * @maxchips: Number of chips to scan for
2618 *
2619 * This fills out all the uninitialized function pointers
2620 * with the defaults.
2621 * The flash ID is read and the mtd/chip structures are
2622 * filled with the appropriate values.
2623 * The mtd->owner field must be set to the module of the caller
2624 *
2625 */
2626 int nand_scan(struct mtd_info *mtd, int maxchips)
2627 {
2628 int ret;
2629
2630 /* Many callers got this wrong, so check for it for a while... */
2631 if (!mtd->owner && caller_is_module()) {
2632 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2633 BUG();
2634 }
2635
2636 ret = nand_scan_ident(mtd, maxchips);
2637 if (!ret)
2638 ret = nand_scan_tail(mtd);
2639 return ret;
2640 }
2641
2642 /**
2643 * nand_release - [NAND Interface] Free resources held by the NAND device
2644 * @mtd: MTD device structure
2645 */
2646 void nand_release(struct mtd_info *mtd)
2647 {
2648 struct nand_chip *chip = mtd->priv;
2649
2650 #ifdef CONFIG_MTD_PARTITIONS
2651 /* Deregister partitions */
2652 del_mtd_partitions(mtd);
2653 #endif
2654 /* Deregister the device */
2655 del_mtd_device(mtd);
2656
2657 /* Free bad block table memory */
2658 kfree(chip->bbt);
2659 if (!(chip->options & NAND_OWN_BUFFERS))
2660 kfree(chip->buffers);
2661 }
2662
2663 EXPORT_SYMBOL_GPL(nand_scan);
2664 EXPORT_SYMBOL_GPL(nand_scan_ident);
2665 EXPORT_SYMBOL_GPL(nand_scan_tail);
2666 EXPORT_SYMBOL_GPL(nand_release);
2667
2668 static int __init nand_base_init(void)
2669 {
2670 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2671 return 0;
2672 }
2673
2674 static void __exit nand_base_exit(void)
2675 {
2676 led_trigger_unregister_simple(nand_led_trigger);
2677 }
2678
2679 module_init(nand_base_init);
2680 module_exit(nand_base_exit);
2681
2682 MODULE_LICENSE("GPL");
2683 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2684 MODULE_DESCRIPTION("Generic NAND flash driver code");
WRT350N Kernel Patches