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[PATCH] Remove hosthw.h from rio (unused file)
[wrt350n-kernel.git] / arch / mips / dec / setup.c
blob9ef54fe1feaaef707df1355bd7c253505538ffae
1 /*
2 * System-specific setup, especially interrupts.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Harald Koerfgen
9 * Copyright (C) 2000, 2001, 2002, 2003, 2005 Maciej W. Rozycki
10 */
11 #include <linux/console.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/ioport.h>
15 #include <linux/module.h>
16 #include <linux/param.h>
17 #include <linux/sched.h>
18 #include <linux/spinlock.h>
19 #include <linux/types.h>
20
21 #include <asm/bootinfo.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/irq.h>
25 #include <asm/irq_cpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/reboot.h>
28 #include <asm/time.h>
29 #include <asm/traps.h>
30 #include <asm/wbflush.h>
31
32 #include <asm/dec/interrupts.h>
33 #include <asm/dec/ioasic.h>
34 #include <asm/dec/ioasic_addrs.h>
35 #include <asm/dec/ioasic_ints.h>
36 #include <asm/dec/kn01.h>
37 #include <asm/dec/kn02.h>
38 #include <asm/dec/kn02ba.h>
39 #include <asm/dec/kn02ca.h>
40 #include <asm/dec/kn03.h>
41 #include <asm/dec/kn230.h>
42 #include <asm/dec/system.h>
43
44
45 extern void dec_machine_restart(char *command);
46 extern void dec_machine_halt(void);
47 extern void dec_machine_power_off(void);
48 extern irqreturn_t dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
49
50 extern asmlinkage void decstation_handle_int(void);
51
52 unsigned long dec_kn_slot_base, dec_kn_slot_size;
53
54 EXPORT_SYMBOL(dec_kn_slot_base);
55 EXPORT_SYMBOL(dec_kn_slot_size);
56
57 spinlock_t ioasic_ssr_lock;
58
59 volatile u32 *ioasic_base;
60
61 EXPORT_SYMBOL(ioasic_base);
62
63 /*
64 * IRQ routing and priority tables. Priorites are set as follows:
65 *
66 * KN01 KN230 KN02 KN02-BA KN02-CA KN03
67 *
68 * MEMORY CPU CPU CPU ASIC CPU CPU
69 * RTC CPU CPU CPU ASIC CPU CPU
70 * DMA - - - ASIC ASIC ASIC
71 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
72 * SERIAL1 - - - ASIC - ASIC
73 * SCSI CPU CPU CSR ASIC ASIC ASIC
74 * ETHERNET CPU * CSR ASIC ASIC ASIC
75 * other - - - ASIC - -
76 * TC2 - - CSR CPU ASIC ASIC
77 * TC1 - - CSR CPU ASIC ASIC
78 * TC0 - - CSR CPU ASIC ASIC
79 * other - CPU - CPU ASIC ASIC
80 * other - - - - CPU CPU
81 *
82 * * -- shared with SCSI
83 */
84
85 int dec_interrupt[DEC_NR_INTS] = {
86 [0 ... DEC_NR_INTS - 1] = -1
87 };
88
89 EXPORT_SYMBOL(dec_interrupt);
90
91 int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2] = {
92 { { .i = ~0 }, { .p = dec_intr_unimplemented } },
93 };
94 int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2] = {
95 { { .i = ~0 }, { .p = asic_intr_unimplemented } },
96 };
97 int cpu_fpu_mask = DEC_CPU_IRQ_MASK(DEC_CPU_INR_FPU);
98
99 static struct irqaction ioirq = {
100 .handler = no_action,
101 .name = "cascade",
102 };
103 static struct irqaction fpuirq = {
104 .handler = no_action,
105 .name = "fpu",
106 };
107
108 static struct irqaction busirq = {
109 .flags = SA_INTERRUPT,
110 .name = "bus error",
111 };
112
113 static struct irqaction haltirq = {
114 .handler = dec_intr_halt,
115 .name = "halt",
116 };
117
118
119 /*
120 * Bus error (DBE/IBE exceptions and bus interrupts) handling setup.
121 */
122 static void __init dec_be_init(void)
123 {
124 switch (mips_machtype) {
125 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
126 board_be_handler = dec_kn01_be_handler;
127 busirq.handler = dec_kn01_be_interrupt;
128 busirq.flags |= SA_SHIRQ;
129 dec_kn01_be_init();
130 break;
131 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
132 case MACH_DS5000_XX: /* DS5000/xx Maxine */
133 board_be_handler = dec_kn02xa_be_handler;
134 busirq.handler = dec_kn02xa_be_interrupt;
135 dec_kn02xa_be_init();
136 break;
137 case MACH_DS5000_200: /* DS5000/200 3max */
138 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
139 case MACH_DS5900: /* DS5900 bigmax */
140 board_be_handler = dec_ecc_be_handler;
141 busirq.handler = dec_ecc_be_interrupt;
142 dec_ecc_be_init();
143 break;
144 }
145 }
146
147
148 extern void dec_time_init(void);
149 extern void dec_timer_setup(struct irqaction *);
150
151 void __init plat_setup(void)
152 {
153 board_be_init = dec_be_init;
154 board_time_init = dec_time_init;
155 board_timer_setup = dec_timer_setup;
156
157 wbflush_setup();
158
159 _machine_restart = dec_machine_restart;
160 _machine_halt = dec_machine_halt;
161 _machine_power_off = dec_machine_power_off;
162
163 ioport_resource.start = ~0UL;
164 ioport_resource.end = 0UL;
165 }
166
167 /*
168 * Machine-specific initialisation for KN01, aka DS2100 (aka Pmin)
169 * or DS3100 (aka Pmax).
170 */
171 static int kn01_interrupt[DEC_NR_INTS] __initdata = {
172 [DEC_IRQ_CASCADE] = -1,
173 [DEC_IRQ_AB_RECV] = -1,
174 [DEC_IRQ_AB_XMIT] = -1,
175 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11),
176 [DEC_IRQ_ASC] = -1,
177 [DEC_IRQ_FLOPPY] = -1,
178 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
179 [DEC_IRQ_HALT] = -1,
180 [DEC_IRQ_ISDN] = -1,
181 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE),
182 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS),
183 [DEC_IRQ_PSU] = -1,
184 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC),
185 [DEC_IRQ_SCC0] = -1,
186 [DEC_IRQ_SCC1] = -1,
187 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII),
188 [DEC_IRQ_TC0] = -1,
189 [DEC_IRQ_TC1] = -1,
190 [DEC_IRQ_TC2] = -1,
191 [DEC_IRQ_TIMER] = -1,
192 [DEC_IRQ_VIDEO] = DEC_CPU_IRQ_NR(KN01_CPU_INR_VIDEO),
193 [DEC_IRQ_ASC_MERR] = -1,
194 [DEC_IRQ_ASC_ERR] = -1,
195 [DEC_IRQ_ASC_DMA] = -1,
196 [DEC_IRQ_FLOPPY_ERR] = -1,
197 [DEC_IRQ_ISDN_ERR] = -1,
198 [DEC_IRQ_ISDN_RXDMA] = -1,
199 [DEC_IRQ_ISDN_TXDMA] = -1,
200 [DEC_IRQ_LANCE_MERR] = -1,
201 [DEC_IRQ_SCC0A_RXERR] = -1,
202 [DEC_IRQ_SCC0A_RXDMA] = -1,
203 [DEC_IRQ_SCC0A_TXERR] = -1,
204 [DEC_IRQ_SCC0A_TXDMA] = -1,
205 [DEC_IRQ_AB_RXERR] = -1,
206 [DEC_IRQ_AB_RXDMA] = -1,
207 [DEC_IRQ_AB_TXERR] = -1,
208 [DEC_IRQ_AB_TXDMA] = -1,
209 [DEC_IRQ_SCC1A_RXERR] = -1,
210 [DEC_IRQ_SCC1A_RXDMA] = -1,
211 [DEC_IRQ_SCC1A_TXERR] = -1,
212 [DEC_IRQ_SCC1A_TXDMA] = -1,
213 };
214
215 static int_ptr kn01_cpu_mask_nr_tbl[][2] __initdata = {
216 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_BUS) },
217 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_BUS) } },
218 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_RTC) },
219 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_RTC) } },
220 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_DZ11) },
221 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_DZ11) } },
222 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_SII) },
223 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_SII) } },
224 { { .i = DEC_CPU_IRQ_MASK(KN01_CPU_INR_LANCE) },
225 { .i = DEC_CPU_IRQ_NR(KN01_CPU_INR_LANCE) } },
226 { { .i = DEC_CPU_IRQ_ALL },
227 { .p = cpu_all_int } },
228 };
229
230 static void __init dec_init_kn01(void)
231 {
232 /* IRQ routing. */
233 memcpy(&dec_interrupt, &kn01_interrupt,
234 sizeof(kn01_interrupt));
235
236 /* CPU IRQ priorities. */
237 memcpy(&cpu_mask_nr_tbl, &kn01_cpu_mask_nr_tbl,
238 sizeof(kn01_cpu_mask_nr_tbl));
239
240 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
241
242 } /* dec_init_kn01 */
243
244
245 /*
246 * Machine-specific initialisation for KN230, aka DS5100, aka MIPSmate.
247 */
248 static int kn230_interrupt[DEC_NR_INTS] __initdata = {
249 [DEC_IRQ_CASCADE] = -1,
250 [DEC_IRQ_AB_RECV] = -1,
251 [DEC_IRQ_AB_XMIT] = -1,
252 [DEC_IRQ_DZ11] = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11),
253 [DEC_IRQ_ASC] = -1,
254 [DEC_IRQ_FLOPPY] = -1,
255 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
256 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN230_CPU_INR_HALT),
257 [DEC_IRQ_ISDN] = -1,
258 [DEC_IRQ_LANCE] = DEC_CPU_IRQ_NR(KN230_CPU_INR_LANCE),
259 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS),
260 [DEC_IRQ_PSU] = -1,
261 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC),
262 [DEC_IRQ_SCC0] = -1,
263 [DEC_IRQ_SCC1] = -1,
264 [DEC_IRQ_SII] = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII),
265 [DEC_IRQ_TC0] = -1,
266 [DEC_IRQ_TC1] = -1,
267 [DEC_IRQ_TC2] = -1,
268 [DEC_IRQ_TIMER] = -1,
269 [DEC_IRQ_VIDEO] = -1,
270 [DEC_IRQ_ASC_MERR] = -1,
271 [DEC_IRQ_ASC_ERR] = -1,
272 [DEC_IRQ_ASC_DMA] = -1,
273 [DEC_IRQ_FLOPPY_ERR] = -1,
274 [DEC_IRQ_ISDN_ERR] = -1,
275 [DEC_IRQ_ISDN_RXDMA] = -1,
276 [DEC_IRQ_ISDN_TXDMA] = -1,
277 [DEC_IRQ_LANCE_MERR] = -1,
278 [DEC_IRQ_SCC0A_RXERR] = -1,
279 [DEC_IRQ_SCC0A_RXDMA] = -1,
280 [DEC_IRQ_SCC0A_TXERR] = -1,
281 [DEC_IRQ_SCC0A_TXDMA] = -1,
282 [DEC_IRQ_AB_RXERR] = -1,
283 [DEC_IRQ_AB_RXDMA] = -1,
284 [DEC_IRQ_AB_TXERR] = -1,
285 [DEC_IRQ_AB_TXDMA] = -1,
286 [DEC_IRQ_SCC1A_RXERR] = -1,
287 [DEC_IRQ_SCC1A_RXDMA] = -1,
288 [DEC_IRQ_SCC1A_TXERR] = -1,
289 [DEC_IRQ_SCC1A_TXDMA] = -1,
290 };
291
292 static int_ptr kn230_cpu_mask_nr_tbl[][2] __initdata = {
293 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_BUS) },
294 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_BUS) } },
295 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_RTC) },
296 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_RTC) } },
297 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_DZ11) },
298 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_DZ11) } },
299 { { .i = DEC_CPU_IRQ_MASK(KN230_CPU_INR_SII) },
300 { .i = DEC_CPU_IRQ_NR(KN230_CPU_INR_SII) } },
301 { { .i = DEC_CPU_IRQ_ALL },
302 { .p = cpu_all_int } },
303 };
304
305 static void __init dec_init_kn230(void)
306 {
307 /* IRQ routing. */
308 memcpy(&dec_interrupt, &kn230_interrupt,
309 sizeof(kn230_interrupt));
310
311 /* CPU IRQ priorities. */
312 memcpy(&cpu_mask_nr_tbl, &kn230_cpu_mask_nr_tbl,
313 sizeof(kn230_cpu_mask_nr_tbl));
314
315 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
316
317 } /* dec_init_kn230 */
318
319
320 /*
321 * Machine-specific initialisation for KN02, aka DS5000/200, aka 3max.
322 */
323 static int kn02_interrupt[DEC_NR_INTS] __initdata = {
324 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02_CPU_INR_CASCADE),
325 [DEC_IRQ_AB_RECV] = -1,
326 [DEC_IRQ_AB_XMIT] = -1,
327 [DEC_IRQ_DZ11] = KN02_IRQ_NR(KN02_CSR_INR_DZ11),
328 [DEC_IRQ_ASC] = KN02_IRQ_NR(KN02_CSR_INR_ASC),
329 [DEC_IRQ_FLOPPY] = -1,
330 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
331 [DEC_IRQ_HALT] = -1,
332 [DEC_IRQ_ISDN] = -1,
333 [DEC_IRQ_LANCE] = KN02_IRQ_NR(KN02_CSR_INR_LANCE),
334 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS),
335 [DEC_IRQ_PSU] = -1,
336 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC),
337 [DEC_IRQ_SCC0] = -1,
338 [DEC_IRQ_SCC1] = -1,
339 [DEC_IRQ_SII] = -1,
340 [DEC_IRQ_TC0] = KN02_IRQ_NR(KN02_CSR_INR_TC0),
341 [DEC_IRQ_TC1] = KN02_IRQ_NR(KN02_CSR_INR_TC1),
342 [DEC_IRQ_TC2] = KN02_IRQ_NR(KN02_CSR_INR_TC2),
343 [DEC_IRQ_TIMER] = -1,
344 [DEC_IRQ_VIDEO] = -1,
345 [DEC_IRQ_ASC_MERR] = -1,
346 [DEC_IRQ_ASC_ERR] = -1,
347 [DEC_IRQ_ASC_DMA] = -1,
348 [DEC_IRQ_FLOPPY_ERR] = -1,
349 [DEC_IRQ_ISDN_ERR] = -1,
350 [DEC_IRQ_ISDN_RXDMA] = -1,
351 [DEC_IRQ_ISDN_TXDMA] = -1,
352 [DEC_IRQ_LANCE_MERR] = -1,
353 [DEC_IRQ_SCC0A_RXERR] = -1,
354 [DEC_IRQ_SCC0A_RXDMA] = -1,
355 [DEC_IRQ_SCC0A_TXERR] = -1,
356 [DEC_IRQ_SCC0A_TXDMA] = -1,
357 [DEC_IRQ_AB_RXERR] = -1,
358 [DEC_IRQ_AB_RXDMA] = -1,
359 [DEC_IRQ_AB_TXERR] = -1,
360 [DEC_IRQ_AB_TXDMA] = -1,
361 [DEC_IRQ_SCC1A_RXERR] = -1,
362 [DEC_IRQ_SCC1A_RXDMA] = -1,
363 [DEC_IRQ_SCC1A_TXERR] = -1,
364 [DEC_IRQ_SCC1A_TXDMA] = -1,
365 };
366
367 static int_ptr kn02_cpu_mask_nr_tbl[][2] __initdata = {
368 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_BUS) },
369 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_BUS) } },
370 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_RTC) },
371 { .i = DEC_CPU_IRQ_NR(KN02_CPU_INR_RTC) } },
372 { { .i = DEC_CPU_IRQ_MASK(KN02_CPU_INR_CASCADE) },
373 { .p = kn02_io_int } },
374 { { .i = DEC_CPU_IRQ_ALL },
375 { .p = cpu_all_int } },
376 };
377
378 static int_ptr kn02_asic_mask_nr_tbl[][2] __initdata = {
379 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_DZ11) },
380 { .i = KN02_IRQ_NR(KN02_CSR_INR_DZ11) } },
381 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_ASC) },
382 { .i = KN02_IRQ_NR(KN02_CSR_INR_ASC) } },
383 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_LANCE) },
384 { .i = KN02_IRQ_NR(KN02_CSR_INR_LANCE) } },
385 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC2) },
386 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC2) } },
387 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC1) },
388 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC1) } },
389 { { .i = KN02_IRQ_MASK(KN02_CSR_INR_TC0) },
390 { .i = KN02_IRQ_NR(KN02_CSR_INR_TC0) } },
391 { { .i = KN02_IRQ_ALL },
392 { .p = kn02_all_int } },
393 };
394
395 static void __init dec_init_kn02(void)
396 {
397 /* IRQ routing. */
398 memcpy(&dec_interrupt, &kn02_interrupt,
399 sizeof(kn02_interrupt));
400
401 /* CPU IRQ priorities. */
402 memcpy(&cpu_mask_nr_tbl, &kn02_cpu_mask_nr_tbl,
403 sizeof(kn02_cpu_mask_nr_tbl));
404
405 /* KN02 CSR IRQ priorities. */
406 memcpy(&asic_mask_nr_tbl, &kn02_asic_mask_nr_tbl,
407 sizeof(kn02_asic_mask_nr_tbl));
408
409 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
410 init_kn02_irqs(KN02_IRQ_BASE);
411
412 } /* dec_init_kn02 */
413
414
415 /*
416 * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
417 * (xx = 20, 25, 33), aka 3min. Also applies to KN04(-BA), aka
418 * DS5000/150, aka 4min.
419 */
420 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
421 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_CASCADE),
422 [DEC_IRQ_AB_RECV] = -1,
423 [DEC_IRQ_AB_XMIT] = -1,
424 [DEC_IRQ_DZ11] = -1,
425 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02BA_IO_INR_ASC),
426 [DEC_IRQ_FLOPPY] = -1,
427 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
428 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_HALT),
429 [DEC_IRQ_ISDN] = -1,
430 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02BA_IO_INR_LANCE),
431 [DEC_IRQ_BUS] = IO_IRQ_NR(KN02BA_IO_INR_BUS),
432 [DEC_IRQ_PSU] = IO_IRQ_NR(KN02BA_IO_INR_PSU),
433 [DEC_IRQ_RTC] = IO_IRQ_NR(KN02BA_IO_INR_RTC),
434 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02BA_IO_INR_SCC0),
435 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN02BA_IO_INR_SCC1),
436 [DEC_IRQ_SII] = -1,
437 [DEC_IRQ_TC0] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0),
438 [DEC_IRQ_TC1] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1),
439 [DEC_IRQ_TC2] = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2),
440 [DEC_IRQ_TIMER] = -1,
441 [DEC_IRQ_VIDEO] = -1,
442 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
443 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
444 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
445 [DEC_IRQ_FLOPPY_ERR] = -1,
446 [DEC_IRQ_ISDN_ERR] = -1,
447 [DEC_IRQ_ISDN_RXDMA] = -1,
448 [DEC_IRQ_ISDN_TXDMA] = -1,
449 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
450 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
451 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
452 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
453 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
454 [DEC_IRQ_AB_RXERR] = -1,
455 [DEC_IRQ_AB_RXDMA] = -1,
456 [DEC_IRQ_AB_TXERR] = -1,
457 [DEC_IRQ_AB_TXDMA] = -1,
458 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
459 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
460 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
461 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
462 };
463
464 static int_ptr kn02ba_cpu_mask_nr_tbl[][2] __initdata = {
465 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_CASCADE) },
466 { .p = kn02xa_io_int } },
467 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC2) },
468 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC2) } },
469 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC1) },
470 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC1) } },
471 { { .i = DEC_CPU_IRQ_MASK(KN02BA_CPU_INR_TC0) },
472 { .i = DEC_CPU_IRQ_NR(KN02BA_CPU_INR_TC0) } },
473 { { .i = DEC_CPU_IRQ_ALL },
474 { .p = cpu_all_int } },
475 };
476
477 static int_ptr kn02ba_asic_mask_nr_tbl[][2] __initdata = {
478 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_BUS) },
479 { .i = IO_IRQ_NR(KN02BA_IO_INR_BUS) } },
480 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_RTC) },
481 { .i = IO_IRQ_NR(KN02BA_IO_INR_RTC) } },
482 { { .i = IO_IRQ_DMA },
483 { .p = asic_dma_int } },
484 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC0) },
485 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC0) } },
486 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_SCC1) },
487 { .i = IO_IRQ_NR(KN02BA_IO_INR_SCC1) } },
488 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_ASC) },
489 { .i = IO_IRQ_NR(KN02BA_IO_INR_ASC) } },
490 { { .i = IO_IRQ_MASK(KN02BA_IO_INR_LANCE) },
491 { .i = IO_IRQ_NR(KN02BA_IO_INR_LANCE) } },
492 { { .i = IO_IRQ_ALL },
493 { .p = asic_all_int } },
494 };
495
496 static void __init dec_init_kn02ba(void)
497 {
498 /* IRQ routing. */
499 memcpy(&dec_interrupt, &kn02ba_interrupt,
500 sizeof(kn02ba_interrupt));
501
502 /* CPU IRQ priorities. */
503 memcpy(&cpu_mask_nr_tbl, &kn02ba_cpu_mask_nr_tbl,
504 sizeof(kn02ba_cpu_mask_nr_tbl));
505
506 /* I/O ASIC IRQ priorities. */
507 memcpy(&asic_mask_nr_tbl, &kn02ba_asic_mask_nr_tbl,
508 sizeof(kn02ba_asic_mask_nr_tbl));
509
510 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
511 init_ioasic_irqs(IO_IRQ_BASE);
512
513 } /* dec_init_kn02ba */
514
515
516 /*
517 * Machine-specific initialisation for KN02-CA, aka DS5000/xx,
518 * (xx = 20, 25, 33), aka MAXine. Also applies to KN04(-CA), aka
519 * DS5000/50, aka 4MAXine.
520 */
521 static int kn02ca_interrupt[DEC_NR_INTS] __initdata = {
522 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_CASCADE),
523 [DEC_IRQ_AB_RECV] = IO_IRQ_NR(KN02CA_IO_INR_AB_RECV),
524 [DEC_IRQ_AB_XMIT] = IO_IRQ_NR(KN02CA_IO_INR_AB_XMIT),
525 [DEC_IRQ_DZ11] = -1,
526 [DEC_IRQ_ASC] = IO_IRQ_NR(KN02CA_IO_INR_ASC),
527 [DEC_IRQ_FLOPPY] = IO_IRQ_NR(KN02CA_IO_INR_FLOPPY),
528 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
529 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_HALT),
530 [DEC_IRQ_ISDN] = IO_IRQ_NR(KN02CA_IO_INR_ISDN),
531 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN02CA_IO_INR_LANCE),
532 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS),
533 [DEC_IRQ_PSU] = -1,
534 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC),
535 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN02CA_IO_INR_SCC0),
536 [DEC_IRQ_SCC1] = -1,
537 [DEC_IRQ_SII] = -1,
538 [DEC_IRQ_TC0] = IO_IRQ_NR(KN02CA_IO_INR_TC0),
539 [DEC_IRQ_TC1] = IO_IRQ_NR(KN02CA_IO_INR_TC1),
540 [DEC_IRQ_TC2] = -1,
541 [DEC_IRQ_TIMER] = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_TIMER),
542 [DEC_IRQ_VIDEO] = IO_IRQ_NR(KN02CA_IO_INR_VIDEO),
543 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
544 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
545 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
546 [DEC_IRQ_FLOPPY_ERR] = IO_IRQ_NR(IO_INR_FLOPPY_ERR),
547 [DEC_IRQ_ISDN_ERR] = IO_IRQ_NR(IO_INR_ISDN_ERR),
548 [DEC_IRQ_ISDN_RXDMA] = IO_IRQ_NR(IO_INR_ISDN_RXDMA),
549 [DEC_IRQ_ISDN_TXDMA] = IO_IRQ_NR(IO_INR_ISDN_TXDMA),
550 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
551 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
552 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
553 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
554 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
555 [DEC_IRQ_AB_RXERR] = IO_IRQ_NR(IO_INR_AB_RXERR),
556 [DEC_IRQ_AB_RXDMA] = IO_IRQ_NR(IO_INR_AB_RXDMA),
557 [DEC_IRQ_AB_TXERR] = IO_IRQ_NR(IO_INR_AB_TXERR),
558 [DEC_IRQ_AB_TXDMA] = IO_IRQ_NR(IO_INR_AB_TXDMA),
559 [DEC_IRQ_SCC1A_RXERR] = -1,
560 [DEC_IRQ_SCC1A_RXDMA] = -1,
561 [DEC_IRQ_SCC1A_TXERR] = -1,
562 [DEC_IRQ_SCC1A_TXDMA] = -1,
563 };
564
565 static int_ptr kn02ca_cpu_mask_nr_tbl[][2] __initdata = {
566 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_BUS) },
567 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_BUS) } },
568 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_RTC) },
569 { .i = DEC_CPU_IRQ_NR(KN02CA_CPU_INR_RTC) } },
570 { { .i = DEC_CPU_IRQ_MASK(KN02CA_CPU_INR_CASCADE) },
571 { .p = kn02xa_io_int } },
572 { { .i = DEC_CPU_IRQ_ALL },
573 { .p = cpu_all_int } },
574 };
575
576 static int_ptr kn02ca_asic_mask_nr_tbl[][2] __initdata = {
577 { { .i = IO_IRQ_DMA },
578 { .p = asic_dma_int } },
579 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_SCC0) },
580 { .i = IO_IRQ_NR(KN02CA_IO_INR_SCC0) } },
581 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_ASC) },
582 { .i = IO_IRQ_NR(KN02CA_IO_INR_ASC) } },
583 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_LANCE) },
584 { .i = IO_IRQ_NR(KN02CA_IO_INR_LANCE) } },
585 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC1) },
586 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC1) } },
587 { { .i = IO_IRQ_MASK(KN02CA_IO_INR_TC0) },
588 { .i = IO_IRQ_NR(KN02CA_IO_INR_TC0) } },
589 { { .i = IO_IRQ_ALL },
590 { .p = asic_all_int } },
591 };
592
593 static void __init dec_init_kn02ca(void)
594 {
595 /* IRQ routing. */
596 memcpy(&dec_interrupt, &kn02ca_interrupt,
597 sizeof(kn02ca_interrupt));
598
599 /* CPU IRQ priorities. */
600 memcpy(&cpu_mask_nr_tbl, &kn02ca_cpu_mask_nr_tbl,
601 sizeof(kn02ca_cpu_mask_nr_tbl));
602
603 /* I/O ASIC IRQ priorities. */
604 memcpy(&asic_mask_nr_tbl, &kn02ca_asic_mask_nr_tbl,
605 sizeof(kn02ca_asic_mask_nr_tbl));
606
607 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
608 init_ioasic_irqs(IO_IRQ_BASE);
609
610 } /* dec_init_kn02ca */
611
612
613 /*
614 * Machine-specific initialisation for KN03, aka DS5000/240,
615 * aka 3max+ and DS5900, aka BIGmax. Also applies to KN05, aka
616 * DS5000/260, aka 4max+ and DS5900/260.
617 */
618 static int kn03_interrupt[DEC_NR_INTS] __initdata = {
619 [DEC_IRQ_CASCADE] = DEC_CPU_IRQ_NR(KN03_CPU_INR_CASCADE),
620 [DEC_IRQ_AB_RECV] = -1,
621 [DEC_IRQ_AB_XMIT] = -1,
622 [DEC_IRQ_DZ11] = -1,
623 [DEC_IRQ_ASC] = IO_IRQ_NR(KN03_IO_INR_ASC),
624 [DEC_IRQ_FLOPPY] = -1,
625 [DEC_IRQ_FPU] = DEC_CPU_IRQ_NR(DEC_CPU_INR_FPU),
626 [DEC_IRQ_HALT] = DEC_CPU_IRQ_NR(KN03_CPU_INR_HALT),
627 [DEC_IRQ_ISDN] = -1,
628 [DEC_IRQ_LANCE] = IO_IRQ_NR(KN03_IO_INR_LANCE),
629 [DEC_IRQ_BUS] = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS),
630 [DEC_IRQ_PSU] = IO_IRQ_NR(KN03_IO_INR_PSU),
631 [DEC_IRQ_RTC] = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC),
632 [DEC_IRQ_SCC0] = IO_IRQ_NR(KN03_IO_INR_SCC0),
633 [DEC_IRQ_SCC1] = IO_IRQ_NR(KN03_IO_INR_SCC1),
634 [DEC_IRQ_SII] = -1,
635 [DEC_IRQ_TC0] = IO_IRQ_NR(KN03_IO_INR_TC0),
636 [DEC_IRQ_TC1] = IO_IRQ_NR(KN03_IO_INR_TC1),
637 [DEC_IRQ_TC2] = IO_IRQ_NR(KN03_IO_INR_TC2),
638 [DEC_IRQ_TIMER] = -1,
639 [DEC_IRQ_VIDEO] = -1,
640 [DEC_IRQ_ASC_MERR] = IO_IRQ_NR(IO_INR_ASC_MERR),
641 [DEC_IRQ_ASC_ERR] = IO_IRQ_NR(IO_INR_ASC_ERR),
642 [DEC_IRQ_ASC_DMA] = IO_IRQ_NR(IO_INR_ASC_DMA),
643 [DEC_IRQ_FLOPPY_ERR] = -1,
644 [DEC_IRQ_ISDN_ERR] = -1,
645 [DEC_IRQ_ISDN_RXDMA] = -1,
646 [DEC_IRQ_ISDN_TXDMA] = -1,
647 [DEC_IRQ_LANCE_MERR] = IO_IRQ_NR(IO_INR_LANCE_MERR),
648 [DEC_IRQ_SCC0A_RXERR] = IO_IRQ_NR(IO_INR_SCC0A_RXERR),
649 [DEC_IRQ_SCC0A_RXDMA] = IO_IRQ_NR(IO_INR_SCC0A_RXDMA),
650 [DEC_IRQ_SCC0A_TXERR] = IO_IRQ_NR(IO_INR_SCC0A_TXERR),
651 [DEC_IRQ_SCC0A_TXDMA] = IO_IRQ_NR(IO_INR_SCC0A_TXDMA),
652 [DEC_IRQ_AB_RXERR] = -1,
653 [DEC_IRQ_AB_RXDMA] = -1,
654 [DEC_IRQ_AB_TXERR] = -1,
655 [DEC_IRQ_AB_TXDMA] = -1,
656 [DEC_IRQ_SCC1A_RXERR] = IO_IRQ_NR(IO_INR_SCC1A_RXERR),
657 [DEC_IRQ_SCC1A_RXDMA] = IO_IRQ_NR(IO_INR_SCC1A_RXDMA),
658 [DEC_IRQ_SCC1A_TXERR] = IO_IRQ_NR(IO_INR_SCC1A_TXERR),
659 [DEC_IRQ_SCC1A_TXDMA] = IO_IRQ_NR(IO_INR_SCC1A_TXDMA),
660 };
661
662 static int_ptr kn03_cpu_mask_nr_tbl[][2] __initdata = {
663 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_BUS) },
664 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_BUS) } },
665 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_RTC) },
666 { .i = DEC_CPU_IRQ_NR(KN03_CPU_INR_RTC) } },
667 { { .i = DEC_CPU_IRQ_MASK(KN03_CPU_INR_CASCADE) },
668 { .p = kn03_io_int } },
669 { { .i = DEC_CPU_IRQ_ALL },
670 { .p = cpu_all_int } },
671 };
672
673 static int_ptr kn03_asic_mask_nr_tbl[][2] __initdata = {
674 { { .i = IO_IRQ_DMA },
675 { .p = asic_dma_int } },
676 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC0) },
677 { .i = IO_IRQ_NR(KN03_IO_INR_SCC0) } },
678 { { .i = IO_IRQ_MASK(KN03_IO_INR_SCC1) },
679 { .i = IO_IRQ_NR(KN03_IO_INR_SCC1) } },
680 { { .i = IO_IRQ_MASK(KN03_IO_INR_ASC) },
681 { .i = IO_IRQ_NR(KN03_IO_INR_ASC) } },
682 { { .i = IO_IRQ_MASK(KN03_IO_INR_LANCE) },
683 { .i = IO_IRQ_NR(KN03_IO_INR_LANCE) } },
684 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC2) },
685 { .i = IO_IRQ_NR(KN03_IO_INR_TC2) } },
686 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC1) },
687 { .i = IO_IRQ_NR(KN03_IO_INR_TC1) } },
688 { { .i = IO_IRQ_MASK(KN03_IO_INR_TC0) },
689 { .i = IO_IRQ_NR(KN03_IO_INR_TC0) } },
690 { { .i = IO_IRQ_ALL },
691 { .p = asic_all_int } },
692 };
693
694 static void __init dec_init_kn03(void)
695 {
696 /* IRQ routing. */
697 memcpy(&dec_interrupt, &kn03_interrupt,
698 sizeof(kn03_interrupt));
699
700 /* CPU IRQ priorities. */
701 memcpy(&cpu_mask_nr_tbl, &kn03_cpu_mask_nr_tbl,
702 sizeof(kn03_cpu_mask_nr_tbl));
703
704 /* I/O ASIC IRQ priorities. */
705 memcpy(&asic_mask_nr_tbl, &kn03_asic_mask_nr_tbl,
706 sizeof(kn03_asic_mask_nr_tbl));
707
708 mips_cpu_irq_init(DEC_CPU_IRQ_BASE);
709 init_ioasic_irqs(IO_IRQ_BASE);
710
711 } /* dec_init_kn03 */
712
713
714 void __init arch_init_irq(void)
715 {
716 switch (mips_machtype) {
717 case MACH_DS23100: /* DS2100/DS3100 Pmin/Pmax */
718 dec_init_kn01();
719 break;
720 case MACH_DS5100: /* DS5100 MIPSmate */
721 dec_init_kn230();
722 break;
723 case MACH_DS5000_200: /* DS5000/200 3max */
724 dec_init_kn02();
725 break;
726 case MACH_DS5000_1XX: /* DS5000/1xx 3min */
727 dec_init_kn02ba();
728 break;
729 case MACH_DS5000_2X0: /* DS5000/240 3max+ */
730 case MACH_DS5900: /* DS5900 bigmax */
731 dec_init_kn03();
732 break;
733 case MACH_DS5000_XX: /* Personal DS5000/xx */
734 dec_init_kn02ca();
735 break;
736 case MACH_DS5800: /* DS5800 Isis */
737 panic("Don't know how to set this up!");
738 break;
739 case MACH_DS5400: /* DS5400 MIPSfair */
740 panic("Don't know how to set this up!");
741 break;
742 case MACH_DS5500: /* DS5500 MIPSfair-2 */
743 panic("Don't know how to set this up!");
744 break;
745 }
746 set_except_vector(0, decstation_handle_int);
747
748 /* Free the FPU interrupt if the exception is present. */
749 if (!cpu_has_nofpuex) {
750 cpu_fpu_mask = 0;
751 dec_interrupt[DEC_IRQ_FPU] = -1;
752 }
753
754 /* Register board interrupts: FPU and cascade. */
755 if (dec_interrupt[DEC_IRQ_FPU] >= 0)
756 setup_irq(dec_interrupt[DEC_IRQ_FPU], &fpuirq);
757 if (dec_interrupt[DEC_IRQ_CASCADE] >= 0)
758 setup_irq(dec_interrupt[DEC_IRQ_CASCADE], &ioirq);
759
760 /* Register the bus error interrupt. */
761 if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq.handler)
762 setup_irq(dec_interrupt[DEC_IRQ_BUS], &busirq);
763
764 /* Register the HALT interrupt. */
765 if (dec_interrupt[DEC_IRQ_HALT] >= 0)
766 setup_irq(dec_interrupt[DEC_IRQ_HALT], &haltirq);
767 }
WRT350N Kernel Patches