arch/mips/jmr3927/rbhma3100/setup.c

   1 /***********************************************************************
   2  *
   3  * Copyright 2001 MontaVista Software Inc.
   4  * Author: MontaVista Software, Inc.
   5  *              ahennessy@mvista.com
   6  *
   7  * Based on arch/mips/ddb5xxx/ddb5477/setup.c
   8  *
   9  *     Setup file for JMR3927.
  10  *
  11  * Copyright (C) 2000-2001 Toshiba Corporation
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  *
  18  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  19  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  20  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  21  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  22  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  24  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  26  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  *  You should have received a copy of the  GNU General Public License along
  30  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  31  *  675 Mass Ave, Cambridge, MA 02139, USA.
  32  *
  33  ***********************************************************************
  34  */
  35
  36 #include <linux/config.h>
  37 #include <linux/init.h>
  38 #include <linux/kernel.h>
  39 #include <linux/kdev_t.h>
  40 #include <linux/types.h>
  41 #include <linux/sched.h>
  42 #include <linux/pci.h>
  43 #include <linux/ide.h>
  44 #include <linux/ioport.h>
  45 #include <linux/param.h>        /* for HZ */
  46 #include <linux/delay.h>
  47 #ifdef CONFIG_SERIAL_TXX9
  48 #include <linux/tty.h>
  49 #include <linux/serial.h>
  50 #include <linux/serial_core.h>
  51 #endif
  52
  53 #include <asm/addrspace.h>
  54 #include <asm/time.h>
  55 #include <asm/bcache.h>
  56 #include <asm/irq.h>
  57 #include <asm/reboot.h>
  58 #include <asm/gdb-stub.h>
  59 #include <asm/jmr3927/jmr3927.h>
  60 #include <asm/mipsregs.h>
  61 #include <asm/traps.h>
  62
  63 extern void puts(unsigned char *cp);
  64
  65 /* Tick Timer divider */
  66 #define JMR3927_TIMER_CCD       0       /* 1/2 */
  67 #define JMR3927_TIMER_CLK       (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
  68
  69 unsigned char led_state = 0xf;
  70
  71 struct {
  72     struct resource ram0;
  73     struct resource ram1;
  74     struct resource pcimem;
  75     struct resource iob;
  76     struct resource ioc;
  77     struct resource pciio;
  78     struct resource jmy1394;
  79     struct resource rom1;
  80     struct resource rom0;
  81     struct resource sio0;
  82     struct resource sio1;
  83 } jmr3927_resources = {
  84     { "RAM0",           0,         0x01FFFFFF,  IORESOURCE_MEM },
  85     { "RAM1",          0x02000000, 0x03FFFFFF,  IORESOURCE_MEM },
  86     { "PCIMEM",        0x08000000, 0x07FFFFFF,  IORESOURCE_MEM },
  87     { "IOB",           0x10000000, 0x13FFFFFF                  },
  88     { "IOC",           0x14000000, 0x14FFFFFF                  },
  89     { "PCIIO",         0x15000000, 0x15FFFFFF                  },
  90     { "JMY1394",       0x1D000000, 0x1D3FFFFF                  },
  91     { "ROM1",          0x1E000000, 0x1E3FFFFF                  },
  92     { "ROM0",          0x1FC00000, 0x1FFFFFFF                  },
  93     { "SIO0",          0xFFFEF300, 0xFFFEF3FF                  },
  94     { "SIO1",          0xFFFEF400, 0xFFFEF4FF                  },
  95 };
  96
  97 /* don't enable - see errata */
  98 int jmr3927_ccfg_toeon = 0;
  99
 100 static inline void do_reset(void)
 101 {
 102 #ifdef CONFIG_TC35815
 103         extern void tc35815_killall(void);
 104         tc35815_killall();
 105 #endif
 106 #if 1   /* Resetting PCI bus */
 107         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 108         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
 109         (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR);       /* flush WB */
 110         mdelay(1);
 111         jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 112 #endif
 113         jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
 114 }
 115
 116 static void jmr3927_machine_restart(char *command)
 117 {
 118         local_irq_disable();
 119         puts("Rebooting...");
 120         do_reset();
 121 }
 122
 123 static void jmr3927_machine_halt(void)
 124 {
 125         puts("JMR-TX3927 halted.\n");
 126         while (1);
 127 }
 128
 129 static void jmr3927_machine_power_off(void)
 130 {
 131         puts("JMR-TX3927 halted. Please turn off the power.\n");
 132         while (1);
 133 }
 134
 135 #define USE_RTC_DS1742
 136 #ifdef USE_RTC_DS1742
 137 extern void rtc_ds1742_init(unsigned long base);
 138 #endif
 139 static void __init jmr3927_time_init(void)
 140 {
 141 #ifdef USE_RTC_DS1742
 142         if (jmr3927_have_nvram()) {
 143                 rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
 144         }
 145 #endif
 146 }
 147
 148 unsigned long jmr3927_do_gettimeoffset(void);
 149 extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
 150
 151 static void __init jmr3927_timer_setup(struct irqaction *irq)
 152 {
 153         do_gettimeoffset = jmr3927_do_gettimeoffset;
 154
 155         jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
 156         jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
 157         jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
 158         jmr3927_tmrptr->tcr =
 159                 TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
 160
 161         setup_irq(JMR3927_IRQ_TICK, irq);
 162 }
 163
 164 #define USECS_PER_JIFFY (1000000/HZ)
 165
 166 unsigned long jmr3927_do_gettimeoffset(void)
 167 {
 168        unsigned long count;
 169        unsigned long res = 0;
 170
 171        /* MUST read TRR before TISR. */
 172        count = jmr3927_tmrptr->trr;
 173
 174        if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
 175                /* timer interrupt is pending.  use Max value. */
 176                res = USECS_PER_JIFFY - 1;
 177        } else {
 178                /* convert to usec */
 179                /* res = count / (JMR3927_TIMER_CLK / 1000000); */
 180                res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
 181
 182                /*
 183                 * Due to possible jiffies inconsistencies, we need to check
 184                 * the result so that we'll get a timer that is monotonic.
 185                 */
 186                if (res >= USECS_PER_JIFFY)
 187                        res = USECS_PER_JIFFY-1;
 188        }
 189
 190        return res;
 191 }
 192
 193
 194 //#undef DO_WRITE_THROUGH
 195 #define DO_WRITE_THROUGH
 196 #define DO_ENABLE_CACHE
 197
 198 extern char * __init prom_getcmdline(void);
 199 static void jmr3927_board_init(void);
 200 extern struct resource pci_io_resource;
 201 extern struct resource pci_mem_resource;
 202
 203 void __init plat_setup(void)
 204 {
 205         char *argptr;
 206
 207         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 208
 209         board_time_init = jmr3927_time_init;
 210         board_timer_setup = jmr3927_timer_setup;
 211
 212         _machine_restart = jmr3927_machine_restart;
 213         _machine_halt = jmr3927_machine_halt;
 214         _machine_power_off = jmr3927_machine_power_off;
 215
 216         /*
 217          * IO/MEM resources.
 218          */
 219         ioport_resource.start = pci_io_resource.start;
 220         ioport_resource.end = pci_io_resource.end;
 221         iomem_resource.start = 0;
 222         iomem_resource.end = 0xffffffff;
 223
 224         /* Reboot on panic */
 225         panic_timeout = 180;
 226
 227         {
 228                 unsigned int conf;
 229                 conf = read_c0_conf();
 230         }
 231
 232 #if 1
 233         /* cache setup */
 234         {
 235                 unsigned int conf;
 236 #ifdef DO_ENABLE_CACHE
 237                 int mips_ic_disable = 0, mips_dc_disable = 0;
 238 #else
 239                 int mips_ic_disable = 1, mips_dc_disable = 1;
 240 #endif
 241 #ifdef DO_WRITE_THROUGH
 242                 int mips_config_cwfon = 0;
 243                 int mips_config_wbon = 0;
 244 #else
 245                 int mips_config_cwfon = 1;
 246                 int mips_config_wbon = 1;
 247 #endif
 248
 249                 conf = read_c0_conf();
 250                 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
 251                 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
 252                 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
 253                 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
 254                 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
 255
 256                 write_c0_conf(conf);
 257                 write_c0_cache(0);
 258         }
 259 #endif
 260
 261         /* initialize board */
 262         jmr3927_board_init();
 263
 264         argptr = prom_getcmdline();
 265
 266         if ((argptr = strstr(argptr, "toeon")) != NULL) {
 267                         jmr3927_ccfg_toeon = 1;
 268         }
 269         argptr = prom_getcmdline();
 270         if ((argptr = strstr(argptr, "ip=")) == NULL) {
 271                 argptr = prom_getcmdline();
 272                 strcat(argptr, " ip=bootp");
 273         }
 274
 275 #ifdef CONFIG_SERIAL_TXX9
 276         {
 277                 extern int early_serial_txx9_setup(struct uart_port *port);
 278                 int i;
 279                 struct uart_port req;
 280                 for(i = 0; i < 2; i++) {
 281                         memset(&req, 0, sizeof(req));
 282                         req.line = i;
 283                         req.iotype = UPIO_MEM;
 284                         req.membase = (char *)TX3927_SIO_REG(i);
 285                         req.mapbase = TX3927_SIO_REG(i);
 286                         req.irq = i == 0 ?
 287                                 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
 288                         if (i == 0)
 289                                 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 290                         req.uartclk = JMR3927_IMCLK;
 291                         early_serial_txx9_setup(&req);
 292                 }
 293         }
 294 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 295         argptr = prom_getcmdline();
 296         if ((argptr = strstr(argptr, "console=")) == NULL) {
 297                 argptr = prom_getcmdline();
 298                 strcat(argptr, " console=ttyS1,115200");
 299         }
 300 #endif
 301 #endif
 302 }
 303
 304 static void tx3927_setup(void);
 305
 306 #ifdef CONFIG_PCI
 307 unsigned long mips_pci_io_base;
 308 unsigned long mips_pci_io_size;
 309 unsigned long mips_pci_mem_base;
 310 unsigned long mips_pci_mem_size;
 311 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 312 unsigned long mips_pci_io_pciaddr = 0;
 313 #endif
 314
 315 static void __init jmr3927_board_init(void)
 316 {
 317         char *argptr;
 318
 319 #ifdef CONFIG_PCI
 320         mips_pci_io_base = JMR3927_PCIIO;
 321         mips_pci_io_size = JMR3927_PCIIO_SIZE;
 322         mips_pci_mem_base = JMR3927_PCIMEM;
 323         mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
 324 #endif
 325
 326         tx3927_setup();
 327
 328         if (jmr3927_have_isac()) {
 329
 330 #ifdef CONFIG_FB_E1355
 331                 argptr = prom_getcmdline();
 332                 if ((argptr = strstr(argptr, "video=")) == NULL) {
 333                         argptr = prom_getcmdline();
 334                         strcat(argptr, " video=e1355fb:crt16h");
 335                 }
 336 #endif
 337
 338 #ifdef CONFIG_BLK_DEV_IDE
 339                 /* overrides PCI-IDE */
 340 #endif
 341         }
 342
 343         /* SIO0 DTR on */
 344         jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
 345
 346         jmr3927_led_set(0);
 347
 348
 349         if (jmr3927_have_isac())
 350                 jmr3927_io_led_set(0);
 351         printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
 352                jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
 353                jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
 354                jmr3927_dipsw1(), jmr3927_dipsw2(),
 355                jmr3927_dipsw3(), jmr3927_dipsw4());
 356         if (jmr3927_have_isac())
 357                 printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
 358                        jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
 359                        jmr3927_io_dipsw());
 360 }
 361
 362 void __init tx3927_setup(void)
 363 {
 364         int i;
 365
 366         /* SDRAMC are configured by PROM */
 367
 368         /* ROMC */
 369         tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
 370         tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
 371         tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
 372         tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
 373
 374         /* CCFG */
 375         /* enable Timeout BusError */
 376         if (jmr3927_ccfg_toeon)
 377                 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
 378
 379         /* clear BusErrorOnWrite flag */
 380         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
 381         /* Disable PCI snoop */
 382         tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
 383
 384 #ifdef DO_WRITE_THROUGH
 385         /* Enable PCI SNOOP - with write through only */
 386         tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
 387 #endif
 388
 389         /* Pin selection */
 390         tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
 391         tx3927_ccfgptr->pcfg |=
 392                 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
 393                 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
 394
 395         printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
 396                tx3927_ccfgptr->crir,
 397                tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
 398
 399         /* IRC */
 400         /* disable interrupt control */
 401         tx3927_ircptr->cer = 0;
 402         /* mask all IRC interrupts */
 403         tx3927_ircptr->imr = 0;
 404         for (i = 0; i < TX3927_NUM_IR / 2; i++) {
 405                 tx3927_ircptr->ilr[i] = 0;
 406         }
 407         /* setup IRC interrupt mode (Low Active) */
 408         for (i = 0; i < TX3927_NUM_IR / 8; i++) {
 409                 tx3927_ircptr->cr[i] = 0;
 410         }
 411
 412         /* TMR */
 413         /* disable all timers */
 414         for (i = 0; i < TX3927_NR_TMR; i++) {
 415                 tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
 416                 tx3927_tmrptr(i)->tisr = 0;
 417                 tx3927_tmrptr(i)->cpra = 0xffffffff;
 418                 tx3927_tmrptr(i)->itmr = 0;
 419                 tx3927_tmrptr(i)->ccdr = 0;
 420                 tx3927_tmrptr(i)->pgmr = 0;
 421         }
 422
 423         /* DMA */
 424         tx3927_dmaptr->mcr = 0;
 425         for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
 426                 /* reset channel */
 427                 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
 428                 tx3927_dmaptr->ch[i].ccr = 0;
 429         }
 430         /* enable DMA */
 431 #ifdef __BIG_ENDIAN
 432         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
 433 #else
 434         tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
 435 #endif
 436
 437 #ifdef CONFIG_PCI
 438         /* PCIC */
 439         printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
 440                tx3927_pcicptr->did, tx3927_pcicptr->vid,
 441                tx3927_pcicptr->rid);
 442         if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
 443                 printk("External\n");
 444                 /* XXX */
 445         } else {
 446                 printk("Internal\n");
 447
 448                 /* Reset PCI Bus */
 449                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 450                 udelay(100);
 451                 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
 452                                     JMR3927_IOC_RESET_ADDR);
 453                 udelay(100);
 454                 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
 455
 456
 457                 /* Disable External PCI Config. Access */
 458                 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
 459 #ifdef __BIG_ENDIAN
 460                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
 461                         TX3927_PCIC_LBC_TIBSE |
 462                         TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
 463 #endif
 464                 /* LB->PCI mappings */
 465                 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
 466                 tx3927_pcicptr->ilbioma = mips_pci_io_base;
 467                 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
 468                 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
 469                 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
 470                 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
 471                 /* PCI->LB mappings */
 472                 tx3927_pcicptr->iobas = 0xffffffff;
 473                 tx3927_pcicptr->ioba = 0;
 474                 tx3927_pcicptr->tlbioma = 0;
 475                 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
 476                 tx3927_pcicptr->mba = 0;
 477                 tx3927_pcicptr->tlbmma = 0;
 478 #ifndef JMR3927_INIT_INDIRECT_PCI
 479                 /* Enable Direct mapping Address Space Decoder */
 480                 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
 481 #endif
 482
 483                 /* Clear All Local Bus Status */
 484                 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
 485                 /* Enable All Local Bus Interrupts */
 486                 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
 487                 /* Clear All PCI Status Error */
 488                 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
 489                 /* Enable All PCI Status Error Interrupts */
 490                 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
 491
 492                 /* PCIC Int => IRC IRQ10 */
 493                 tx3927_pcicptr->il = TX3927_IR_PCI;
 494 #if 1
 495                 /* Target Control (per errata) */
 496                 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
 497 #endif
 498
 499                 /* Enable Bus Arbiter */
 500 #if 0
 501                 tx3927_pcicptr->req_trace = 0x73737373;
 502 #endif
 503                 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
 504
 505                 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
 506                         PCI_COMMAND_MEMORY |
 507 #if 1
 508                         PCI_COMMAND_IO |
 509 #endif
 510                         PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 511         }
 512 #endif /* CONFIG_PCI */
 513
 514         /* PIO */
 515         /* PIO[15:12] connected to LEDs */
 516         tx3927_pioptr->dir = 0x0000f000;
 517         tx3927_pioptr->maskcpu = 0;
 518         tx3927_pioptr->maskext = 0;
 519         {
 520                 unsigned int conf;
 521
 522         conf = read_c0_conf();
 523                if (!(conf & TX39_CONF_ICE))
 524                        printk("TX3927 I-Cache disabled.\n");
 525                if (!(conf & TX39_CONF_DCE))
 526                        printk("TX3927 D-Cache disabled.\n");
 527                else if (!(conf & TX39_CONF_WBON))
 528                        printk("TX3927 D-Cache WriteThrough.\n");
 529                else if (!(conf & TX39_CONF_CWFON))
 530                        printk("TX3927 D-Cache WriteBack.\n");
 531                else
 532                        printk("TX3927 D-Cache WriteBack (CWF) .\n");
 533         }
 534 }