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[PATCH] Remove hosthw.h from rio (unused file)
[wrt350n-kernel.git] / drivers / net / bnx2.c
blob49fa1e4413fa470ddf7feadae6ec937a22c80e6e
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME "bnx2"
16 #define PFX DRV_MODULE_NAME ": "
17 #define DRV_MODULE_VERSION "1.4.30"
18 #define DRV_MODULE_RELDATE "October 11, 2005"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT (5*HZ)
24
25 static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44 BCM5708,
45 BCM5708S,
46 } board_t;
47
48 /* indexed by board_t, above */
49 static struct {
50 char *name;
51 } board_info[] __devinitdata = {
52 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
53 { "HP NC370T Multifunction Gigabit Server Adapter" },
54 { "HP NC370i Multifunction Gigabit Server Adapter" },
55 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
56 { "HP NC370F Multifunction Gigabit Server Adapter" },
57 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
58 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
59 };
60
61 static struct pci_device_id bnx2_pci_tbl[] = {
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
65 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
68 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
69 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
70 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
71 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
72 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
74 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
76 { 0, }
77 };
78
79 static struct flash_spec flash_table[] =
80 {
81 /* Slow EEPROM */
82 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
83 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
84 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
85 "EEPROM - slow"},
86 /* Expansion entry 0001 */
87 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
88 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
89 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
90 "Entry 0001"},
91 /* Saifun SA25F010 (non-buffered flash) */
92 /* strap, cfg1, & write1 need updates */
93 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
94 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
95 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
96 "Non-buffered flash (128kB)"},
97 /* Saifun SA25F020 (non-buffered flash) */
98 /* strap, cfg1, & write1 need updates */
99 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
100 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
101 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
102 "Non-buffered flash (256kB)"},
103 /* Expansion entry 0100 */
104 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
105 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
106 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
107 "Entry 0100"},
108 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
109 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
110 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
111 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
112 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
113 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
114 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
115 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
116 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
117 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
118 /* Saifun SA25F005 (non-buffered flash) */
119 /* strap, cfg1, & write1 need updates */
120 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
121 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
122 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
123 "Non-buffered flash (64kB)"},
124 /* Fast EEPROM */
125 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
126 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
127 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 "EEPROM - fast"},
129 /* Expansion entry 1001 */
130 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
131 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
132 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 "Entry 1001"},
134 /* Expansion entry 1010 */
135 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 1010"},
139 /* ATMEL AT45DB011B (buffered flash) */
140 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
141 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
142 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
143 "Buffered flash (128kB)"},
144 /* Expansion entry 1100 */
145 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
146 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 "Entry 1100"},
149 /* Expansion entry 1101 */
150 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
151 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
153 "Entry 1101"},
154 /* Ateml Expansion entry 1110 */
155 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
156 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
157 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
158 "Entry 1110 (Atmel)"},
159 /* ATMEL AT45DB021B (buffered flash) */
160 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
161 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
162 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
163 "Buffered flash (256kB)"},
164 };
165
166 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
167
168 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
169 {
170 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
171
172 if (diff > MAX_TX_DESC_CNT)
173 diff = (diff & MAX_TX_DESC_CNT) - 1;
174 return (bp->tx_ring_size - diff);
175 }
176
177 static u32
178 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
179 {
180 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
181 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
182 }
183
184 static void
185 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
186 {
187 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
188 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
189 }
190
191 static void
192 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
193 {
194 offset += cid_addr;
195 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
196 REG_WR(bp, BNX2_CTX_DATA, val);
197 }
198
199 static int
200 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
201 {
202 u32 val1;
203 int i, ret;
204
205 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
206 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
207 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
208
209 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
210 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
211
212 udelay(40);
213 }
214
215 val1 = (bp->phy_addr << 21) | (reg << 16) |
216 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
217 BNX2_EMAC_MDIO_COMM_START_BUSY;
218 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
219
220 for (i = 0; i < 50; i++) {
221 udelay(10);
222
223 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
224 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
225 udelay(5);
226
227 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
228 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
229
230 break;
231 }
232 }
233
234 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
235 *val = 0x0;
236 ret = -EBUSY;
237 }
238 else {
239 *val = val1;
240 ret = 0;
241 }
242
243 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
244 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
245 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
246
247 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
248 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249
250 udelay(40);
251 }
252
253 return ret;
254 }
255
256 static int
257 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
258 {
259 u32 val1;
260 int i, ret;
261
262 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
263 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
264 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
265
266 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
267 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
268
269 udelay(40);
270 }
271
272 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
273 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
274 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
275 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
276
277 for (i = 0; i < 50; i++) {
278 udelay(10);
279
280 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
281 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
282 udelay(5);
283 break;
284 }
285 }
286
287 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
288 ret = -EBUSY;
289 else
290 ret = 0;
291
292 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
293 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
294 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
295
296 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
297 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
298
299 udelay(40);
300 }
301
302 return ret;
303 }
304
305 static void
306 bnx2_disable_int(struct bnx2 *bp)
307 {
308 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
309 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
310 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
311 }
312
313 static void
314 bnx2_enable_int(struct bnx2 *bp)
315 {
316 u32 val;
317
318 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
319 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
320
321 val = REG_RD(bp, BNX2_HC_COMMAND);
322 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
323 }
324
325 static void
326 bnx2_disable_int_sync(struct bnx2 *bp)
327 {
328 atomic_inc(&bp->intr_sem);
329 bnx2_disable_int(bp);
330 synchronize_irq(bp->pdev->irq);
331 }
332
333 static void
334 bnx2_netif_stop(struct bnx2 *bp)
335 {
336 bnx2_disable_int_sync(bp);
337 if (netif_running(bp->dev)) {
338 netif_poll_disable(bp->dev);
339 netif_tx_disable(bp->dev);
340 bp->dev->trans_start = jiffies; /* prevent tx timeout */
341 }
342 }
343
344 static void
345 bnx2_netif_start(struct bnx2 *bp)
346 {
347 if (atomic_dec_and_test(&bp->intr_sem)) {
348 if (netif_running(bp->dev)) {
349 netif_wake_queue(bp->dev);
350 netif_poll_enable(bp->dev);
351 bnx2_enable_int(bp);
352 }
353 }
354 }
355
356 static void
357 bnx2_free_mem(struct bnx2 *bp)
358 {
359 if (bp->stats_blk) {
360 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
361 bp->stats_blk, bp->stats_blk_mapping);
362 bp->stats_blk = NULL;
363 }
364 if (bp->status_blk) {
365 pci_free_consistent(bp->pdev, sizeof(struct status_block),
366 bp->status_blk, bp->status_blk_mapping);
367 bp->status_blk = NULL;
368 }
369 if (bp->tx_desc_ring) {
370 pci_free_consistent(bp->pdev,
371 sizeof(struct tx_bd) * TX_DESC_CNT,
372 bp->tx_desc_ring, bp->tx_desc_mapping);
373 bp->tx_desc_ring = NULL;
374 }
375 kfree(bp->tx_buf_ring);
376 bp->tx_buf_ring = NULL;
377 if (bp->rx_desc_ring) {
378 pci_free_consistent(bp->pdev,
379 sizeof(struct rx_bd) * RX_DESC_CNT,
380 bp->rx_desc_ring, bp->rx_desc_mapping);
381 bp->rx_desc_ring = NULL;
382 }
383 kfree(bp->rx_buf_ring);
384 bp->rx_buf_ring = NULL;
385 }
386
387 static int
388 bnx2_alloc_mem(struct bnx2 *bp)
389 {
390 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
391 GFP_KERNEL);
392 if (bp->tx_buf_ring == NULL)
393 return -ENOMEM;
394
395 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
396 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
397 sizeof(struct tx_bd) *
398 TX_DESC_CNT,
399 &bp->tx_desc_mapping);
400 if (bp->tx_desc_ring == NULL)
401 goto alloc_mem_err;
402
403 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
404 GFP_KERNEL);
405 if (bp->rx_buf_ring == NULL)
406 goto alloc_mem_err;
407
408 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
409 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
410 sizeof(struct rx_bd) *
411 RX_DESC_CNT,
412 &bp->rx_desc_mapping);
413 if (bp->rx_desc_ring == NULL)
414 goto alloc_mem_err;
415
416 bp->status_blk = pci_alloc_consistent(bp->pdev,
417 sizeof(struct status_block),
418 &bp->status_blk_mapping);
419 if (bp->status_blk == NULL)
420 goto alloc_mem_err;
421
422 memset(bp->status_blk, 0, sizeof(struct status_block));
423
424 bp->stats_blk = pci_alloc_consistent(bp->pdev,
425 sizeof(struct statistics_block),
426 &bp->stats_blk_mapping);
427 if (bp->stats_blk == NULL)
428 goto alloc_mem_err;
429
430 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
431
432 return 0;
433
434 alloc_mem_err:
435 bnx2_free_mem(bp);
436 return -ENOMEM;
437 }
438
439 static void
440 bnx2_report_fw_link(struct bnx2 *bp)
441 {
442 u32 fw_link_status = 0;
443
444 if (bp->link_up) {
445 u32 bmsr;
446
447 switch (bp->line_speed) {
448 case SPEED_10:
449 if (bp->duplex == DUPLEX_HALF)
450 fw_link_status = BNX2_LINK_STATUS_10HALF;
451 else
452 fw_link_status = BNX2_LINK_STATUS_10FULL;
453 break;
454 case SPEED_100:
455 if (bp->duplex == DUPLEX_HALF)
456 fw_link_status = BNX2_LINK_STATUS_100HALF;
457 else
458 fw_link_status = BNX2_LINK_STATUS_100FULL;
459 break;
460 case SPEED_1000:
461 if (bp->duplex == DUPLEX_HALF)
462 fw_link_status = BNX2_LINK_STATUS_1000HALF;
463 else
464 fw_link_status = BNX2_LINK_STATUS_1000FULL;
465 break;
466 case SPEED_2500:
467 if (bp->duplex == DUPLEX_HALF)
468 fw_link_status = BNX2_LINK_STATUS_2500HALF;
469 else
470 fw_link_status = BNX2_LINK_STATUS_2500FULL;
471 break;
472 }
473
474 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
475
476 if (bp->autoneg) {
477 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
478
479 bnx2_read_phy(bp, MII_BMSR, &bmsr);
480 bnx2_read_phy(bp, MII_BMSR, &bmsr);
481
482 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
483 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
484 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
485 else
486 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
487 }
488 }
489 else
490 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
491
492 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
493 }
494
495 static void
496 bnx2_report_link(struct bnx2 *bp)
497 {
498 if (bp->link_up) {
499 netif_carrier_on(bp->dev);
500 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
501
502 printk("%d Mbps ", bp->line_speed);
503
504 if (bp->duplex == DUPLEX_FULL)
505 printk("full duplex");
506 else
507 printk("half duplex");
508
509 if (bp->flow_ctrl) {
510 if (bp->flow_ctrl & FLOW_CTRL_RX) {
511 printk(", receive ");
512 if (bp->flow_ctrl & FLOW_CTRL_TX)
513 printk("& transmit ");
514 }
515 else {
516 printk(", transmit ");
517 }
518 printk("flow control ON");
519 }
520 printk("\n");
521 }
522 else {
523 netif_carrier_off(bp->dev);
524 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
525 }
526
527 bnx2_report_fw_link(bp);
528 }
529
530 static void
531 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
532 {
533 u32 local_adv, remote_adv;
534
535 bp->flow_ctrl = 0;
536 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
537 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
538
539 if (bp->duplex == DUPLEX_FULL) {
540 bp->flow_ctrl = bp->req_flow_ctrl;
541 }
542 return;
543 }
544
545 if (bp->duplex != DUPLEX_FULL) {
546 return;
547 }
548
549 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
550 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
551 u32 val;
552
553 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
554 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
555 bp->flow_ctrl |= FLOW_CTRL_TX;
556 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
557 bp->flow_ctrl |= FLOW_CTRL_RX;
558 return;
559 }
560
561 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
562 bnx2_read_phy(bp, MII_LPA, &remote_adv);
563
564 if (bp->phy_flags & PHY_SERDES_FLAG) {
565 u32 new_local_adv = 0;
566 u32 new_remote_adv = 0;
567
568 if (local_adv & ADVERTISE_1000XPAUSE)
569 new_local_adv |= ADVERTISE_PAUSE_CAP;
570 if (local_adv & ADVERTISE_1000XPSE_ASYM)
571 new_local_adv |= ADVERTISE_PAUSE_ASYM;
572 if (remote_adv & ADVERTISE_1000XPAUSE)
573 new_remote_adv |= ADVERTISE_PAUSE_CAP;
574 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
575 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
576
577 local_adv = new_local_adv;
578 remote_adv = new_remote_adv;
579 }
580
581 /* See Table 28B-3 of 802.3ab-1999 spec. */
582 if (local_adv & ADVERTISE_PAUSE_CAP) {
583 if(local_adv & ADVERTISE_PAUSE_ASYM) {
584 if (remote_adv & ADVERTISE_PAUSE_CAP) {
585 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
586 }
587 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
588 bp->flow_ctrl = FLOW_CTRL_RX;
589 }
590 }
591 else {
592 if (remote_adv & ADVERTISE_PAUSE_CAP) {
593 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
594 }
595 }
596 }
597 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
598 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
599 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
600
601 bp->flow_ctrl = FLOW_CTRL_TX;
602 }
603 }
604 }
605
606 static int
607 bnx2_5708s_linkup(struct bnx2 *bp)
608 {
609 u32 val;
610
611 bp->link_up = 1;
612 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
613 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
614 case BCM5708S_1000X_STAT1_SPEED_10:
615 bp->line_speed = SPEED_10;
616 break;
617 case BCM5708S_1000X_STAT1_SPEED_100:
618 bp->line_speed = SPEED_100;
619 break;
620 case BCM5708S_1000X_STAT1_SPEED_1G:
621 bp->line_speed = SPEED_1000;
622 break;
623 case BCM5708S_1000X_STAT1_SPEED_2G5:
624 bp->line_speed = SPEED_2500;
625 break;
626 }
627 if (val & BCM5708S_1000X_STAT1_FD)
628 bp->duplex = DUPLEX_FULL;
629 else
630 bp->duplex = DUPLEX_HALF;
631
632 return 0;
633 }
634
635 static int
636 bnx2_5706s_linkup(struct bnx2 *bp)
637 {
638 u32 bmcr, local_adv, remote_adv, common;
639
640 bp->link_up = 1;
641 bp->line_speed = SPEED_1000;
642
643 bnx2_read_phy(bp, MII_BMCR, &bmcr);
644 if (bmcr & BMCR_FULLDPLX) {
645 bp->duplex = DUPLEX_FULL;
646 }
647 else {
648 bp->duplex = DUPLEX_HALF;
649 }
650
651 if (!(bmcr & BMCR_ANENABLE)) {
652 return 0;
653 }
654
655 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
656 bnx2_read_phy(bp, MII_LPA, &remote_adv);
657
658 common = local_adv & remote_adv;
659 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
660
661 if (common & ADVERTISE_1000XFULL) {
662 bp->duplex = DUPLEX_FULL;
663 }
664 else {
665 bp->duplex = DUPLEX_HALF;
666 }
667 }
668
669 return 0;
670 }
671
672 static int
673 bnx2_copper_linkup(struct bnx2 *bp)
674 {
675 u32 bmcr;
676
677 bnx2_read_phy(bp, MII_BMCR, &bmcr);
678 if (bmcr & BMCR_ANENABLE) {
679 u32 local_adv, remote_adv, common;
680
681 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
682 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
683
684 common = local_adv & (remote_adv >> 2);
685 if (common & ADVERTISE_1000FULL) {
686 bp->line_speed = SPEED_1000;
687 bp->duplex = DUPLEX_FULL;
688 }
689 else if (common & ADVERTISE_1000HALF) {
690 bp->line_speed = SPEED_1000;
691 bp->duplex = DUPLEX_HALF;
692 }
693 else {
694 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
695 bnx2_read_phy(bp, MII_LPA, &remote_adv);
696
697 common = local_adv & remote_adv;
698 if (common & ADVERTISE_100FULL) {
699 bp->line_speed = SPEED_100;
700 bp->duplex = DUPLEX_FULL;
701 }
702 else if (common & ADVERTISE_100HALF) {
703 bp->line_speed = SPEED_100;
704 bp->duplex = DUPLEX_HALF;
705 }
706 else if (common & ADVERTISE_10FULL) {
707 bp->line_speed = SPEED_10;
708 bp->duplex = DUPLEX_FULL;
709 }
710 else if (common & ADVERTISE_10HALF) {
711 bp->line_speed = SPEED_10;
712 bp->duplex = DUPLEX_HALF;
713 }
714 else {
715 bp->line_speed = 0;
716 bp->link_up = 0;
717 }
718 }
719 }
720 else {
721 if (bmcr & BMCR_SPEED100) {
722 bp->line_speed = SPEED_100;
723 }
724 else {
725 bp->line_speed = SPEED_10;
726 }
727 if (bmcr & BMCR_FULLDPLX) {
728 bp->duplex = DUPLEX_FULL;
729 }
730 else {
731 bp->duplex = DUPLEX_HALF;
732 }
733 }
734
735 return 0;
736 }
737
738 static int
739 bnx2_set_mac_link(struct bnx2 *bp)
740 {
741 u32 val;
742
743 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
744 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
745 (bp->duplex == DUPLEX_HALF)) {
746 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
747 }
748
749 /* Configure the EMAC mode register. */
750 val = REG_RD(bp, BNX2_EMAC_MODE);
751
752 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
753 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
754 BNX2_EMAC_MODE_25G);
755
756 if (bp->link_up) {
757 switch (bp->line_speed) {
758 case SPEED_10:
759 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
760 val |= BNX2_EMAC_MODE_PORT_MII_10;
761 break;
762 }
763 /* fall through */
764 case SPEED_100:
765 val |= BNX2_EMAC_MODE_PORT_MII;
766 break;
767 case SPEED_2500:
768 val |= BNX2_EMAC_MODE_25G;
769 /* fall through */
770 case SPEED_1000:
771 val |= BNX2_EMAC_MODE_PORT_GMII;
772 break;
773 }
774 }
775 else {
776 val |= BNX2_EMAC_MODE_PORT_GMII;
777 }
778
779 /* Set the MAC to operate in the appropriate duplex mode. */
780 if (bp->duplex == DUPLEX_HALF)
781 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
782 REG_WR(bp, BNX2_EMAC_MODE, val);
783
784 /* Enable/disable rx PAUSE. */
785 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
786
787 if (bp->flow_ctrl & FLOW_CTRL_RX)
788 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
789 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
790
791 /* Enable/disable tx PAUSE. */
792 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
793 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
794
795 if (bp->flow_ctrl & FLOW_CTRL_TX)
796 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
797 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
798
799 /* Acknowledge the interrupt. */
800 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
801
802 return 0;
803 }
804
805 static int
806 bnx2_set_link(struct bnx2 *bp)
807 {
808 u32 bmsr;
809 u8 link_up;
810
811 if (bp->loopback == MAC_LOOPBACK) {
812 bp->link_up = 1;
813 return 0;
814 }
815
816 link_up = bp->link_up;
817
818 bnx2_read_phy(bp, MII_BMSR, &bmsr);
819 bnx2_read_phy(bp, MII_BMSR, &bmsr);
820
821 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
822 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
823 u32 val;
824
825 val = REG_RD(bp, BNX2_EMAC_STATUS);
826 if (val & BNX2_EMAC_STATUS_LINK)
827 bmsr |= BMSR_LSTATUS;
828 else
829 bmsr &= ~BMSR_LSTATUS;
830 }
831
832 if (bmsr & BMSR_LSTATUS) {
833 bp->link_up = 1;
834
835 if (bp->phy_flags & PHY_SERDES_FLAG) {
836 if (CHIP_NUM(bp) == CHIP_NUM_5706)
837 bnx2_5706s_linkup(bp);
838 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
839 bnx2_5708s_linkup(bp);
840 }
841 else {
842 bnx2_copper_linkup(bp);
843 }
844 bnx2_resolve_flow_ctrl(bp);
845 }
846 else {
847 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
848 (bp->autoneg & AUTONEG_SPEED)) {
849
850 u32 bmcr;
851
852 bnx2_read_phy(bp, MII_BMCR, &bmcr);
853 if (!(bmcr & BMCR_ANENABLE)) {
854 bnx2_write_phy(bp, MII_BMCR, bmcr |
855 BMCR_ANENABLE);
856 }
857 }
858 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
859 bp->link_up = 0;
860 }
861
862 if (bp->link_up != link_up) {
863 bnx2_report_link(bp);
864 }
865
866 bnx2_set_mac_link(bp);
867
868 return 0;
869 }
870
871 static int
872 bnx2_reset_phy(struct bnx2 *bp)
873 {
874 int i;
875 u32 reg;
876
877 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
878
879 #define PHY_RESET_MAX_WAIT 100
880 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
881 udelay(10);
882
883 bnx2_read_phy(bp, MII_BMCR, &reg);
884 if (!(reg & BMCR_RESET)) {
885 udelay(20);
886 break;
887 }
888 }
889 if (i == PHY_RESET_MAX_WAIT) {
890 return -EBUSY;
891 }
892 return 0;
893 }
894
895 static u32
896 bnx2_phy_get_pause_adv(struct bnx2 *bp)
897 {
898 u32 adv = 0;
899
900 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
901 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
902
903 if (bp->phy_flags & PHY_SERDES_FLAG) {
904 adv = ADVERTISE_1000XPAUSE;
905 }
906 else {
907 adv = ADVERTISE_PAUSE_CAP;
908 }
909 }
910 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
911 if (bp->phy_flags & PHY_SERDES_FLAG) {
912 adv = ADVERTISE_1000XPSE_ASYM;
913 }
914 else {
915 adv = ADVERTISE_PAUSE_ASYM;
916 }
917 }
918 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
919 if (bp->phy_flags & PHY_SERDES_FLAG) {
920 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
921 }
922 else {
923 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
924 }
925 }
926 return adv;
927 }
928
929 static int
930 bnx2_setup_serdes_phy(struct bnx2 *bp)
931 {
932 u32 adv, bmcr, up1;
933 u32 new_adv = 0;
934
935 if (!(bp->autoneg & AUTONEG_SPEED)) {
936 u32 new_bmcr;
937 int force_link_down = 0;
938
939 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
940 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
941 if (up1 & BCM5708S_UP1_2G5) {
942 up1 &= ~BCM5708S_UP1_2G5;
943 bnx2_write_phy(bp, BCM5708S_UP1, up1);
944 force_link_down = 1;
945 }
946 }
947
948 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
949 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
950
951 bnx2_read_phy(bp, MII_BMCR, &bmcr);
952 new_bmcr = bmcr & ~BMCR_ANENABLE;
953 new_bmcr |= BMCR_SPEED1000;
954 if (bp->req_duplex == DUPLEX_FULL) {
955 adv |= ADVERTISE_1000XFULL;
956 new_bmcr |= BMCR_FULLDPLX;
957 }
958 else {
959 adv |= ADVERTISE_1000XHALF;
960 new_bmcr &= ~BMCR_FULLDPLX;
961 }
962 if ((new_bmcr != bmcr) || (force_link_down)) {
963 /* Force a link down visible on the other side */
964 if (bp->link_up) {
965 bnx2_write_phy(bp, MII_ADVERTISE, adv &
966 ~(ADVERTISE_1000XFULL |
967 ADVERTISE_1000XHALF));
968 bnx2_write_phy(bp, MII_BMCR, bmcr |
969 BMCR_ANRESTART | BMCR_ANENABLE);
970
971 bp->link_up = 0;
972 netif_carrier_off(bp->dev);
973 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
974 }
975 bnx2_write_phy(bp, MII_ADVERTISE, adv);
976 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
977 }
978 return 0;
979 }
980
981 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
982 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
983 up1 |= BCM5708S_UP1_2G5;
984 bnx2_write_phy(bp, BCM5708S_UP1, up1);
985 }
986
987 if (bp->advertising & ADVERTISED_1000baseT_Full)
988 new_adv |= ADVERTISE_1000XFULL;
989
990 new_adv |= bnx2_phy_get_pause_adv(bp);
991
992 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
993 bnx2_read_phy(bp, MII_BMCR, &bmcr);
994
995 bp->serdes_an_pending = 0;
996 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
997 /* Force a link down visible on the other side */
998 if (bp->link_up) {
999 int i;
1000
1001 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1002 for (i = 0; i < 110; i++) {
1003 udelay(100);
1004 }
1005 }
1006
1007 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1008 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1009 BMCR_ANENABLE);
1010 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1011 /* Speed up link-up time when the link partner
1012 * does not autonegotiate which is very common
1013 * in blade servers. Some blade servers use
1014 * IPMI for kerboard input and it's important
1015 * to minimize link disruptions. Autoneg. involves
1016 * exchanging base pages plus 3 next pages and
1017 * normally completes in about 120 msec.
1018 */
1019 bp->current_interval = SERDES_AN_TIMEOUT;
1020 bp->serdes_an_pending = 1;
1021 mod_timer(&bp->timer, jiffies + bp->current_interval);
1022 }
1023 }
1024
1025 return 0;
1026 }
1027
1028 #define ETHTOOL_ALL_FIBRE_SPEED \
1029 (ADVERTISED_1000baseT_Full)
1030
1031 #define ETHTOOL_ALL_COPPER_SPEED \
1032 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1033 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1034 ADVERTISED_1000baseT_Full)
1035
1036 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1037 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1038
1039 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1040
1041 static int
1042 bnx2_setup_copper_phy(struct bnx2 *bp)
1043 {
1044 u32 bmcr;
1045 u32 new_bmcr;
1046
1047 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1048
1049 if (bp->autoneg & AUTONEG_SPEED) {
1050 u32 adv_reg, adv1000_reg;
1051 u32 new_adv_reg = 0;
1052 u32 new_adv1000_reg = 0;
1053
1054 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1055 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1056 ADVERTISE_PAUSE_ASYM);
1057
1058 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1059 adv1000_reg &= PHY_ALL_1000_SPEED;
1060
1061 if (bp->advertising & ADVERTISED_10baseT_Half)
1062 new_adv_reg |= ADVERTISE_10HALF;
1063 if (bp->advertising & ADVERTISED_10baseT_Full)
1064 new_adv_reg |= ADVERTISE_10FULL;
1065 if (bp->advertising & ADVERTISED_100baseT_Half)
1066 new_adv_reg |= ADVERTISE_100HALF;
1067 if (bp->advertising & ADVERTISED_100baseT_Full)
1068 new_adv_reg |= ADVERTISE_100FULL;
1069 if (bp->advertising & ADVERTISED_1000baseT_Full)
1070 new_adv1000_reg |= ADVERTISE_1000FULL;
1071
1072 new_adv_reg |= ADVERTISE_CSMA;
1073
1074 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1075
1076 if ((adv1000_reg != new_adv1000_reg) ||
1077 (adv_reg != new_adv_reg) ||
1078 ((bmcr & BMCR_ANENABLE) == 0)) {
1079
1080 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1081 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1082 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1083 BMCR_ANENABLE);
1084 }
1085 else if (bp->link_up) {
1086 /* Flow ctrl may have changed from auto to forced */
1087 /* or vice-versa. */
1088
1089 bnx2_resolve_flow_ctrl(bp);
1090 bnx2_set_mac_link(bp);
1091 }
1092 return 0;
1093 }
1094
1095 new_bmcr = 0;
1096 if (bp->req_line_speed == SPEED_100) {
1097 new_bmcr |= BMCR_SPEED100;
1098 }
1099 if (bp->req_duplex == DUPLEX_FULL) {
1100 new_bmcr |= BMCR_FULLDPLX;
1101 }
1102 if (new_bmcr != bmcr) {
1103 u32 bmsr;
1104 int i = 0;
1105
1106 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1107 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1108
1109 if (bmsr & BMSR_LSTATUS) {
1110 /* Force link down */
1111 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1112 do {
1113 udelay(100);
1114 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1115 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1116 i++;
1117 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1118 }
1119
1120 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1121
1122 /* Normally, the new speed is setup after the link has
1123 * gone down and up again. In some cases, link will not go
1124 * down so we need to set up the new speed here.
1125 */
1126 if (bmsr & BMSR_LSTATUS) {
1127 bp->line_speed = bp->req_line_speed;
1128 bp->duplex = bp->req_duplex;
1129 bnx2_resolve_flow_ctrl(bp);
1130 bnx2_set_mac_link(bp);
1131 }
1132 }
1133 return 0;
1134 }
1135
1136 static int
1137 bnx2_setup_phy(struct bnx2 *bp)
1138 {
1139 if (bp->loopback == MAC_LOOPBACK)
1140 return 0;
1141
1142 if (bp->phy_flags & PHY_SERDES_FLAG) {
1143 return (bnx2_setup_serdes_phy(bp));
1144 }
1145 else {
1146 return (bnx2_setup_copper_phy(bp));
1147 }
1148 }
1149
1150 static int
1151 bnx2_init_5708s_phy(struct bnx2 *bp)
1152 {
1153 u32 val;
1154
1155 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1156 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1157 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1158
1159 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1160 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1161 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1162
1163 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1164 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1165 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1166
1167 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1168 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1169 val |= BCM5708S_UP1_2G5;
1170 bnx2_write_phy(bp, BCM5708S_UP1, val);
1171 }
1172
1173 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1174 (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
1175 /* increase tx signal amplitude */
1176 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1177 BCM5708S_BLK_ADDR_TX_MISC);
1178 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1179 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1180 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1181 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1182 }
1183
1184 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1185 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1186
1187 if (val) {
1188 u32 is_backplane;
1189
1190 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1191 BNX2_SHARED_HW_CFG_CONFIG);
1192 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1193 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1194 BCM5708S_BLK_ADDR_TX_MISC);
1195 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1196 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1197 BCM5708S_BLK_ADDR_DIG);
1198 }
1199 }
1200 return 0;
1201 }
1202
1203 static int
1204 bnx2_init_5706s_phy(struct bnx2 *bp)
1205 {
1206 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1207
1208 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1209 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1210 }
1211
1212 if (bp->dev->mtu > 1500) {
1213 u32 val;
1214
1215 /* Set extended packet length bit */
1216 bnx2_write_phy(bp, 0x18, 0x7);
1217 bnx2_read_phy(bp, 0x18, &val);
1218 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1219
1220 bnx2_write_phy(bp, 0x1c, 0x6c00);
1221 bnx2_read_phy(bp, 0x1c, &val);
1222 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1223 }
1224 else {
1225 u32 val;
1226
1227 bnx2_write_phy(bp, 0x18, 0x7);
1228 bnx2_read_phy(bp, 0x18, &val);
1229 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1230
1231 bnx2_write_phy(bp, 0x1c, 0x6c00);
1232 bnx2_read_phy(bp, 0x1c, &val);
1233 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1234 }
1235
1236 return 0;
1237 }
1238
1239 static int
1240 bnx2_init_copper_phy(struct bnx2 *bp)
1241 {
1242 u32 val;
1243
1244 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1245
1246 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1247 bnx2_write_phy(bp, 0x18, 0x0c00);
1248 bnx2_write_phy(bp, 0x17, 0x000a);
1249 bnx2_write_phy(bp, 0x15, 0x310b);
1250 bnx2_write_phy(bp, 0x17, 0x201f);
1251 bnx2_write_phy(bp, 0x15, 0x9506);
1252 bnx2_write_phy(bp, 0x17, 0x401f);
1253 bnx2_write_phy(bp, 0x15, 0x14e2);
1254 bnx2_write_phy(bp, 0x18, 0x0400);
1255 }
1256
1257 if (bp->dev->mtu > 1500) {
1258 /* Set extended packet length bit */
1259 bnx2_write_phy(bp, 0x18, 0x7);
1260 bnx2_read_phy(bp, 0x18, &val);
1261 bnx2_write_phy(bp, 0x18, val | 0x4000);
1262
1263 bnx2_read_phy(bp, 0x10, &val);
1264 bnx2_write_phy(bp, 0x10, val | 0x1);
1265 }
1266 else {
1267 bnx2_write_phy(bp, 0x18, 0x7);
1268 bnx2_read_phy(bp, 0x18, &val);
1269 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1270
1271 bnx2_read_phy(bp, 0x10, &val);
1272 bnx2_write_phy(bp, 0x10, val & ~0x1);
1273 }
1274
1275 /* ethernet@wirespeed */
1276 bnx2_write_phy(bp, 0x18, 0x7007);
1277 bnx2_read_phy(bp, 0x18, &val);
1278 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1279 return 0;
1280 }
1281
1282
1283 static int
1284 bnx2_init_phy(struct bnx2 *bp)
1285 {
1286 u32 val;
1287 int rc = 0;
1288
1289 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1290 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1291
1292 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1293
1294 bnx2_reset_phy(bp);
1295
1296 bnx2_read_phy(bp, MII_PHYSID1, &val);
1297 bp->phy_id = val << 16;
1298 bnx2_read_phy(bp, MII_PHYSID2, &val);
1299 bp->phy_id |= val & 0xffff;
1300
1301 if (bp->phy_flags & PHY_SERDES_FLAG) {
1302 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1303 rc = bnx2_init_5706s_phy(bp);
1304 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1305 rc = bnx2_init_5708s_phy(bp);
1306 }
1307 else {
1308 rc = bnx2_init_copper_phy(bp);
1309 }
1310
1311 bnx2_setup_phy(bp);
1312
1313 return rc;
1314 }
1315
1316 static int
1317 bnx2_set_mac_loopback(struct bnx2 *bp)
1318 {
1319 u32 mac_mode;
1320
1321 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1322 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1323 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1324 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1325 bp->link_up = 1;
1326 return 0;
1327 }
1328
1329 static int
1330 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1331 {
1332 int i;
1333 u32 val;
1334
1335 if (bp->fw_timed_out)
1336 return -EBUSY;
1337
1338 bp->fw_wr_seq++;
1339 msg_data |= bp->fw_wr_seq;
1340
1341 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1342
1343 /* wait for an acknowledgement. */
1344 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1345 udelay(5);
1346
1347 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1348
1349 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1350 break;
1351 }
1352
1353 /* If we timed out, inform the firmware that this is the case. */
1354 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1355 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1356
1357 msg_data &= ~BNX2_DRV_MSG_CODE;
1358 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1359
1360 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1361
1362 bp->fw_timed_out = 1;
1363
1364 return -EBUSY;
1365 }
1366
1367 return 0;
1368 }
1369
1370 static void
1371 bnx2_init_context(struct bnx2 *bp)
1372 {
1373 u32 vcid;
1374
1375 vcid = 96;
1376 while (vcid) {
1377 u32 vcid_addr, pcid_addr, offset;
1378
1379 vcid--;
1380
1381 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1382 u32 new_vcid;
1383
1384 vcid_addr = GET_PCID_ADDR(vcid);
1385 if (vcid & 0x8) {
1386 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1387 }
1388 else {
1389 new_vcid = vcid;
1390 }
1391 pcid_addr = GET_PCID_ADDR(new_vcid);
1392 }
1393 else {
1394 vcid_addr = GET_CID_ADDR(vcid);
1395 pcid_addr = vcid_addr;
1396 }
1397
1398 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1399 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1400
1401 /* Zero out the context. */
1402 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1403 CTX_WR(bp, 0x00, offset, 0);
1404 }
1405
1406 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1407 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1408 }
1409 }
1410
1411 static int
1412 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1413 {
1414 u16 *good_mbuf;
1415 u32 good_mbuf_cnt;
1416 u32 val;
1417
1418 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1419 if (good_mbuf == NULL) {
1420 printk(KERN_ERR PFX "Failed to allocate memory in "
1421 "bnx2_alloc_bad_rbuf\n");
1422 return -ENOMEM;
1423 }
1424
1425 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1426 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1427
1428 good_mbuf_cnt = 0;
1429
1430 /* Allocate a bunch of mbufs and save the good ones in an array. */
1431 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1432 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1433 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1434
1435 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1436
1437 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1438
1439 /* The addresses with Bit 9 set are bad memory blocks. */
1440 if (!(val & (1 << 9))) {
1441 good_mbuf[good_mbuf_cnt] = (u16) val;
1442 good_mbuf_cnt++;
1443 }
1444
1445 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1446 }
1447
1448 /* Free the good ones back to the mbuf pool thus discarding
1449 * all the bad ones. */
1450 while (good_mbuf_cnt) {
1451 good_mbuf_cnt--;
1452
1453 val = good_mbuf[good_mbuf_cnt];
1454 val = (val << 9) | val | 1;
1455
1456 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1457 }
1458 kfree(good_mbuf);
1459 return 0;
1460 }
1461
1462 static void
1463 bnx2_set_mac_addr(struct bnx2 *bp)
1464 {
1465 u32 val;
1466 u8 *mac_addr = bp->dev->dev_addr;
1467
1468 val = (mac_addr[0] << 8) | mac_addr[1];
1469
1470 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1471
1472 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1473 (mac_addr[4] << 8) | mac_addr[5];
1474
1475 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1476 }
1477
1478 static inline int
1479 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1480 {
1481 struct sk_buff *skb;
1482 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1483 dma_addr_t mapping;
1484 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1485 unsigned long align;
1486
1487 skb = dev_alloc_skb(bp->rx_buf_size);
1488 if (skb == NULL) {
1489 return -ENOMEM;
1490 }
1491
1492 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1493 skb_reserve(skb, 8 - align);
1494 }
1495
1496 skb->dev = bp->dev;
1497 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1498 PCI_DMA_FROMDEVICE);
1499
1500 rx_buf->skb = skb;
1501 pci_unmap_addr_set(rx_buf, mapping, mapping);
1502
1503 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1504 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1505
1506 bp->rx_prod_bseq += bp->rx_buf_use_size;
1507
1508 return 0;
1509 }
1510
1511 static void
1512 bnx2_phy_int(struct bnx2 *bp)
1513 {
1514 u32 new_link_state, old_link_state;
1515
1516 new_link_state = bp->status_blk->status_attn_bits &
1517 STATUS_ATTN_BITS_LINK_STATE;
1518 old_link_state = bp->status_blk->status_attn_bits_ack &
1519 STATUS_ATTN_BITS_LINK_STATE;
1520 if (new_link_state != old_link_state) {
1521 if (new_link_state) {
1522 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1523 STATUS_ATTN_BITS_LINK_STATE);
1524 }
1525 else {
1526 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1527 STATUS_ATTN_BITS_LINK_STATE);
1528 }
1529 bnx2_set_link(bp);
1530 }
1531 }
1532
1533 static void
1534 bnx2_tx_int(struct bnx2 *bp)
1535 {
1536 struct status_block *sblk = bp->status_blk;
1537 u16 hw_cons, sw_cons, sw_ring_cons;
1538 int tx_free_bd = 0;
1539
1540 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1541 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1542 hw_cons++;
1543 }
1544 sw_cons = bp->tx_cons;
1545
1546 while (sw_cons != hw_cons) {
1547 struct sw_bd *tx_buf;
1548 struct sk_buff *skb;
1549 int i, last;
1550
1551 sw_ring_cons = TX_RING_IDX(sw_cons);
1552
1553 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1554 skb = tx_buf->skb;
1555 #ifdef BCM_TSO
1556 /* partial BD completions possible with TSO packets */
1557 if (skb_shinfo(skb)->tso_size) {
1558 u16 last_idx, last_ring_idx;
1559
1560 last_idx = sw_cons +
1561 skb_shinfo(skb)->nr_frags + 1;
1562 last_ring_idx = sw_ring_cons +
1563 skb_shinfo(skb)->nr_frags + 1;
1564 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1565 last_idx++;
1566 }
1567 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1568 break;
1569 }
1570 }
1571 #endif
1572 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1573 skb_headlen(skb), PCI_DMA_TODEVICE);
1574
1575 tx_buf->skb = NULL;
1576 last = skb_shinfo(skb)->nr_frags;
1577
1578 for (i = 0; i < last; i++) {
1579 sw_cons = NEXT_TX_BD(sw_cons);
1580
1581 pci_unmap_page(bp->pdev,
1582 pci_unmap_addr(
1583 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1584 mapping),
1585 skb_shinfo(skb)->frags[i].size,
1586 PCI_DMA_TODEVICE);
1587 }
1588
1589 sw_cons = NEXT_TX_BD(sw_cons);
1590
1591 tx_free_bd += last + 1;
1592
1593 dev_kfree_skb_irq(skb);
1594
1595 hw_cons = bp->hw_tx_cons =
1596 sblk->status_tx_quick_consumer_index0;
1597
1598 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1599 hw_cons++;
1600 }
1601 }
1602
1603 bp->tx_cons = sw_cons;
1604
1605 if (unlikely(netif_queue_stopped(bp->dev))) {
1606 spin_lock(&bp->tx_lock);
1607 if ((netif_queue_stopped(bp->dev)) &&
1608 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1609
1610 netif_wake_queue(bp->dev);
1611 }
1612 spin_unlock(&bp->tx_lock);
1613 }
1614 }
1615
1616 static inline void
1617 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1618 u16 cons, u16 prod)
1619 {
1620 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1621 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1622 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1623 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1624
1625 pci_dma_sync_single_for_device(bp->pdev,
1626 pci_unmap_addr(cons_rx_buf, mapping),
1627 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1628
1629 prod_rx_buf->skb = cons_rx_buf->skb;
1630 pci_unmap_addr_set(prod_rx_buf, mapping,
1631 pci_unmap_addr(cons_rx_buf, mapping));
1632
1633 memcpy(prod_bd, cons_bd, 8);
1634
1635 bp->rx_prod_bseq += bp->rx_buf_use_size;
1636
1637 }
1638
1639 static int
1640 bnx2_rx_int(struct bnx2 *bp, int budget)
1641 {
1642 struct status_block *sblk = bp->status_blk;
1643 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1644 struct l2_fhdr *rx_hdr;
1645 int rx_pkt = 0;
1646
1647 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1648 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1649 hw_cons++;
1650 }
1651 sw_cons = bp->rx_cons;
1652 sw_prod = bp->rx_prod;
1653
1654 /* Memory barrier necessary as speculative reads of the rx
1655 * buffer can be ahead of the index in the status block
1656 */
1657 rmb();
1658 while (sw_cons != hw_cons) {
1659 unsigned int len;
1660 u16 status;
1661 struct sw_bd *rx_buf;
1662 struct sk_buff *skb;
1663
1664 sw_ring_cons = RX_RING_IDX(sw_cons);
1665 sw_ring_prod = RX_RING_IDX(sw_prod);
1666
1667 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1668 skb = rx_buf->skb;
1669 pci_dma_sync_single_for_cpu(bp->pdev,
1670 pci_unmap_addr(rx_buf, mapping),
1671 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1672
1673 rx_hdr = (struct l2_fhdr *) skb->data;
1674 len = rx_hdr->l2_fhdr_pkt_len - 4;
1675
1676 if (rx_hdr->l2_fhdr_errors &
1677 (L2_FHDR_ERRORS_BAD_CRC |
1678 L2_FHDR_ERRORS_PHY_DECODE |
1679 L2_FHDR_ERRORS_ALIGNMENT |
1680 L2_FHDR_ERRORS_TOO_SHORT |
1681 L2_FHDR_ERRORS_GIANT_FRAME)) {
1682
1683 goto reuse_rx;
1684 }
1685
1686 /* Since we don't have a jumbo ring, copy small packets
1687 * if mtu > 1500
1688 */
1689 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1690 struct sk_buff *new_skb;
1691
1692 new_skb = dev_alloc_skb(len + 2);
1693 if (new_skb == NULL)
1694 goto reuse_rx;
1695
1696 /* aligned copy */
1697 memcpy(new_skb->data,
1698 skb->data + bp->rx_offset - 2,
1699 len + 2);
1700
1701 skb_reserve(new_skb, 2);
1702 skb_put(new_skb, len);
1703 new_skb->dev = bp->dev;
1704
1705 bnx2_reuse_rx_skb(bp, skb,
1706 sw_ring_cons, sw_ring_prod);
1707
1708 skb = new_skb;
1709 }
1710 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1711 pci_unmap_single(bp->pdev,
1712 pci_unmap_addr(rx_buf, mapping),
1713 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1714
1715 skb_reserve(skb, bp->rx_offset);
1716 skb_put(skb, len);
1717 }
1718 else {
1719 reuse_rx:
1720 bnx2_reuse_rx_skb(bp, skb,
1721 sw_ring_cons, sw_ring_prod);
1722 goto next_rx;
1723 }
1724
1725 skb->protocol = eth_type_trans(skb, bp->dev);
1726
1727 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1728 (htons(skb->protocol) != 0x8100)) {
1729
1730 dev_kfree_skb_irq(skb);
1731 goto next_rx;
1732
1733 }
1734
1735 status = rx_hdr->l2_fhdr_status;
1736 skb->ip_summed = CHECKSUM_NONE;
1737 if (bp->rx_csum &&
1738 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1739 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1740
1741 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1742
1743 if (cksum == 0xffff)
1744 skb->ip_summed = CHECKSUM_UNNECESSARY;
1745 }
1746
1747 #ifdef BCM_VLAN
1748 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1749 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1750 rx_hdr->l2_fhdr_vlan_tag);
1751 }
1752 else
1753 #endif
1754 netif_receive_skb(skb);
1755
1756 bp->dev->last_rx = jiffies;
1757 rx_pkt++;
1758
1759 next_rx:
1760 rx_buf->skb = NULL;
1761
1762 sw_cons = NEXT_RX_BD(sw_cons);
1763 sw_prod = NEXT_RX_BD(sw_prod);
1764
1765 if ((rx_pkt == budget))
1766 break;
1767
1768 /* Refresh hw_cons to see if there is new work */
1769 if (sw_cons == hw_cons) {
1770 hw_cons = bp->hw_rx_cons =
1771 sblk->status_rx_quick_consumer_index0;
1772 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1773 hw_cons++;
1774 rmb();
1775 }
1776 }
1777 bp->rx_cons = sw_cons;
1778 bp->rx_prod = sw_prod;
1779
1780 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1781
1782 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1783
1784 mmiowb();
1785
1786 return rx_pkt;
1787
1788 }
1789
1790 /* MSI ISR - The only difference between this and the INTx ISR
1791 * is that the MSI interrupt is always serviced.
1792 */
1793 static irqreturn_t
1794 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1795 {
1796 struct net_device *dev = dev_instance;
1797 struct bnx2 *bp = dev->priv;
1798
1799 prefetch(bp->status_blk);
1800 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1801 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1802 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1803
1804 /* Return here if interrupt is disabled. */
1805 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1806 return IRQ_HANDLED;
1807
1808 netif_rx_schedule(dev);
1809
1810 return IRQ_HANDLED;
1811 }
1812
1813 static irqreturn_t
1814 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1815 {
1816 struct net_device *dev = dev_instance;
1817 struct bnx2 *bp = dev->priv;
1818
1819 /* When using INTx, it is possible for the interrupt to arrive
1820 * at the CPU before the status block posted prior to the
1821 * interrupt. Reading a register will flush the status block.
1822 * When using MSI, the MSI message will always complete after
1823 * the status block write.
1824 */
1825 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1826 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1827 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1828 return IRQ_NONE;
1829
1830 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1831 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1832 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1833
1834 /* Return here if interrupt is shared and is disabled. */
1835 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1836 return IRQ_HANDLED;
1837
1838 netif_rx_schedule(dev);
1839
1840 return IRQ_HANDLED;
1841 }
1842
1843 static inline int
1844 bnx2_has_work(struct bnx2 *bp)
1845 {
1846 struct status_block *sblk = bp->status_blk;
1847
1848 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1849 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1850 return 1;
1851
1852 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1853 bp->link_up)
1854 return 1;
1855
1856 return 0;
1857 }
1858
1859 static int
1860 bnx2_poll(struct net_device *dev, int *budget)
1861 {
1862 struct bnx2 *bp = dev->priv;
1863
1864 if ((bp->status_blk->status_attn_bits &
1865 STATUS_ATTN_BITS_LINK_STATE) !=
1866 (bp->status_blk->status_attn_bits_ack &
1867 STATUS_ATTN_BITS_LINK_STATE)) {
1868
1869 spin_lock(&bp->phy_lock);
1870 bnx2_phy_int(bp);
1871 spin_unlock(&bp->phy_lock);
1872 }
1873
1874 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1875 bnx2_tx_int(bp);
1876
1877 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1878 int orig_budget = *budget;
1879 int work_done;
1880
1881 if (orig_budget > dev->quota)
1882 orig_budget = dev->quota;
1883
1884 work_done = bnx2_rx_int(bp, orig_budget);
1885 *budget -= work_done;
1886 dev->quota -= work_done;
1887 }
1888
1889 bp->last_status_idx = bp->status_blk->status_idx;
1890 rmb();
1891
1892 if (!bnx2_has_work(bp)) {
1893 netif_rx_complete(dev);
1894 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1895 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1896 bp->last_status_idx);
1897 return 0;
1898 }
1899
1900 return 1;
1901 }
1902
1903 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1904 * from set_multicast.
1905 */
1906 static void
1907 bnx2_set_rx_mode(struct net_device *dev)
1908 {
1909 struct bnx2 *bp = dev->priv;
1910 u32 rx_mode, sort_mode;
1911 int i;
1912
1913 spin_lock_bh(&bp->phy_lock);
1914
1915 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1916 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1917 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1918 #ifdef BCM_VLAN
1919 if (!bp->vlgrp) {
1920 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1921 }
1922 #else
1923 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1924 #endif
1925 if (dev->flags & IFF_PROMISC) {
1926 /* Promiscuous mode. */
1927 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1928 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1929 }
1930 else if (dev->flags & IFF_ALLMULTI) {
1931 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1932 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1933 0xffffffff);
1934 }
1935 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1936 }
1937 else {
1938 /* Accept one or more multicast(s). */
1939 struct dev_mc_list *mclist;
1940 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1941 u32 regidx;
1942 u32 bit;
1943 u32 crc;
1944
1945 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1946
1947 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1948 i++, mclist = mclist->next) {
1949
1950 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1951 bit = crc & 0xff;
1952 regidx = (bit & 0xe0) >> 5;
1953 bit &= 0x1f;
1954 mc_filter[regidx] |= (1 << bit);
1955 }
1956
1957 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1958 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1959 mc_filter[i]);
1960 }
1961
1962 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1963 }
1964
1965 if (rx_mode != bp->rx_mode) {
1966 bp->rx_mode = rx_mode;
1967 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1968 }
1969
1970 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1971 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1972 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1973
1974 spin_unlock_bh(&bp->phy_lock);
1975 }
1976
1977 static void
1978 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1979 u32 rv2p_proc)
1980 {
1981 int i;
1982 u32 val;
1983
1984
1985 for (i = 0; i < rv2p_code_len; i += 8) {
1986 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1987 rv2p_code++;
1988 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1989 rv2p_code++;
1990
1991 if (rv2p_proc == RV2P_PROC1) {
1992 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1993 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1994 }
1995 else {
1996 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1997 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1998 }
1999 }
2000
2001 /* Reset the processor, un-stall is done later. */
2002 if (rv2p_proc == RV2P_PROC1) {
2003 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2004 }
2005 else {
2006 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2007 }
2008 }
2009
2010 static void
2011 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2012 {
2013 u32 offset;
2014 u32 val;
2015
2016 /* Halt the CPU. */
2017 val = REG_RD_IND(bp, cpu_reg->mode);
2018 val |= cpu_reg->mode_value_halt;
2019 REG_WR_IND(bp, cpu_reg->mode, val);
2020 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2021
2022 /* Load the Text area. */
2023 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2024 if (fw->text) {
2025 int j;
2026
2027 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2028 REG_WR_IND(bp, offset, fw->text[j]);
2029 }
2030 }
2031
2032 /* Load the Data area. */
2033 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2034 if (fw->data) {
2035 int j;
2036
2037 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2038 REG_WR_IND(bp, offset, fw->data[j]);
2039 }
2040 }
2041
2042 /* Load the SBSS area. */
2043 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2044 if (fw->sbss) {
2045 int j;
2046
2047 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2048 REG_WR_IND(bp, offset, fw->sbss[j]);
2049 }
2050 }
2051
2052 /* Load the BSS area. */
2053 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2054 if (fw->bss) {
2055 int j;
2056
2057 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2058 REG_WR_IND(bp, offset, fw->bss[j]);
2059 }
2060 }
2061
2062 /* Load the Read-Only area. */
2063 offset = cpu_reg->spad_base +
2064 (fw->rodata_addr - cpu_reg->mips_view_base);
2065 if (fw->rodata) {
2066 int j;
2067
2068 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2069 REG_WR_IND(bp, offset, fw->rodata[j]);
2070 }
2071 }
2072
2073 /* Clear the pre-fetch instruction. */
2074 REG_WR_IND(bp, cpu_reg->inst, 0);
2075 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2076
2077 /* Start the CPU. */
2078 val = REG_RD_IND(bp, cpu_reg->mode);
2079 val &= ~cpu_reg->mode_value_halt;
2080 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2081 REG_WR_IND(bp, cpu_reg->mode, val);
2082 }
2083
2084 static void
2085 bnx2_init_cpus(struct bnx2 *bp)
2086 {
2087 struct cpu_reg cpu_reg;
2088 struct fw_info fw;
2089
2090 /* Initialize the RV2P processor. */
2091 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
2092 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
2093
2094 /* Initialize the RX Processor. */
2095 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2096 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2097 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2098 cpu_reg.state = BNX2_RXP_CPU_STATE;
2099 cpu_reg.state_value_clear = 0xffffff;
2100 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2101 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2102 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2103 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2104 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2105 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2106 cpu_reg.mips_view_base = 0x8000000;
2107
2108 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2109 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2110 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2111 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2112
2113 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2114 fw.text_len = bnx2_RXP_b06FwTextLen;
2115 fw.text_index = 0;
2116 fw.text = bnx2_RXP_b06FwText;
2117
2118 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2119 fw.data_len = bnx2_RXP_b06FwDataLen;
2120 fw.data_index = 0;
2121 fw.data = bnx2_RXP_b06FwData;
2122
2123 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2124 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2125 fw.sbss_index = 0;
2126 fw.sbss = bnx2_RXP_b06FwSbss;
2127
2128 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2129 fw.bss_len = bnx2_RXP_b06FwBssLen;
2130 fw.bss_index = 0;
2131 fw.bss = bnx2_RXP_b06FwBss;
2132
2133 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2134 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2135 fw.rodata_index = 0;
2136 fw.rodata = bnx2_RXP_b06FwRodata;
2137
2138 load_cpu_fw(bp, &cpu_reg, &fw);
2139
2140 /* Initialize the TX Processor. */
2141 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2142 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2143 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2144 cpu_reg.state = BNX2_TXP_CPU_STATE;
2145 cpu_reg.state_value_clear = 0xffffff;
2146 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2147 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2148 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2149 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2150 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2151 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2152 cpu_reg.mips_view_base = 0x8000000;
2153
2154 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2155 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2156 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2157 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2158
2159 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2160 fw.text_len = bnx2_TXP_b06FwTextLen;
2161 fw.text_index = 0;
2162 fw.text = bnx2_TXP_b06FwText;
2163
2164 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2165 fw.data_len = bnx2_TXP_b06FwDataLen;
2166 fw.data_index = 0;
2167 fw.data = bnx2_TXP_b06FwData;
2168
2169 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2170 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2171 fw.sbss_index = 0;
2172 fw.sbss = bnx2_TXP_b06FwSbss;
2173
2174 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2175 fw.bss_len = bnx2_TXP_b06FwBssLen;
2176 fw.bss_index = 0;
2177 fw.bss = bnx2_TXP_b06FwBss;
2178
2179 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2180 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2181 fw.rodata_index = 0;
2182 fw.rodata = bnx2_TXP_b06FwRodata;
2183
2184 load_cpu_fw(bp, &cpu_reg, &fw);
2185
2186 /* Initialize the TX Patch-up Processor. */
2187 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2188 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2189 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2190 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2191 cpu_reg.state_value_clear = 0xffffff;
2192 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2193 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2194 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2195 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2196 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2197 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2198 cpu_reg.mips_view_base = 0x8000000;
2199
2200 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2201 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2202 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2203 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2204
2205 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2206 fw.text_len = bnx2_TPAT_b06FwTextLen;
2207 fw.text_index = 0;
2208 fw.text = bnx2_TPAT_b06FwText;
2209
2210 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2211 fw.data_len = bnx2_TPAT_b06FwDataLen;
2212 fw.data_index = 0;
2213 fw.data = bnx2_TPAT_b06FwData;
2214
2215 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2216 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2217 fw.sbss_index = 0;
2218 fw.sbss = bnx2_TPAT_b06FwSbss;
2219
2220 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2221 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2222 fw.bss_index = 0;
2223 fw.bss = bnx2_TPAT_b06FwBss;
2224
2225 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2226 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2227 fw.rodata_index = 0;
2228 fw.rodata = bnx2_TPAT_b06FwRodata;
2229
2230 load_cpu_fw(bp, &cpu_reg, &fw);
2231
2232 /* Initialize the Completion Processor. */
2233 cpu_reg.mode = BNX2_COM_CPU_MODE;
2234 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2235 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2236 cpu_reg.state = BNX2_COM_CPU_STATE;
2237 cpu_reg.state_value_clear = 0xffffff;
2238 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2239 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2240 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2241 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2242 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2243 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2244 cpu_reg.mips_view_base = 0x8000000;
2245
2246 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2247 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2248 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2249 fw.start_addr = bnx2_COM_b06FwStartAddr;
2250
2251 fw.text_addr = bnx2_COM_b06FwTextAddr;
2252 fw.text_len = bnx2_COM_b06FwTextLen;
2253 fw.text_index = 0;
2254 fw.text = bnx2_COM_b06FwText;
2255
2256 fw.data_addr = bnx2_COM_b06FwDataAddr;
2257 fw.data_len = bnx2_COM_b06FwDataLen;
2258 fw.data_index = 0;
2259 fw.data = bnx2_COM_b06FwData;
2260
2261 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2262 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2263 fw.sbss_index = 0;
2264 fw.sbss = bnx2_COM_b06FwSbss;
2265
2266 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2267 fw.bss_len = bnx2_COM_b06FwBssLen;
2268 fw.bss_index = 0;
2269 fw.bss = bnx2_COM_b06FwBss;
2270
2271 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2272 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2273 fw.rodata_index = 0;
2274 fw.rodata = bnx2_COM_b06FwRodata;
2275
2276 load_cpu_fw(bp, &cpu_reg, &fw);
2277
2278 }
2279
2280 static int
2281 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2282 {
2283 u16 pmcsr;
2284
2285 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2286
2287 switch (state) {
2288 case PCI_D0: {
2289 u32 val;
2290
2291 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2292 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2293 PCI_PM_CTRL_PME_STATUS);
2294
2295 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2296 /* delay required during transition out of D3hot */
2297 msleep(20);
2298
2299 val = REG_RD(bp, BNX2_EMAC_MODE);
2300 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2301 val &= ~BNX2_EMAC_MODE_MPKT;
2302 REG_WR(bp, BNX2_EMAC_MODE, val);
2303
2304 val = REG_RD(bp, BNX2_RPM_CONFIG);
2305 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2306 REG_WR(bp, BNX2_RPM_CONFIG, val);
2307 break;
2308 }
2309 case PCI_D3hot: {
2310 int i;
2311 u32 val, wol_msg;
2312
2313 if (bp->wol) {
2314 u32 advertising;
2315 u8 autoneg;
2316
2317 autoneg = bp->autoneg;
2318 advertising = bp->advertising;
2319
2320 bp->autoneg = AUTONEG_SPEED;
2321 bp->advertising = ADVERTISED_10baseT_Half |
2322 ADVERTISED_10baseT_Full |
2323 ADVERTISED_100baseT_Half |
2324 ADVERTISED_100baseT_Full |
2325 ADVERTISED_Autoneg;
2326
2327 bnx2_setup_copper_phy(bp);
2328
2329 bp->autoneg = autoneg;
2330 bp->advertising = advertising;
2331
2332 bnx2_set_mac_addr(bp);
2333
2334 val = REG_RD(bp, BNX2_EMAC_MODE);
2335
2336 /* Enable port mode. */
2337 val &= ~BNX2_EMAC_MODE_PORT;
2338 val |= BNX2_EMAC_MODE_PORT_MII |
2339 BNX2_EMAC_MODE_MPKT_RCVD |
2340 BNX2_EMAC_MODE_ACPI_RCVD |
2341 BNX2_EMAC_MODE_FORCE_LINK |
2342 BNX2_EMAC_MODE_MPKT;
2343
2344 REG_WR(bp, BNX2_EMAC_MODE, val);
2345
2346 /* receive all multicast */
2347 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2348 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2349 0xffffffff);
2350 }
2351 REG_WR(bp, BNX2_EMAC_RX_MODE,
2352 BNX2_EMAC_RX_MODE_SORT_MODE);
2353
2354 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2355 BNX2_RPM_SORT_USER0_MC_EN;
2356 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2357 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2358 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2359 BNX2_RPM_SORT_USER0_ENA);
2360
2361 /* Need to enable EMAC and RPM for WOL. */
2362 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2363 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2364 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2365 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2366
2367 val = REG_RD(bp, BNX2_RPM_CONFIG);
2368 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2369 REG_WR(bp, BNX2_RPM_CONFIG, val);
2370
2371 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2372 }
2373 else {
2374 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2375 }
2376
2377 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2378
2379 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2380 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2381 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2382
2383 if (bp->wol)
2384 pmcsr |= 3;
2385 }
2386 else {
2387 pmcsr |= 3;
2388 }
2389 if (bp->wol) {
2390 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2391 }
2392 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2393 pmcsr);
2394
2395 /* No more memory access after this point until
2396 * device is brought back to D0.
2397 */
2398 udelay(50);
2399 break;
2400 }
2401 default:
2402 return -EINVAL;
2403 }
2404 return 0;
2405 }
2406
2407 static int
2408 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2409 {
2410 u32 val;
2411 int j;
2412
2413 /* Request access to the flash interface. */
2414 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2415 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2416 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2417 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2418 break;
2419
2420 udelay(5);
2421 }
2422
2423 if (j >= NVRAM_TIMEOUT_COUNT)
2424 return -EBUSY;
2425
2426 return 0;
2427 }
2428
2429 static int
2430 bnx2_release_nvram_lock(struct bnx2 *bp)
2431 {
2432 int j;
2433 u32 val;
2434
2435 /* Relinquish nvram interface. */
2436 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2437
2438 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2439 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2440 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2441 break;
2442
2443 udelay(5);
2444 }
2445
2446 if (j >= NVRAM_TIMEOUT_COUNT)
2447 return -EBUSY;
2448
2449 return 0;
2450 }
2451
2452
2453 static int
2454 bnx2_enable_nvram_write(struct bnx2 *bp)
2455 {
2456 u32 val;
2457
2458 val = REG_RD(bp, BNX2_MISC_CFG);
2459 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2460
2461 if (!bp->flash_info->buffered) {
2462 int j;
2463
2464 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2465 REG_WR(bp, BNX2_NVM_COMMAND,
2466 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2467
2468 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2469 udelay(5);
2470
2471 val = REG_RD(bp, BNX2_NVM_COMMAND);
2472 if (val & BNX2_NVM_COMMAND_DONE)
2473 break;
2474 }
2475
2476 if (j >= NVRAM_TIMEOUT_COUNT)
2477 return -EBUSY;
2478 }
2479 return 0;
2480 }
2481
2482 static void
2483 bnx2_disable_nvram_write(struct bnx2 *bp)
2484 {
2485 u32 val;
2486
2487 val = REG_RD(bp, BNX2_MISC_CFG);
2488 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2489 }
2490
2491
2492 static void
2493 bnx2_enable_nvram_access(struct bnx2 *bp)
2494 {
2495 u32 val;
2496
2497 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2498 /* Enable both bits, even on read. */
2499 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2500 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2501 }
2502
2503 static void
2504 bnx2_disable_nvram_access(struct bnx2 *bp)
2505 {
2506 u32 val;
2507
2508 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2509 /* Disable both bits, even after read. */
2510 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2511 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2512 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2513 }
2514
2515 static int
2516 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2517 {
2518 u32 cmd;
2519 int j;
2520
2521 if (bp->flash_info->buffered)
2522 /* Buffered flash, no erase needed */
2523 return 0;
2524
2525 /* Build an erase command */
2526 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2527 BNX2_NVM_COMMAND_DOIT;
2528
2529 /* Need to clear DONE bit separately. */
2530 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2531
2532 /* Address of the NVRAM to read from. */
2533 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2534
2535 /* Issue an erase command. */
2536 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2537
2538 /* Wait for completion. */
2539 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2540 u32 val;
2541
2542 udelay(5);
2543
2544 val = REG_RD(bp, BNX2_NVM_COMMAND);
2545 if (val & BNX2_NVM_COMMAND_DONE)
2546 break;
2547 }
2548
2549 if (j >= NVRAM_TIMEOUT_COUNT)
2550 return -EBUSY;
2551
2552 return 0;
2553 }
2554
2555 static int
2556 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2557 {
2558 u32 cmd;
2559 int j;
2560
2561 /* Build the command word. */
2562 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2563
2564 /* Calculate an offset of a buffered flash. */
2565 if (bp->flash_info->buffered) {
2566 offset = ((offset / bp->flash_info->page_size) <<
2567 bp->flash_info->page_bits) +
2568 (offset % bp->flash_info->page_size);
2569 }
2570
2571 /* Need to clear DONE bit separately. */
2572 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2573
2574 /* Address of the NVRAM to read from. */
2575 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2576
2577 /* Issue a read command. */
2578 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2579
2580 /* Wait for completion. */
2581 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2582 u32 val;
2583
2584 udelay(5);
2585
2586 val = REG_RD(bp, BNX2_NVM_COMMAND);
2587 if (val & BNX2_NVM_COMMAND_DONE) {
2588 val = REG_RD(bp, BNX2_NVM_READ);
2589
2590 val = be32_to_cpu(val);
2591 memcpy(ret_val, &val, 4);
2592 break;
2593 }
2594 }
2595 if (j >= NVRAM_TIMEOUT_COUNT)
2596 return -EBUSY;
2597
2598 return 0;
2599 }
2600
2601
2602 static int
2603 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2604 {
2605 u32 cmd, val32;
2606 int j;
2607
2608 /* Build the command word. */
2609 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2610
2611 /* Calculate an offset of a buffered flash. */
2612 if (bp->flash_info->buffered) {
2613 offset = ((offset / bp->flash_info->page_size) <<
2614 bp->flash_info->page_bits) +
2615 (offset % bp->flash_info->page_size);
2616 }
2617
2618 /* Need to clear DONE bit separately. */
2619 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2620
2621 memcpy(&val32, val, 4);
2622 val32 = cpu_to_be32(val32);
2623
2624 /* Write the data. */
2625 REG_WR(bp, BNX2_NVM_WRITE, val32);
2626
2627 /* Address of the NVRAM to write to. */
2628 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2629
2630 /* Issue the write command. */
2631 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2632
2633 /* Wait for completion. */
2634 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2635 udelay(5);
2636
2637 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2638 break;
2639 }
2640 if (j >= NVRAM_TIMEOUT_COUNT)
2641 return -EBUSY;
2642
2643 return 0;
2644 }
2645
2646 static int
2647 bnx2_init_nvram(struct bnx2 *bp)
2648 {
2649 u32 val;
2650 int j, entry_count, rc;
2651 struct flash_spec *flash;
2652
2653 /* Determine the selected interface. */
2654 val = REG_RD(bp, BNX2_NVM_CFG1);
2655
2656 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2657
2658 rc = 0;
2659 if (val & 0x40000000) {
2660
2661 /* Flash interface has been reconfigured */
2662 for (j = 0, flash = &flash_table[0]; j < entry_count;
2663 j++, flash++) {
2664 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2665 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2666 bp->flash_info = flash;
2667 break;
2668 }
2669 }
2670 }
2671 else {
2672 u32 mask;
2673 /* Not yet been reconfigured */
2674
2675 if (val & (1 << 23))
2676 mask = FLASH_BACKUP_STRAP_MASK;
2677 else
2678 mask = FLASH_STRAP_MASK;
2679
2680 for (j = 0, flash = &flash_table[0]; j < entry_count;
2681 j++, flash++) {
2682
2683 if ((val & mask) == (flash->strapping & mask)) {
2684 bp->flash_info = flash;
2685
2686 /* Request access to the flash interface. */
2687 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2688 return rc;
2689
2690 /* Enable access to flash interface */
2691 bnx2_enable_nvram_access(bp);
2692
2693 /* Reconfigure the flash interface */
2694 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2695 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2696 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2697 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2698
2699 /* Disable access to flash interface */
2700 bnx2_disable_nvram_access(bp);
2701 bnx2_release_nvram_lock(bp);
2702
2703 break;
2704 }
2705 }
2706 } /* if (val & 0x40000000) */
2707
2708 if (j == entry_count) {
2709 bp->flash_info = NULL;
2710 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2711 rc = -ENODEV;
2712 }
2713
2714 return rc;
2715 }
2716
2717 static int
2718 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2719 int buf_size)
2720 {
2721 int rc = 0;
2722 u32 cmd_flags, offset32, len32, extra;
2723
2724 if (buf_size == 0)
2725 return 0;
2726
2727 /* Request access to the flash interface. */
2728 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2729 return rc;
2730
2731 /* Enable access to flash interface */
2732 bnx2_enable_nvram_access(bp);
2733
2734 len32 = buf_size;
2735 offset32 = offset;
2736 extra = 0;
2737
2738 cmd_flags = 0;
2739
2740 if (offset32 & 3) {
2741 u8 buf[4];
2742 u32 pre_len;
2743
2744 offset32 &= ~3;
2745 pre_len = 4 - (offset & 3);
2746
2747 if (pre_len >= len32) {
2748 pre_len = len32;
2749 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2750 BNX2_NVM_COMMAND_LAST;
2751 }
2752 else {
2753 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2754 }
2755
2756 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2757
2758 if (rc)
2759 return rc;
2760
2761 memcpy(ret_buf, buf + (offset & 3), pre_len);
2762
2763 offset32 += 4;
2764 ret_buf += pre_len;
2765 len32 -= pre_len;
2766 }
2767 if (len32 & 3) {
2768 extra = 4 - (len32 & 3);
2769 len32 = (len32 + 4) & ~3;
2770 }
2771
2772 if (len32 == 4) {
2773 u8 buf[4];
2774
2775 if (cmd_flags)
2776 cmd_flags = BNX2_NVM_COMMAND_LAST;
2777 else
2778 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2779 BNX2_NVM_COMMAND_LAST;
2780
2781 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2782
2783 memcpy(ret_buf, buf, 4 - extra);
2784 }
2785 else if (len32 > 0) {
2786 u8 buf[4];
2787
2788 /* Read the first word. */
2789 if (cmd_flags)
2790 cmd_flags = 0;
2791 else
2792 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2793
2794 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2795
2796 /* Advance to the next dword. */
2797 offset32 += 4;
2798 ret_buf += 4;
2799 len32 -= 4;
2800
2801 while (len32 > 4 && rc == 0) {
2802 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2803
2804 /* Advance to the next dword. */
2805 offset32 += 4;
2806 ret_buf += 4;
2807 len32 -= 4;
2808 }
2809
2810 if (rc)
2811 return rc;
2812
2813 cmd_flags = BNX2_NVM_COMMAND_LAST;
2814 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2815
2816 memcpy(ret_buf, buf, 4 - extra);
2817 }
2818
2819 /* Disable access to flash interface */
2820 bnx2_disable_nvram_access(bp);
2821
2822 bnx2_release_nvram_lock(bp);
2823
2824 return rc;
2825 }
2826
2827 static int
2828 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2829 int buf_size)
2830 {
2831 u32 written, offset32, len32;
2832 u8 *buf, start[4], end[4];
2833 int rc = 0;
2834 int align_start, align_end;
2835
2836 buf = data_buf;
2837 offset32 = offset;
2838 len32 = buf_size;
2839 align_start = align_end = 0;
2840
2841 if ((align_start = (offset32 & 3))) {
2842 offset32 &= ~3;
2843 len32 += align_start;
2844 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2845 return rc;
2846 }
2847
2848 if (len32 & 3) {
2849 if ((len32 > 4) || !align_start) {
2850 align_end = 4 - (len32 & 3);
2851 len32 += align_end;
2852 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2853 end, 4))) {
2854 return rc;
2855 }
2856 }
2857 }
2858
2859 if (align_start || align_end) {
2860 buf = kmalloc(len32, GFP_KERNEL);
2861 if (buf == 0)
2862 return -ENOMEM;
2863 if (align_start) {
2864 memcpy(buf, start, 4);
2865 }
2866 if (align_end) {
2867 memcpy(buf + len32 - 4, end, 4);
2868 }
2869 memcpy(buf + align_start, data_buf, buf_size);
2870 }
2871
2872 written = 0;
2873 while ((written < len32) && (rc == 0)) {
2874 u32 page_start, page_end, data_start, data_end;
2875 u32 addr, cmd_flags;
2876 int i;
2877 u8 flash_buffer[264];
2878
2879 /* Find the page_start addr */
2880 page_start = offset32 + written;
2881 page_start -= (page_start % bp->flash_info->page_size);
2882 /* Find the page_end addr */
2883 page_end = page_start + bp->flash_info->page_size;
2884 /* Find the data_start addr */
2885 data_start = (written == 0) ? offset32 : page_start;
2886 /* Find the data_end addr */
2887 data_end = (page_end > offset32 + len32) ?
2888 (offset32 + len32) : page_end;
2889
2890 /* Request access to the flash interface. */
2891 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2892 goto nvram_write_end;
2893
2894 /* Enable access to flash interface */
2895 bnx2_enable_nvram_access(bp);
2896
2897 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2898 if (bp->flash_info->buffered == 0) {
2899 int j;
2900
2901 /* Read the whole page into the buffer
2902 * (non-buffer flash only) */
2903 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2904 if (j == (bp->flash_info->page_size - 4)) {
2905 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2906 }
2907 rc = bnx2_nvram_read_dword(bp,
2908 page_start + j,
2909 &flash_buffer[j],
2910 cmd_flags);
2911
2912 if (rc)
2913 goto nvram_write_end;
2914
2915 cmd_flags = 0;
2916 }
2917 }
2918
2919 /* Enable writes to flash interface (unlock write-protect) */
2920 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2921 goto nvram_write_end;
2922
2923 /* Erase the page */
2924 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2925 goto nvram_write_end;
2926
2927 /* Re-enable the write again for the actual write */
2928 bnx2_enable_nvram_write(bp);
2929
2930 /* Loop to write back the buffer data from page_start to
2931 * data_start */
2932 i = 0;
2933 if (bp->flash_info->buffered == 0) {
2934 for (addr = page_start; addr < data_start;
2935 addr += 4, i += 4) {
2936
2937 rc = bnx2_nvram_write_dword(bp, addr,
2938 &flash_buffer[i], cmd_flags);
2939
2940 if (rc != 0)
2941 goto nvram_write_end;
2942
2943 cmd_flags = 0;
2944 }
2945 }
2946
2947 /* Loop to write the new data from data_start to data_end */
2948 for (addr = data_start; addr < data_end; addr += 4, i++) {
2949 if ((addr == page_end - 4) ||
2950 ((bp->flash_info->buffered) &&
2951 (addr == data_end - 4))) {
2952
2953 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2954 }
2955 rc = bnx2_nvram_write_dword(bp, addr, buf,
2956 cmd_flags);
2957
2958 if (rc != 0)
2959 goto nvram_write_end;
2960
2961 cmd_flags = 0;
2962 buf += 4;
2963 }
2964
2965 /* Loop to write back the buffer data from data_end
2966 * to page_end */
2967 if (bp->flash_info->buffered == 0) {
2968 for (addr = data_end; addr < page_end;
2969 addr += 4, i += 4) {
2970
2971 if (addr == page_end-4) {
2972 cmd_flags = BNX2_NVM_COMMAND_LAST;
2973 }
2974 rc = bnx2_nvram_write_dword(bp, addr,
2975 &flash_buffer[i], cmd_flags);
2976
2977 if (rc != 0)
2978 goto nvram_write_end;
2979
2980 cmd_flags = 0;
2981 }
2982 }
2983
2984 /* Disable writes to flash interface (lock write-protect) */
2985 bnx2_disable_nvram_write(bp);
2986
2987 /* Disable access to flash interface */
2988 bnx2_disable_nvram_access(bp);
2989 bnx2_release_nvram_lock(bp);
2990
2991 /* Increment written */
2992 written += data_end - data_start;
2993 }
2994
2995 nvram_write_end:
2996 if (align_start || align_end)
2997 kfree(buf);
2998 return rc;
2999 }
3000
3001 static int
3002 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3003 {
3004 u32 val;
3005 int i, rc = 0;
3006
3007 /* Wait for the current PCI transaction to complete before
3008 * issuing a reset. */
3009 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3010 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3011 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3012 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3013 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3014 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3015 udelay(5);
3016
3017 /* Deposit a driver reset signature so the firmware knows that
3018 * this is a soft reset. */
3019 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3020 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3021
3022 bp->fw_timed_out = 0;
3023
3024 /* Wait for the firmware to tell us it is ok to issue a reset. */
3025 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
3026
3027 /* Do a dummy read to force the chip to complete all current transaction
3028 * before we issue a reset. */
3029 val = REG_RD(bp, BNX2_MISC_ID);
3030
3031 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3032 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3033 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3034
3035 /* Chip reset. */
3036 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3037
3038 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3039 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3040 msleep(15);
3041
3042 /* Reset takes approximate 30 usec */
3043 for (i = 0; i < 10; i++) {
3044 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3045 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3046 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3047 break;
3048 }
3049 udelay(10);
3050 }
3051
3052 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3053 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3054 printk(KERN_ERR PFX "Chip reset did not complete\n");
3055 return -EBUSY;
3056 }
3057
3058 /* Make sure byte swapping is properly configured. */
3059 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3060 if (val != 0x01020304) {
3061 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3062 return -ENODEV;
3063 }
3064
3065 bp->fw_timed_out = 0;
3066
3067 /* Wait for the firmware to finish its initialization. */
3068 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
3069
3070 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3071 /* Adjust the voltage regular to two steps lower. The default
3072 * of this register is 0x0000000e. */
3073 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3074
3075 /* Remove bad rbuf memory from the free pool. */
3076 rc = bnx2_alloc_bad_rbuf(bp);
3077 }
3078
3079 return rc;
3080 }
3081
3082 static int
3083 bnx2_init_chip(struct bnx2 *bp)
3084 {
3085 u32 val;
3086
3087 /* Make sure the interrupt is not active. */
3088 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3089
3090 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3091 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3092 #ifdef __BIG_ENDIAN
3093 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3094 #endif
3095 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3096 DMA_READ_CHANS << 12 |
3097 DMA_WRITE_CHANS << 16;
3098
3099 val |= (0x2 << 20) | (1 << 11);
3100
3101 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
3102 val |= (1 << 23);
3103
3104 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3105 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3106 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3107
3108 REG_WR(bp, BNX2_DMA_CONFIG, val);
3109
3110 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3111 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3112 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3113 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3114 }
3115
3116 if (bp->flags & PCIX_FLAG) {
3117 u16 val16;
3118
3119 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3120 &val16);
3121 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3122 val16 & ~PCI_X_CMD_ERO);
3123 }
3124
3125 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3126 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3127 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3128 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3129
3130 /* Initialize context mapping and zero out the quick contexts. The
3131 * context block must have already been enabled. */
3132 bnx2_init_context(bp);
3133
3134 bnx2_init_cpus(bp);
3135 bnx2_init_nvram(bp);
3136
3137 bnx2_set_mac_addr(bp);
3138
3139 val = REG_RD(bp, BNX2_MQ_CONFIG);
3140 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3141 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3142 REG_WR(bp, BNX2_MQ_CONFIG, val);
3143
3144 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3145 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3146 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3147
3148 val = (BCM_PAGE_BITS - 8) << 24;
3149 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3150
3151 /* Configure page size. */
3152 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3153 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3154 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3155 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3156
3157 val = bp->mac_addr[0] +
3158 (bp->mac_addr[1] << 8) +
3159 (bp->mac_addr[2] << 16) +
3160 bp->mac_addr[3] +
3161 (bp->mac_addr[4] << 8) +
3162 (bp->mac_addr[5] << 16);
3163 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3164
3165 /* Program the MTU. Also include 4 bytes for CRC32. */
3166 val = bp->dev->mtu + ETH_HLEN + 4;
3167 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3168 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3169 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3170
3171 bp->last_status_idx = 0;
3172 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3173
3174 /* Set up how to generate a link change interrupt. */
3175 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3176
3177 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3178 (u64) bp->status_blk_mapping & 0xffffffff);
3179 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3180
3181 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3182 (u64) bp->stats_blk_mapping & 0xffffffff);
3183 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3184 (u64) bp->stats_blk_mapping >> 32);
3185
3186 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3187 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3188
3189 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3190 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3191
3192 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3193 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3194
3195 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3196
3197 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3198
3199 REG_WR(bp, BNX2_HC_COM_TICKS,
3200 (bp->com_ticks_int << 16) | bp->com_ticks);
3201
3202 REG_WR(bp, BNX2_HC_CMD_TICKS,
3203 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3204
3205 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3206 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3207
3208 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3209 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3210 else {
3211 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3212 BNX2_HC_CONFIG_TX_TMR_MODE |
3213 BNX2_HC_CONFIG_COLLECT_STATS);
3214 }
3215
3216 /* Clear internal stats counters. */
3217 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3218
3219 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3220
3221 /* Initialize the receive filter. */
3222 bnx2_set_rx_mode(bp->dev);
3223
3224 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
3225
3226 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3227 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3228
3229 udelay(20);
3230
3231 return 0;
3232 }
3233
3234
3235 static void
3236 bnx2_init_tx_ring(struct bnx2 *bp)
3237 {
3238 struct tx_bd *txbd;
3239 u32 val;
3240
3241 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3242
3243 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3244 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3245
3246 bp->tx_prod = 0;
3247 bp->tx_cons = 0;
3248 bp->hw_tx_cons = 0;
3249 bp->tx_prod_bseq = 0;
3250
3251 val = BNX2_L2CTX_TYPE_TYPE_L2;
3252 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3253 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3254
3255 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3256 val |= 8 << 16;
3257 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3258
3259 val = (u64) bp->tx_desc_mapping >> 32;
3260 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3261
3262 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3263 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3264 }
3265
3266 static void
3267 bnx2_init_rx_ring(struct bnx2 *bp)
3268 {
3269 struct rx_bd *rxbd;
3270 int i;
3271 u16 prod, ring_prod;
3272 u32 val;
3273
3274 /* 8 for CRC and VLAN */
3275 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3276 /* 8 for alignment */
3277 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3278
3279 ring_prod = prod = bp->rx_prod = 0;
3280 bp->rx_cons = 0;
3281 bp->hw_rx_cons = 0;
3282 bp->rx_prod_bseq = 0;
3283
3284 rxbd = &bp->rx_desc_ring[0];
3285 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3286 rxbd->rx_bd_len = bp->rx_buf_use_size;
3287 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3288 }
3289
3290 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3291 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3292
3293 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3294 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3295 val |= 0x02 << 8;
3296 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3297
3298 val = (u64) bp->rx_desc_mapping >> 32;
3299 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3300
3301 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3302 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3303
3304 for ( ;ring_prod < bp->rx_ring_size; ) {
3305 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3306 break;
3307 }
3308 prod = NEXT_RX_BD(prod);
3309 ring_prod = RX_RING_IDX(prod);
3310 }
3311 bp->rx_prod = prod;
3312
3313 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3314
3315 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3316 }
3317
3318 static void
3319 bnx2_free_tx_skbs(struct bnx2 *bp)
3320 {
3321 int i;
3322
3323 if (bp->tx_buf_ring == NULL)
3324 return;
3325
3326 for (i = 0; i < TX_DESC_CNT; ) {
3327 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3328 struct sk_buff *skb = tx_buf->skb;
3329 int j, last;
3330
3331 if (skb == NULL) {
3332 i++;
3333 continue;
3334 }
3335
3336 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3337 skb_headlen(skb), PCI_DMA_TODEVICE);
3338
3339 tx_buf->skb = NULL;
3340
3341 last = skb_shinfo(skb)->nr_frags;
3342 for (j = 0; j < last; j++) {
3343 tx_buf = &bp->tx_buf_ring[i + j + 1];
3344 pci_unmap_page(bp->pdev,
3345 pci_unmap_addr(tx_buf, mapping),
3346 skb_shinfo(skb)->frags[j].size,
3347 PCI_DMA_TODEVICE);
3348 }
3349 dev_kfree_skb_any(skb);
3350 i += j + 1;
3351 }
3352
3353 }
3354
3355 static void
3356 bnx2_free_rx_skbs(struct bnx2 *bp)
3357 {
3358 int i;
3359
3360 if (bp->rx_buf_ring == NULL)
3361 return;
3362
3363 for (i = 0; i < RX_DESC_CNT; i++) {
3364 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3365 struct sk_buff *skb = rx_buf->skb;
3366
3367 if (skb == NULL)
3368 continue;
3369
3370 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3371 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3372
3373 rx_buf->skb = NULL;
3374
3375 dev_kfree_skb_any(skb);
3376 }
3377 }
3378
3379 static void
3380 bnx2_free_skbs(struct bnx2 *bp)
3381 {
3382 bnx2_free_tx_skbs(bp);
3383 bnx2_free_rx_skbs(bp);
3384 }
3385
3386 static int
3387 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3388 {
3389 int rc;
3390
3391 rc = bnx2_reset_chip(bp, reset_code);
3392 bnx2_free_skbs(bp);
3393 if (rc)
3394 return rc;
3395
3396 bnx2_init_chip(bp);
3397 bnx2_init_tx_ring(bp);
3398 bnx2_init_rx_ring(bp);
3399 return 0;
3400 }
3401
3402 static int
3403 bnx2_init_nic(struct bnx2 *bp)
3404 {
3405 int rc;
3406
3407 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3408 return rc;
3409
3410 bnx2_init_phy(bp);
3411 bnx2_set_link(bp);
3412 return 0;
3413 }
3414
3415 static int
3416 bnx2_test_registers(struct bnx2 *bp)
3417 {
3418 int ret;
3419 int i;
3420 static struct {
3421 u16 offset;
3422 u16 flags;
3423 u32 rw_mask;
3424 u32 ro_mask;
3425 } reg_tbl[] = {
3426 { 0x006c, 0, 0x00000000, 0x0000003f },
3427 { 0x0090, 0, 0xffffffff, 0x00000000 },
3428 { 0x0094, 0, 0x00000000, 0x00000000 },
3429
3430 { 0x0404, 0, 0x00003f00, 0x00000000 },
3431 { 0x0418, 0, 0x00000000, 0xffffffff },
3432 { 0x041c, 0, 0x00000000, 0xffffffff },
3433 { 0x0420, 0, 0x00000000, 0x80ffffff },
3434 { 0x0424, 0, 0x00000000, 0x00000000 },
3435 { 0x0428, 0, 0x00000000, 0x00000001 },
3436 { 0x0450, 0, 0x00000000, 0x0000ffff },
3437 { 0x0454, 0, 0x00000000, 0xffffffff },
3438 { 0x0458, 0, 0x00000000, 0xffffffff },
3439
3440 { 0x0808, 0, 0x00000000, 0xffffffff },
3441 { 0x0854, 0, 0x00000000, 0xffffffff },
3442 { 0x0868, 0, 0x00000000, 0x77777777 },
3443 { 0x086c, 0, 0x00000000, 0x77777777 },
3444 { 0x0870, 0, 0x00000000, 0x77777777 },
3445 { 0x0874, 0, 0x00000000, 0x77777777 },
3446
3447 { 0x0c00, 0, 0x00000000, 0x00000001 },
3448 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3449 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3450 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3451 { 0x0c30, 0, 0x00000000, 0xffffffff },
3452 { 0x0c34, 0, 0x00000000, 0xffffffff },
3453 { 0x0c38, 0, 0x00000000, 0xffffffff },
3454 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3455 { 0x0c40, 0, 0x00000000, 0xffffffff },
3456 { 0x0c44, 0, 0x00000000, 0xffffffff },
3457 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3458 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3459 { 0x0c50, 0, 0x00000000, 0xffffffff },
3460 { 0x0c54, 0, 0x00000000, 0xffffffff },
3461 { 0x0c58, 0, 0x00000000, 0xffffffff },
3462 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3463 { 0x0c60, 0, 0x00000000, 0xffffffff },
3464 { 0x0c64, 0, 0x00000000, 0xffffffff },
3465 { 0x0c68, 0, 0x00000000, 0xffffffff },
3466 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3467 { 0x0c70, 0, 0x00000000, 0xffffffff },
3468 { 0x0c74, 0, 0x00000000, 0xffffffff },
3469 { 0x0c78, 0, 0x00000000, 0xffffffff },
3470 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3471 { 0x0c80, 0, 0x00000000, 0xffffffff },
3472 { 0x0c84, 0, 0x00000000, 0xffffffff },
3473 { 0x0c88, 0, 0x00000000, 0xffffffff },
3474 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3475 { 0x0c90, 0, 0x00000000, 0xffffffff },
3476 { 0x0c94, 0, 0x00000000, 0xffffffff },
3477 { 0x0c98, 0, 0x00000000, 0xffffffff },
3478 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3479 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3480 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3481 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3482 { 0x0cac, 0, 0x00000000, 0xffffffff },
3483 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3484 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3485 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3486 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3487 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3488 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3489 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3490 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3491 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3492 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3493 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3494 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3495 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3496 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3497 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3498 { 0x0cec, 0, 0x00000000, 0xffffffff },
3499 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3500 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3501 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3502 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3503 { 0x0d00, 0, 0x00000000, 0xffffffff },
3504 { 0x0d04, 0, 0x00000000, 0xffffffff },
3505
3506 { 0x1000, 0, 0x00000000, 0x00000001 },
3507 { 0x1004, 0, 0x00000000, 0x000f0001 },
3508 { 0x1044, 0, 0x00000000, 0xffc003ff },
3509 { 0x1080, 0, 0x00000000, 0x0001ffff },
3510 { 0x1084, 0, 0x00000000, 0xffffffff },
3511 { 0x1088, 0, 0x00000000, 0xffffffff },
3512 { 0x108c, 0, 0x00000000, 0xffffffff },
3513 { 0x1090, 0, 0x00000000, 0xffffffff },
3514 { 0x1094, 0, 0x00000000, 0xffffffff },
3515 { 0x1098, 0, 0x00000000, 0xffffffff },
3516 { 0x109c, 0, 0x00000000, 0xffffffff },
3517 { 0x10a0, 0, 0x00000000, 0xffffffff },
3518
3519 { 0x1408, 0, 0x01c00800, 0x00000000 },
3520 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3521 { 0x14a8, 0, 0x00000000, 0x000001ff },
3522 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3523 { 0x14b0, 0, 0x00000002, 0x00000001 },
3524 { 0x14b8, 0, 0x00000000, 0x00000000 },
3525 { 0x14c0, 0, 0x00000000, 0x00000009 },
3526 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3527 { 0x14cc, 0, 0x00000000, 0x00000001 },
3528 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3529 { 0x1500, 0, 0x00000000, 0xffffffff },
3530 { 0x1504, 0, 0x00000000, 0xffffffff },
3531 { 0x1508, 0, 0x00000000, 0xffffffff },
3532 { 0x150c, 0, 0x00000000, 0xffffffff },
3533 { 0x1510, 0, 0x00000000, 0xffffffff },
3534 { 0x1514, 0, 0x00000000, 0xffffffff },
3535 { 0x1518, 0, 0x00000000, 0xffffffff },
3536 { 0x151c, 0, 0x00000000, 0xffffffff },
3537 { 0x1520, 0, 0x00000000, 0xffffffff },
3538 { 0x1524, 0, 0x00000000, 0xffffffff },
3539 { 0x1528, 0, 0x00000000, 0xffffffff },
3540 { 0x152c, 0, 0x00000000, 0xffffffff },
3541 { 0x1530, 0, 0x00000000, 0xffffffff },
3542 { 0x1534, 0, 0x00000000, 0xffffffff },
3543 { 0x1538, 0, 0x00000000, 0xffffffff },
3544 { 0x153c, 0, 0x00000000, 0xffffffff },
3545 { 0x1540, 0, 0x00000000, 0xffffffff },
3546 { 0x1544, 0, 0x00000000, 0xffffffff },
3547 { 0x1548, 0, 0x00000000, 0xffffffff },
3548 { 0x154c, 0, 0x00000000, 0xffffffff },
3549 { 0x1550, 0, 0x00000000, 0xffffffff },
3550 { 0x1554, 0, 0x00000000, 0xffffffff },
3551 { 0x1558, 0, 0x00000000, 0xffffffff },
3552 { 0x1600, 0, 0x00000000, 0xffffffff },
3553 { 0x1604, 0, 0x00000000, 0xffffffff },
3554 { 0x1608, 0, 0x00000000, 0xffffffff },
3555 { 0x160c, 0, 0x00000000, 0xffffffff },
3556 { 0x1610, 0, 0x00000000, 0xffffffff },
3557 { 0x1614, 0, 0x00000000, 0xffffffff },
3558 { 0x1618, 0, 0x00000000, 0xffffffff },
3559 { 0x161c, 0, 0x00000000, 0xffffffff },
3560 { 0x1620, 0, 0x00000000, 0xffffffff },
3561 { 0x1624, 0, 0x00000000, 0xffffffff },
3562 { 0x1628, 0, 0x00000000, 0xffffffff },
3563 { 0x162c, 0, 0x00000000, 0xffffffff },
3564 { 0x1630, 0, 0x00000000, 0xffffffff },
3565 { 0x1634, 0, 0x00000000, 0xffffffff },
3566 { 0x1638, 0, 0x00000000, 0xffffffff },
3567 { 0x163c, 0, 0x00000000, 0xffffffff },
3568 { 0x1640, 0, 0x00000000, 0xffffffff },
3569 { 0x1644, 0, 0x00000000, 0xffffffff },
3570 { 0x1648, 0, 0x00000000, 0xffffffff },
3571 { 0x164c, 0, 0x00000000, 0xffffffff },
3572 { 0x1650, 0, 0x00000000, 0xffffffff },
3573 { 0x1654, 0, 0x00000000, 0xffffffff },
3574
3575 { 0x1800, 0, 0x00000000, 0x00000001 },
3576 { 0x1804, 0, 0x00000000, 0x00000003 },
3577 { 0x1840, 0, 0x00000000, 0xffffffff },
3578 { 0x1844, 0, 0x00000000, 0xffffffff },
3579 { 0x1848, 0, 0x00000000, 0xffffffff },
3580 { 0x184c, 0, 0x00000000, 0xffffffff },
3581 { 0x1850, 0, 0x00000000, 0xffffffff },
3582 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3583 { 0x1904, 0, 0xffffffff, 0x00000000 },
3584 { 0x190c, 0, 0xffffffff, 0x00000000 },
3585 { 0x1914, 0, 0xffffffff, 0x00000000 },
3586 { 0x191c, 0, 0xffffffff, 0x00000000 },
3587 { 0x1924, 0, 0xffffffff, 0x00000000 },
3588 { 0x192c, 0, 0xffffffff, 0x00000000 },
3589 { 0x1934, 0, 0xffffffff, 0x00000000 },
3590 { 0x193c, 0, 0xffffffff, 0x00000000 },
3591 { 0x1944, 0, 0xffffffff, 0x00000000 },
3592 { 0x194c, 0, 0xffffffff, 0x00000000 },
3593 { 0x1954, 0, 0xffffffff, 0x00000000 },
3594 { 0x195c, 0, 0xffffffff, 0x00000000 },
3595 { 0x1964, 0, 0xffffffff, 0x00000000 },
3596 { 0x196c, 0, 0xffffffff, 0x00000000 },
3597 { 0x1974, 0, 0xffffffff, 0x00000000 },
3598 { 0x197c, 0, 0xffffffff, 0x00000000 },
3599 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3600
3601 { 0x1c00, 0, 0x00000000, 0x00000001 },
3602 { 0x1c04, 0, 0x00000000, 0x00000003 },
3603 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3604 { 0x1c40, 0, 0x00000000, 0xffffffff },
3605 { 0x1c44, 0, 0x00000000, 0xffffffff },
3606 { 0x1c48, 0, 0x00000000, 0xffffffff },
3607 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3608 { 0x1c50, 0, 0x00000000, 0xffffffff },
3609 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3610 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3611 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3612 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3613 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3614 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3615 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3616 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3617 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3618 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3619 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3620 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3621 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3622 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3623 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3624 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3625 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3626 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3627
3628 { 0x2004, 0, 0x00000000, 0x0337000f },
3629 { 0x2008, 0, 0xffffffff, 0x00000000 },
3630 { 0x200c, 0, 0xffffffff, 0x00000000 },
3631 { 0x2010, 0, 0xffffffff, 0x00000000 },
3632 { 0x2014, 0, 0x801fff80, 0x00000000 },
3633 { 0x2018, 0, 0x000003ff, 0x00000000 },
3634
3635 { 0x2800, 0, 0x00000000, 0x00000001 },
3636 { 0x2804, 0, 0x00000000, 0x00003f01 },
3637 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3638 { 0x2810, 0, 0xffff0000, 0x00000000 },
3639 { 0x2814, 0, 0xffff0000, 0x00000000 },
3640 { 0x2818, 0, 0xffff0000, 0x00000000 },
3641 { 0x281c, 0, 0xffff0000, 0x00000000 },
3642 { 0x2834, 0, 0xffffffff, 0x00000000 },
3643 { 0x2840, 0, 0x00000000, 0xffffffff },
3644 { 0x2844, 0, 0x00000000, 0xffffffff },
3645 { 0x2848, 0, 0xffffffff, 0x00000000 },
3646 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3647
3648 { 0x2c00, 0, 0x00000000, 0x00000011 },
3649 { 0x2c04, 0, 0x00000000, 0x00030007 },
3650
3651 { 0x3000, 0, 0x00000000, 0x00000001 },
3652 { 0x3004, 0, 0x00000000, 0x007007ff },
3653 { 0x3008, 0, 0x00000003, 0x00000000 },
3654 { 0x300c, 0, 0xffffffff, 0x00000000 },
3655 { 0x3010, 0, 0xffffffff, 0x00000000 },
3656 { 0x3014, 0, 0xffffffff, 0x00000000 },
3657 { 0x3034, 0, 0xffffffff, 0x00000000 },
3658 { 0x3038, 0, 0xffffffff, 0x00000000 },
3659 { 0x3050, 0, 0x00000001, 0x00000000 },
3660
3661 { 0x3c00, 0, 0x00000000, 0x00000001 },
3662 { 0x3c04, 0, 0x00000000, 0x00070000 },
3663 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3664 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3665 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3666 { 0x3c14, 0, 0x00000000, 0xffffffff },
3667 { 0x3c18, 0, 0x00000000, 0xffffffff },
3668 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3669 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3670 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3671 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3672 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3673 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3674 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3675 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3676 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3677 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3678 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3679 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3680 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3681 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3682 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3683 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3684 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3685 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3686 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3687 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3688 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3689 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3690 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3691 { 0x3c78, 0, 0x00000000, 0x00000000 },
3692 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3693 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3694 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3695 { 0x3c88, 0, 0x00000000, 0xffffffff },
3696 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3697
3698 { 0x4000, 0, 0x00000000, 0x00000001 },
3699 { 0x4004, 0, 0x00000000, 0x00030000 },
3700 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3701 { 0x400c, 0, 0xffffffff, 0x00000000 },
3702 { 0x4088, 0, 0x00000000, 0x00070303 },
3703
3704 { 0x4400, 0, 0x00000000, 0x00000001 },
3705 { 0x4404, 0, 0x00000000, 0x00003f01 },
3706 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3707 { 0x440c, 0, 0xffffffff, 0x00000000 },
3708 { 0x4410, 0, 0xffff, 0x0000 },
3709 { 0x4414, 0, 0xffff, 0x0000 },
3710 { 0x4418, 0, 0xffff, 0x0000 },
3711 { 0x441c, 0, 0xffff, 0x0000 },
3712 { 0x4428, 0, 0xffffffff, 0x00000000 },
3713 { 0x442c, 0, 0xffffffff, 0x00000000 },
3714 { 0x4430, 0, 0xffffffff, 0x00000000 },
3715 { 0x4434, 0, 0xffffffff, 0x00000000 },
3716 { 0x4438, 0, 0xffffffff, 0x00000000 },
3717 { 0x443c, 0, 0xffffffff, 0x00000000 },
3718 { 0x4440, 0, 0xffffffff, 0x00000000 },
3719 { 0x4444, 0, 0xffffffff, 0x00000000 },
3720
3721 { 0x4c00, 0, 0x00000000, 0x00000001 },
3722 { 0x4c04, 0, 0x00000000, 0x0000003f },
3723 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3724 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3725 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3726 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3727 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3728 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3729 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3730 { 0x4c50, 0, 0x00000000, 0xffffffff },
3731
3732 { 0x5004, 0, 0x00000000, 0x0000007f },
3733 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3734 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3735
3736 { 0x5400, 0, 0x00000008, 0x00000001 },
3737 { 0x5404, 0, 0x00000000, 0x0000003f },
3738 { 0x5408, 0, 0x0000001f, 0x00000000 },
3739 { 0x540c, 0, 0xffffffff, 0x00000000 },
3740 { 0x5410, 0, 0xffffffff, 0x00000000 },
3741 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3742 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3743 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3744 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3745 { 0x5428, 0, 0x000000ff, 0x00000000 },
3746 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3747 { 0x5430, 0, 0x001fff80, 0x00000000 },
3748 { 0x5438, 0, 0xffffffff, 0x00000000 },
3749 { 0x543c, 0, 0xffffffff, 0x00000000 },
3750 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3751
3752 { 0x5c00, 0, 0x00000000, 0x00000001 },
3753 { 0x5c04, 0, 0x00000000, 0x0003000f },
3754 { 0x5c08, 0, 0x00000003, 0x00000000 },
3755 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3756 { 0x5c10, 0, 0x00000000, 0xffffffff },
3757 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3758 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3759 { 0x5c88, 0, 0x00000000, 0x00077373 },
3760 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3761
3762 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3763 { 0x680c, 0, 0xffffffff, 0x00000000 },
3764 { 0x6810, 0, 0xffffffff, 0x00000000 },
3765 { 0x6814, 0, 0xffffffff, 0x00000000 },
3766 { 0x6818, 0, 0xffffffff, 0x00000000 },
3767 { 0x681c, 0, 0xffffffff, 0x00000000 },
3768 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3769 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3770 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3771 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3772 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3773 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3774 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3775 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3776 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3777 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3778 { 0x684c, 0, 0xffffffff, 0x00000000 },
3779 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3780 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3781 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3782 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3783 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3784 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3785
3786 { 0xffff, 0, 0x00000000, 0x00000000 },
3787 };
3788
3789 ret = 0;
3790 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3791 u32 offset, rw_mask, ro_mask, save_val, val;
3792
3793 offset = (u32) reg_tbl[i].offset;
3794 rw_mask = reg_tbl[i].rw_mask;
3795 ro_mask = reg_tbl[i].ro_mask;
3796
3797 save_val = readl(bp->regview + offset);
3798
3799 writel(0, bp->regview + offset);
3800
3801 val = readl(bp->regview + offset);
3802 if ((val & rw_mask) != 0) {
3803 goto reg_test_err;
3804 }
3805
3806 if ((val & ro_mask) != (save_val & ro_mask)) {
3807 goto reg_test_err;
3808 }
3809
3810 writel(0xffffffff, bp->regview + offset);
3811
3812 val = readl(bp->regview + offset);
3813 if ((val & rw_mask) != rw_mask) {
3814 goto reg_test_err;
3815 }
3816
3817 if ((val & ro_mask) != (save_val & ro_mask)) {
3818 goto reg_test_err;
3819 }
3820
3821 writel(save_val, bp->regview + offset);
3822 continue;
3823
3824 reg_test_err:
3825 writel(save_val, bp->regview + offset);
3826 ret = -ENODEV;
3827 break;
3828 }
3829 return ret;
3830 }
3831
3832 static int
3833 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3834 {
3835 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3836 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3837 int i;
3838
3839 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3840 u32 offset;
3841
3842 for (offset = 0; offset < size; offset += 4) {
3843
3844 REG_WR_IND(bp, start + offset, test_pattern[i]);
3845
3846 if (REG_RD_IND(bp, start + offset) !=
3847 test_pattern[i]) {
3848 return -ENODEV;
3849 }
3850 }
3851 }
3852 return 0;
3853 }
3854
3855 static int
3856 bnx2_test_memory(struct bnx2 *bp)
3857 {
3858 int ret = 0;
3859 int i;
3860 static struct {
3861 u32 offset;
3862 u32 len;
3863 } mem_tbl[] = {
3864 { 0x60000, 0x4000 },
3865 { 0xa0000, 0x3000 },
3866 { 0xe0000, 0x4000 },
3867 { 0x120000, 0x4000 },
3868 { 0x1a0000, 0x4000 },
3869 { 0x160000, 0x4000 },
3870 { 0xffffffff, 0 },
3871 };
3872
3873 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3874 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3875 mem_tbl[i].len)) != 0) {
3876 return ret;
3877 }
3878 }
3879
3880 return ret;
3881 }
3882
3883 static int
3884 bnx2_test_loopback(struct bnx2 *bp)
3885 {
3886 unsigned int pkt_size, num_pkts, i;
3887 struct sk_buff *skb, *rx_skb;
3888 unsigned char *packet;
3889 u16 rx_start_idx, rx_idx, send_idx;
3890 u32 send_bseq, val;
3891 dma_addr_t map;
3892 struct tx_bd *txbd;
3893 struct sw_bd *rx_buf;
3894 struct l2_fhdr *rx_hdr;
3895 int ret = -ENODEV;
3896
3897 if (!netif_running(bp->dev))
3898 return -ENODEV;
3899
3900 bp->loopback = MAC_LOOPBACK;
3901 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3902 bnx2_set_mac_loopback(bp);
3903
3904 pkt_size = 1514;
3905 skb = dev_alloc_skb(pkt_size);
3906 if (!skb)
3907 return -ENOMEM;
3908 packet = skb_put(skb, pkt_size);
3909 memcpy(packet, bp->mac_addr, 6);
3910 memset(packet + 6, 0x0, 8);
3911 for (i = 14; i < pkt_size; i++)
3912 packet[i] = (unsigned char) (i & 0xff);
3913
3914 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3915 PCI_DMA_TODEVICE);
3916
3917 val = REG_RD(bp, BNX2_HC_COMMAND);
3918 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3919 REG_RD(bp, BNX2_HC_COMMAND);
3920
3921 udelay(5);
3922 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3923
3924 send_idx = 0;
3925 send_bseq = 0;
3926 num_pkts = 0;
3927
3928 txbd = &bp->tx_desc_ring[send_idx];
3929
3930 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3931 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3932 txbd->tx_bd_mss_nbytes = pkt_size;
3933 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3934
3935 num_pkts++;
3936 send_idx = NEXT_TX_BD(send_idx);
3937
3938 send_bseq += pkt_size;
3939
3940 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3941 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3942
3943
3944 udelay(100);
3945
3946 val = REG_RD(bp, BNX2_HC_COMMAND);
3947 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3948 REG_RD(bp, BNX2_HC_COMMAND);
3949
3950 udelay(5);
3951
3952 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3953 dev_kfree_skb_irq(skb);
3954
3955 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3956 goto loopback_test_done;
3957 }
3958
3959 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3960 if (rx_idx != rx_start_idx + num_pkts) {
3961 goto loopback_test_done;
3962 }
3963
3964 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3965 rx_skb = rx_buf->skb;
3966
3967 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3968 skb_reserve(rx_skb, bp->rx_offset);
3969
3970 pci_dma_sync_single_for_cpu(bp->pdev,
3971 pci_unmap_addr(rx_buf, mapping),
3972 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3973
3974 if (rx_hdr->l2_fhdr_errors &
3975 (L2_FHDR_ERRORS_BAD_CRC |
3976 L2_FHDR_ERRORS_PHY_DECODE |
3977 L2_FHDR_ERRORS_ALIGNMENT |
3978 L2_FHDR_ERRORS_TOO_SHORT |
3979 L2_FHDR_ERRORS_GIANT_FRAME)) {
3980
3981 goto loopback_test_done;
3982 }
3983
3984 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3985 goto loopback_test_done;
3986 }
3987
3988 for (i = 14; i < pkt_size; i++) {
3989 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3990 goto loopback_test_done;
3991 }
3992 }
3993
3994 ret = 0;
3995
3996 loopback_test_done:
3997 bp->loopback = 0;
3998 return ret;
3999 }
4000
4001 #define NVRAM_SIZE 0x200
4002 #define CRC32_RESIDUAL 0xdebb20e3
4003
4004 static int
4005 bnx2_test_nvram(struct bnx2 *bp)
4006 {
4007 u32 buf[NVRAM_SIZE / 4];
4008 u8 *data = (u8 *) buf;
4009 int rc = 0;
4010 u32 magic, csum;
4011
4012 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4013 goto test_nvram_done;
4014
4015 magic = be32_to_cpu(buf[0]);
4016 if (magic != 0x669955aa) {
4017 rc = -ENODEV;
4018 goto test_nvram_done;
4019 }
4020
4021 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4022 goto test_nvram_done;
4023
4024 csum = ether_crc_le(0x100, data);
4025 if (csum != CRC32_RESIDUAL) {
4026 rc = -ENODEV;
4027 goto test_nvram_done;
4028 }
4029
4030 csum = ether_crc_le(0x100, data + 0x100);
4031 if (csum != CRC32_RESIDUAL) {
4032 rc = -ENODEV;
4033 }
4034
4035 test_nvram_done:
4036 return rc;
4037 }
4038
4039 static int
4040 bnx2_test_link(struct bnx2 *bp)
4041 {
4042 u32 bmsr;
4043
4044 spin_lock_bh(&bp->phy_lock);
4045 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4046 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4047 spin_unlock_bh(&bp->phy_lock);
4048
4049 if (bmsr & BMSR_LSTATUS) {
4050 return 0;
4051 }
4052 return -ENODEV;
4053 }
4054
4055 static int
4056 bnx2_test_intr(struct bnx2 *bp)
4057 {
4058 int i;
4059 u32 val;
4060 u16 status_idx;
4061
4062 if (!netif_running(bp->dev))
4063 return -ENODEV;
4064
4065 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4066
4067 /* This register is not touched during run-time. */
4068 val = REG_RD(bp, BNX2_HC_COMMAND);
4069 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
4070 REG_RD(bp, BNX2_HC_COMMAND);
4071
4072 for (i = 0; i < 10; i++) {
4073 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4074 status_idx) {
4075
4076 break;
4077 }
4078
4079 msleep_interruptible(10);
4080 }
4081 if (i < 10)
4082 return 0;
4083
4084 return -ENODEV;
4085 }
4086
4087 static void
4088 bnx2_timer(unsigned long data)
4089 {
4090 struct bnx2 *bp = (struct bnx2 *) data;
4091 u32 msg;
4092
4093 if (!netif_running(bp->dev))
4094 return;
4095
4096 if (atomic_read(&bp->intr_sem) != 0)
4097 goto bnx2_restart_timer;
4098
4099 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4100 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4101
4102 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4103 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4104
4105 spin_lock(&bp->phy_lock);
4106 if (bp->serdes_an_pending) {
4107 bp->serdes_an_pending--;
4108 }
4109 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4110 u32 bmcr;
4111
4112 bp->current_interval = bp->timer_interval;
4113
4114 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4115
4116 if (bmcr & BMCR_ANENABLE) {
4117 u32 phy1, phy2;
4118
4119 bnx2_write_phy(bp, 0x1c, 0x7c00);
4120 bnx2_read_phy(bp, 0x1c, &phy1);
4121
4122 bnx2_write_phy(bp, 0x17, 0x0f01);
4123 bnx2_read_phy(bp, 0x15, &phy2);
4124 bnx2_write_phy(bp, 0x17, 0x0f01);
4125 bnx2_read_phy(bp, 0x15, &phy2);
4126
4127 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4128 !(phy2 & 0x20)) { /* no CONFIG */
4129
4130 bmcr &= ~BMCR_ANENABLE;
4131 bmcr |= BMCR_SPEED1000 |
4132 BMCR_FULLDPLX;
4133 bnx2_write_phy(bp, MII_BMCR, bmcr);
4134 bp->phy_flags |=
4135 PHY_PARALLEL_DETECT_FLAG;
4136 }
4137 }
4138 }
4139 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4140 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4141 u32 phy2;
4142
4143 bnx2_write_phy(bp, 0x17, 0x0f01);
4144 bnx2_read_phy(bp, 0x15, &phy2);
4145 if (phy2 & 0x20) {
4146 u32 bmcr;
4147
4148 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4149 bmcr |= BMCR_ANENABLE;
4150 bnx2_write_phy(bp, MII_BMCR, bmcr);
4151
4152 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4153
4154 }
4155 }
4156 else
4157 bp->current_interval = bp->timer_interval;
4158
4159 spin_unlock(&bp->phy_lock);
4160 }
4161
4162 bnx2_restart_timer:
4163 mod_timer(&bp->timer, jiffies + bp->current_interval);
4164 }
4165
4166 /* Called with rtnl_lock */
4167 static int
4168 bnx2_open(struct net_device *dev)
4169 {
4170 struct bnx2 *bp = dev->priv;
4171 int rc;
4172
4173 bnx2_set_power_state(bp, PCI_D0);
4174 bnx2_disable_int(bp);
4175
4176 rc = bnx2_alloc_mem(bp);
4177 if (rc)
4178 return rc;
4179
4180 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4181 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4182 !disable_msi) {
4183
4184 if (pci_enable_msi(bp->pdev) == 0) {
4185 bp->flags |= USING_MSI_FLAG;
4186 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4187 dev);
4188 }
4189 else {
4190 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4191 SA_SHIRQ, dev->name, dev);
4192 }
4193 }
4194 else {
4195 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
4196 dev->name, dev);
4197 }
4198 if (rc) {
4199 bnx2_free_mem(bp);
4200 return rc;
4201 }
4202
4203 rc = bnx2_init_nic(bp);
4204
4205 if (rc) {
4206 free_irq(bp->pdev->irq, dev);
4207 if (bp->flags & USING_MSI_FLAG) {
4208 pci_disable_msi(bp->pdev);
4209 bp->flags &= ~USING_MSI_FLAG;
4210 }
4211 bnx2_free_skbs(bp);
4212 bnx2_free_mem(bp);
4213 return rc;
4214 }
4215
4216 mod_timer(&bp->timer, jiffies + bp->current_interval);
4217
4218 atomic_set(&bp->intr_sem, 0);
4219
4220 bnx2_enable_int(bp);
4221
4222 if (bp->flags & USING_MSI_FLAG) {
4223 /* Test MSI to make sure it is working
4224 * If MSI test fails, go back to INTx mode
4225 */
4226 if (bnx2_test_intr(bp) != 0) {
4227 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4228 " using MSI, switching to INTx mode. Please"
4229 " report this failure to the PCI maintainer"
4230 " and include system chipset information.\n",
4231 bp->dev->name);
4232
4233 bnx2_disable_int(bp);
4234 free_irq(bp->pdev->irq, dev);
4235 pci_disable_msi(bp->pdev);
4236 bp->flags &= ~USING_MSI_FLAG;
4237
4238 rc = bnx2_init_nic(bp);
4239
4240 if (!rc) {
4241 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4242 SA_SHIRQ, dev->name, dev);
4243 }
4244 if (rc) {
4245 bnx2_free_skbs(bp);
4246 bnx2_free_mem(bp);
4247 del_timer_sync(&bp->timer);
4248 return rc;
4249 }
4250 bnx2_enable_int(bp);
4251 }
4252 }
4253 if (bp->flags & USING_MSI_FLAG) {
4254 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4255 }
4256
4257 netif_start_queue(dev);
4258
4259 return 0;
4260 }
4261
4262 static void
4263 bnx2_reset_task(void *data)
4264 {
4265 struct bnx2 *bp = data;
4266
4267 if (!netif_running(bp->dev))
4268 return;
4269
4270 bp->in_reset_task = 1;
4271 bnx2_netif_stop(bp);
4272
4273 bnx2_init_nic(bp);
4274
4275 atomic_set(&bp->intr_sem, 1);
4276 bnx2_netif_start(bp);
4277 bp->in_reset_task = 0;
4278 }
4279
4280 static void
4281 bnx2_tx_timeout(struct net_device *dev)
4282 {
4283 struct bnx2 *bp = dev->priv;
4284
4285 /* This allows the netif to be shutdown gracefully before resetting */
4286 schedule_work(&bp->reset_task);
4287 }
4288
4289 #ifdef BCM_VLAN
4290 /* Called with rtnl_lock */
4291 static void
4292 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4293 {
4294 struct bnx2 *bp = dev->priv;
4295
4296 bnx2_netif_stop(bp);
4297
4298 bp->vlgrp = vlgrp;
4299 bnx2_set_rx_mode(dev);
4300
4301 bnx2_netif_start(bp);
4302 }
4303
4304 /* Called with rtnl_lock */
4305 static void
4306 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4307 {
4308 struct bnx2 *bp = dev->priv;
4309
4310 bnx2_netif_stop(bp);
4311
4312 if (bp->vlgrp)
4313 bp->vlgrp->vlan_devices[vid] = NULL;
4314 bnx2_set_rx_mode(dev);
4315
4316 bnx2_netif_start(bp);
4317 }
4318 #endif
4319
4320 /* Called with dev->xmit_lock.
4321 * hard_start_xmit is pseudo-lockless - a lock is only required when
4322 * the tx queue is full. This way, we get the benefit of lockless
4323 * operations most of the time without the complexities to handle
4324 * netif_stop_queue/wake_queue race conditions.
4325 */
4326 static int
4327 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4328 {
4329 struct bnx2 *bp = dev->priv;
4330 dma_addr_t mapping;
4331 struct tx_bd *txbd;
4332 struct sw_bd *tx_buf;
4333 u32 len, vlan_tag_flags, last_frag, mss;
4334 u16 prod, ring_prod;
4335 int i;
4336
4337 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4338 netif_stop_queue(dev);
4339 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4340 dev->name);
4341
4342 return NETDEV_TX_BUSY;
4343 }
4344 len = skb_headlen(skb);
4345 prod = bp->tx_prod;
4346 ring_prod = TX_RING_IDX(prod);
4347
4348 vlan_tag_flags = 0;
4349 if (skb->ip_summed == CHECKSUM_HW) {
4350 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4351 }
4352
4353 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4354 vlan_tag_flags |=
4355 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4356 }
4357 #ifdef BCM_TSO
4358 if ((mss = skb_shinfo(skb)->tso_size) &&
4359 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4360 u32 tcp_opt_len, ip_tcp_len;
4361
4362 if (skb_header_cloned(skb) &&
4363 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4364 dev_kfree_skb(skb);
4365 return NETDEV_TX_OK;
4366 }
4367
4368 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4369 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4370
4371 tcp_opt_len = 0;
4372 if (skb->h.th->doff > 5) {
4373 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4374 }
4375 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4376
4377 skb->nh.iph->check = 0;
4378 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4379 skb->h.th->check =
4380 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4381 skb->nh.iph->daddr,
4382 0, IPPROTO_TCP, 0);
4383
4384 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4385 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4386 (tcp_opt_len >> 2)) << 8;
4387 }
4388 }
4389 else
4390 #endif
4391 {
4392 mss = 0;
4393 }
4394
4395 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4396
4397 tx_buf = &bp->tx_buf_ring[ring_prod];
4398 tx_buf->skb = skb;
4399 pci_unmap_addr_set(tx_buf, mapping, mapping);
4400
4401 txbd = &bp->tx_desc_ring[ring_prod];
4402
4403 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4404 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4405 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4406 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4407
4408 last_frag = skb_shinfo(skb)->nr_frags;
4409
4410 for (i = 0; i < last_frag; i++) {
4411 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4412
4413 prod = NEXT_TX_BD(prod);
4414 ring_prod = TX_RING_IDX(prod);
4415 txbd = &bp->tx_desc_ring[ring_prod];
4416
4417 len = frag->size;
4418 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4419 len, PCI_DMA_TODEVICE);
4420 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4421 mapping, mapping);
4422
4423 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4424 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4425 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4426 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4427
4428 }
4429 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4430
4431 prod = NEXT_TX_BD(prod);
4432 bp->tx_prod_bseq += skb->len;
4433
4434 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4435 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4436
4437 mmiowb();
4438
4439 bp->tx_prod = prod;
4440 dev->trans_start = jiffies;
4441
4442 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4443 spin_lock(&bp->tx_lock);
4444 netif_stop_queue(dev);
4445
4446 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4447 netif_wake_queue(dev);
4448 spin_unlock(&bp->tx_lock);
4449 }
4450
4451 return NETDEV_TX_OK;
4452 }
4453
4454 /* Called with rtnl_lock */
4455 static int
4456 bnx2_close(struct net_device *dev)
4457 {
4458 struct bnx2 *bp = dev->priv;
4459 u32 reset_code;
4460
4461 /* Calling flush_scheduled_work() may deadlock because
4462 * linkwatch_event() may be on the workqueue and it will try to get
4463 * the rtnl_lock which we are holding.
4464 */
4465 while (bp->in_reset_task)
4466 msleep(1);
4467
4468 bnx2_netif_stop(bp);
4469 del_timer_sync(&bp->timer);
4470 if (bp->wol)
4471 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4472 else
4473 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4474 bnx2_reset_chip(bp, reset_code);
4475 free_irq(bp->pdev->irq, dev);
4476 if (bp->flags & USING_MSI_FLAG) {
4477 pci_disable_msi(bp->pdev);
4478 bp->flags &= ~USING_MSI_FLAG;
4479 }
4480 bnx2_free_skbs(bp);
4481 bnx2_free_mem(bp);
4482 bp->link_up = 0;
4483 netif_carrier_off(bp->dev);
4484 bnx2_set_power_state(bp, PCI_D3hot);
4485 return 0;
4486 }
4487
4488 #define GET_NET_STATS64(ctr) \
4489 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4490 (unsigned long) (ctr##_lo)
4491
4492 #define GET_NET_STATS32(ctr) \
4493 (ctr##_lo)
4494
4495 #if (BITS_PER_LONG == 64)
4496 #define GET_NET_STATS GET_NET_STATS64
4497 #else
4498 #define GET_NET_STATS GET_NET_STATS32
4499 #endif
4500
4501 static struct net_device_stats *
4502 bnx2_get_stats(struct net_device *dev)
4503 {
4504 struct bnx2 *bp = dev->priv;
4505 struct statistics_block *stats_blk = bp->stats_blk;
4506 struct net_device_stats *net_stats = &bp->net_stats;
4507
4508 if (bp->stats_blk == NULL) {
4509 return net_stats;
4510 }
4511 net_stats->rx_packets =
4512 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4513 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4514 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4515
4516 net_stats->tx_packets =
4517 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4518 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4519 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4520
4521 net_stats->rx_bytes =
4522 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4523
4524 net_stats->tx_bytes =
4525 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4526
4527 net_stats->multicast =
4528 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4529
4530 net_stats->collisions =
4531 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4532
4533 net_stats->rx_length_errors =
4534 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4535 stats_blk->stat_EtherStatsOverrsizePkts);
4536
4537 net_stats->rx_over_errors =
4538 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4539
4540 net_stats->rx_frame_errors =
4541 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4542
4543 net_stats->rx_crc_errors =
4544 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4545
4546 net_stats->rx_errors = net_stats->rx_length_errors +
4547 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4548 net_stats->rx_crc_errors;
4549
4550 net_stats->tx_aborted_errors =
4551 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4552 stats_blk->stat_Dot3StatsLateCollisions);
4553
4554 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4555 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4556 net_stats->tx_carrier_errors = 0;
4557 else {
4558 net_stats->tx_carrier_errors =
4559 (unsigned long)
4560 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4561 }
4562
4563 net_stats->tx_errors =
4564 (unsigned long)
4565 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4566 +
4567 net_stats->tx_aborted_errors +
4568 net_stats->tx_carrier_errors;
4569
4570 return net_stats;
4571 }
4572
4573 /* All ethtool functions called with rtnl_lock */
4574
4575 static int
4576 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4577 {
4578 struct bnx2 *bp = dev->priv;
4579
4580 cmd->supported = SUPPORTED_Autoneg;
4581 if (bp->phy_flags & PHY_SERDES_FLAG) {
4582 cmd->supported |= SUPPORTED_1000baseT_Full |
4583 SUPPORTED_FIBRE;
4584
4585 cmd->port = PORT_FIBRE;
4586 }
4587 else {
4588 cmd->supported |= SUPPORTED_10baseT_Half |
4589 SUPPORTED_10baseT_Full |
4590 SUPPORTED_100baseT_Half |
4591 SUPPORTED_100baseT_Full |
4592 SUPPORTED_1000baseT_Full |
4593 SUPPORTED_TP;
4594
4595 cmd->port = PORT_TP;
4596 }
4597
4598 cmd->advertising = bp->advertising;
4599
4600 if (bp->autoneg & AUTONEG_SPEED) {
4601 cmd->autoneg = AUTONEG_ENABLE;
4602 }
4603 else {
4604 cmd->autoneg = AUTONEG_DISABLE;
4605 }
4606
4607 if (netif_carrier_ok(dev)) {
4608 cmd->speed = bp->line_speed;
4609 cmd->duplex = bp->duplex;
4610 }
4611 else {
4612 cmd->speed = -1;
4613 cmd->duplex = -1;
4614 }
4615
4616 cmd->transceiver = XCVR_INTERNAL;
4617 cmd->phy_address = bp->phy_addr;
4618
4619 return 0;
4620 }
4621
4622 static int
4623 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4624 {
4625 struct bnx2 *bp = dev->priv;
4626 u8 autoneg = bp->autoneg;
4627 u8 req_duplex = bp->req_duplex;
4628 u16 req_line_speed = bp->req_line_speed;
4629 u32 advertising = bp->advertising;
4630
4631 if (cmd->autoneg == AUTONEG_ENABLE) {
4632 autoneg |= AUTONEG_SPEED;
4633
4634 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4635
4636 /* allow advertising 1 speed */
4637 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4638 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4639 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4640 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4641
4642 if (bp->phy_flags & PHY_SERDES_FLAG)
4643 return -EINVAL;
4644
4645 advertising = cmd->advertising;
4646
4647 }
4648 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4649 advertising = cmd->advertising;
4650 }
4651 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4652 return -EINVAL;
4653 }
4654 else {
4655 if (bp->phy_flags & PHY_SERDES_FLAG) {
4656 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4657 }
4658 else {
4659 advertising = ETHTOOL_ALL_COPPER_SPEED;
4660 }
4661 }
4662 advertising |= ADVERTISED_Autoneg;
4663 }
4664 else {
4665 if (bp->phy_flags & PHY_SERDES_FLAG) {
4666 if ((cmd->speed != SPEED_1000) ||
4667 (cmd->duplex != DUPLEX_FULL)) {
4668 return -EINVAL;
4669 }
4670 }
4671 else if (cmd->speed == SPEED_1000) {
4672 return -EINVAL;
4673 }
4674 autoneg &= ~AUTONEG_SPEED;
4675 req_line_speed = cmd->speed;
4676 req_duplex = cmd->duplex;
4677 advertising = 0;
4678 }
4679
4680 bp->autoneg = autoneg;
4681 bp->advertising = advertising;
4682 bp->req_line_speed = req_line_speed;
4683 bp->req_duplex = req_duplex;
4684
4685 spin_lock_bh(&bp->phy_lock);
4686
4687 bnx2_setup_phy(bp);
4688
4689 spin_unlock_bh(&bp->phy_lock);
4690
4691 return 0;
4692 }
4693
4694 static void
4695 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4696 {
4697 struct bnx2 *bp = dev->priv;
4698
4699 strcpy(info->driver, DRV_MODULE_NAME);
4700 strcpy(info->version, DRV_MODULE_VERSION);
4701 strcpy(info->bus_info, pci_name(bp->pdev));
4702 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4703 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4704 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4705 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4706 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4707 info->fw_version[7] = 0;
4708 }
4709
4710 static void
4711 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4712 {
4713 struct bnx2 *bp = dev->priv;
4714
4715 if (bp->flags & NO_WOL_FLAG) {
4716 wol->supported = 0;
4717 wol->wolopts = 0;
4718 }
4719 else {
4720 wol->supported = WAKE_MAGIC;
4721 if (bp->wol)
4722 wol->wolopts = WAKE_MAGIC;
4723 else
4724 wol->wolopts = 0;
4725 }
4726 memset(&wol->sopass, 0, sizeof(wol->sopass));
4727 }
4728
4729 static int
4730 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4731 {
4732 struct bnx2 *bp = dev->priv;
4733
4734 if (wol->wolopts & ~WAKE_MAGIC)
4735 return -EINVAL;
4736
4737 if (wol->wolopts & WAKE_MAGIC) {
4738 if (bp->flags & NO_WOL_FLAG)
4739 return -EINVAL;
4740
4741 bp->wol = 1;
4742 }
4743 else {
4744 bp->wol = 0;
4745 }
4746 return 0;
4747 }
4748
4749 static int
4750 bnx2_nway_reset(struct net_device *dev)
4751 {
4752 struct bnx2 *bp = dev->priv;
4753 u32 bmcr;
4754
4755 if (!(bp->autoneg & AUTONEG_SPEED)) {
4756 return -EINVAL;
4757 }
4758
4759 spin_lock_bh(&bp->phy_lock);
4760
4761 /* Force a link down visible on the other side */
4762 if (bp->phy_flags & PHY_SERDES_FLAG) {
4763 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4764 spin_unlock_bh(&bp->phy_lock);
4765
4766 msleep(20);
4767
4768 spin_lock_bh(&bp->phy_lock);
4769 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4770 bp->current_interval = SERDES_AN_TIMEOUT;
4771 bp->serdes_an_pending = 1;
4772 mod_timer(&bp->timer, jiffies + bp->current_interval);
4773 }
4774 }
4775
4776 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4777 bmcr &= ~BMCR_LOOPBACK;
4778 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4779
4780 spin_unlock_bh(&bp->phy_lock);
4781
4782 return 0;
4783 }
4784
4785 static int
4786 bnx2_get_eeprom_len(struct net_device *dev)
4787 {
4788 struct bnx2 *bp = dev->priv;
4789
4790 if (bp->flash_info == 0)
4791 return 0;
4792
4793 return (int) bp->flash_info->total_size;
4794 }
4795
4796 static int
4797 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4798 u8 *eebuf)
4799 {
4800 struct bnx2 *bp = dev->priv;
4801 int rc;
4802
4803 /* parameters already validated in ethtool_get_eeprom */
4804
4805 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4806
4807 return rc;
4808 }
4809
4810 static int
4811 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4812 u8 *eebuf)
4813 {
4814 struct bnx2 *bp = dev->priv;
4815 int rc;
4816
4817 /* parameters already validated in ethtool_set_eeprom */
4818
4819 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4820
4821 return rc;
4822 }
4823
4824 static int
4825 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4826 {
4827 struct bnx2 *bp = dev->priv;
4828
4829 memset(coal, 0, sizeof(struct ethtool_coalesce));
4830
4831 coal->rx_coalesce_usecs = bp->rx_ticks;
4832 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4833 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4834 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4835
4836 coal->tx_coalesce_usecs = bp->tx_ticks;
4837 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4838 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4839 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4840
4841 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4842
4843 return 0;
4844 }
4845
4846 static int
4847 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4848 {
4849 struct bnx2 *bp = dev->priv;
4850
4851 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4852 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4853
4854 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4855 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4856
4857 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4858 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4859
4860 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4861 if (bp->rx_quick_cons_trip_int > 0xff)
4862 bp->rx_quick_cons_trip_int = 0xff;
4863
4864 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4865 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4866
4867 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4868 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4869
4870 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4871 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4872
4873 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4874 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4875 0xff;
4876
4877 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4878 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4879 bp->stats_ticks &= 0xffff00;
4880
4881 if (netif_running(bp->dev)) {
4882 bnx2_netif_stop(bp);
4883 bnx2_init_nic(bp);
4884 bnx2_netif_start(bp);
4885 }
4886
4887 return 0;
4888 }
4889
4890 static void
4891 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4892 {
4893 struct bnx2 *bp = dev->priv;
4894
4895 ering->rx_max_pending = MAX_RX_DESC_CNT;
4896 ering->rx_mini_max_pending = 0;
4897 ering->rx_jumbo_max_pending = 0;
4898
4899 ering->rx_pending = bp->rx_ring_size;
4900 ering->rx_mini_pending = 0;
4901 ering->rx_jumbo_pending = 0;
4902
4903 ering->tx_max_pending = MAX_TX_DESC_CNT;
4904 ering->tx_pending = bp->tx_ring_size;
4905 }
4906
4907 static int
4908 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4909 {
4910 struct bnx2 *bp = dev->priv;
4911
4912 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4913 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4914 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4915
4916 return -EINVAL;
4917 }
4918 bp->rx_ring_size = ering->rx_pending;
4919 bp->tx_ring_size = ering->tx_pending;
4920
4921 if (netif_running(bp->dev)) {
4922 bnx2_netif_stop(bp);
4923 bnx2_init_nic(bp);
4924 bnx2_netif_start(bp);
4925 }
4926
4927 return 0;
4928 }
4929
4930 static void
4931 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4932 {
4933 struct bnx2 *bp = dev->priv;
4934
4935 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4936 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4937 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4938 }
4939
4940 static int
4941 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4942 {
4943 struct bnx2 *bp = dev->priv;
4944
4945 bp->req_flow_ctrl = 0;
4946 if (epause->rx_pause)
4947 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4948 if (epause->tx_pause)
4949 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4950
4951 if (epause->autoneg) {
4952 bp->autoneg |= AUTONEG_FLOW_CTRL;
4953 }
4954 else {
4955 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4956 }
4957
4958 spin_lock_bh(&bp->phy_lock);
4959
4960 bnx2_setup_phy(bp);
4961
4962 spin_unlock_bh(&bp->phy_lock);
4963
4964 return 0;
4965 }
4966
4967 static u32
4968 bnx2_get_rx_csum(struct net_device *dev)
4969 {
4970 struct bnx2 *bp = dev->priv;
4971
4972 return bp->rx_csum;
4973 }
4974
4975 static int
4976 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4977 {
4978 struct bnx2 *bp = dev->priv;
4979
4980 bp->rx_csum = data;
4981 return 0;
4982 }
4983
4984 #define BNX2_NUM_STATS 45
4985
4986 static struct {
4987 char string[ETH_GSTRING_LEN];
4988 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4989 { "rx_bytes" },
4990 { "rx_error_bytes" },
4991 { "tx_bytes" },
4992 { "tx_error_bytes" },
4993 { "rx_ucast_packets" },
4994 { "rx_mcast_packets" },
4995 { "rx_bcast_packets" },
4996 { "tx_ucast_packets" },
4997 { "tx_mcast_packets" },
4998 { "tx_bcast_packets" },
4999 { "tx_mac_errors" },
5000 { "tx_carrier_errors" },
5001 { "rx_crc_errors" },
5002 { "rx_align_errors" },
5003 { "tx_single_collisions" },
5004 { "tx_multi_collisions" },
5005 { "tx_deferred" },
5006 { "tx_excess_collisions" },
5007 { "tx_late_collisions" },
5008 { "tx_total_collisions" },
5009 { "rx_fragments" },
5010 { "rx_jabbers" },
5011 { "rx_undersize_packets" },
5012 { "rx_oversize_packets" },
5013 { "rx_64_byte_packets" },
5014 { "rx_65_to_127_byte_packets" },
5015 { "rx_128_to_255_byte_packets" },
5016 { "rx_256_to_511_byte_packets" },
5017 { "rx_512_to_1023_byte_packets" },
5018 { "rx_1024_to_1522_byte_packets" },
5019 { "rx_1523_to_9022_byte_packets" },
5020 { "tx_64_byte_packets" },
5021 { "tx_65_to_127_byte_packets" },
5022 { "tx_128_to_255_byte_packets" },
5023 { "tx_256_to_511_byte_packets" },
5024 { "tx_512_to_1023_byte_packets" },
5025 { "tx_1024_to_1522_byte_packets" },
5026 { "tx_1523_to_9022_byte_packets" },
5027 { "rx_xon_frames" },
5028 { "rx_xoff_frames" },
5029 { "tx_xon_frames" },
5030 { "tx_xoff_frames" },
5031 { "rx_mac_ctrl_frames" },
5032 { "rx_filtered_packets" },
5033 { "rx_discards" },
5034 };
5035
5036 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5037
5038 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5039 STATS_OFFSET32(stat_IfHCInOctets_hi),
5040 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5041 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5042 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5043 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5044 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5045 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5046 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5047 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5048 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5049 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5050 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5051 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5052 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5053 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5054 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5055 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5056 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5057 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5058 STATS_OFFSET32(stat_EtherStatsCollisions),
5059 STATS_OFFSET32(stat_EtherStatsFragments),
5060 STATS_OFFSET32(stat_EtherStatsJabbers),
5061 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5062 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5063 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5064 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5065 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5066 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5067 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5068 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5069 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5070 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5071 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5072 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5073 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5074 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5075 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5076 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5077 STATS_OFFSET32(stat_XonPauseFramesReceived),
5078 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5079 STATS_OFFSET32(stat_OutXonSent),
5080 STATS_OFFSET32(stat_OutXoffSent),
5081 STATS_OFFSET32(stat_MacControlFramesReceived),
5082 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5083 STATS_OFFSET32(stat_IfInMBUFDiscards),
5084 };
5085
5086 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5087 * skipped because of errata.
5088 */
5089 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5090 8,0,8,8,8,8,8,8,8,8,
5091 4,0,4,4,4,4,4,4,4,4,
5092 4,4,4,4,4,4,4,4,4,4,
5093 4,4,4,4,4,4,4,4,4,4,
5094 4,4,4,4,4,
5095 };
5096
5097 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5098 8,0,8,8,8,8,8,8,8,8,
5099 4,4,4,4,4,4,4,4,4,4,
5100 4,4,4,4,4,4,4,4,4,4,
5101 4,4,4,4,4,4,4,4,4,4,
5102 4,4,4,4,4,
5103 };
5104
5105 #define BNX2_NUM_TESTS 6
5106
5107 static struct {
5108 char string[ETH_GSTRING_LEN];
5109 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5110 { "register_test (offline)" },
5111 { "memory_test (offline)" },
5112 { "loopback_test (offline)" },
5113 { "nvram_test (online)" },
5114 { "interrupt_test (online)" },
5115 { "link_test (online)" },
5116 };
5117
5118 static int
5119 bnx2_self_test_count(struct net_device *dev)
5120 {
5121 return BNX2_NUM_TESTS;
5122 }
5123
5124 static void
5125 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5126 {
5127 struct bnx2 *bp = dev->priv;
5128
5129 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5130 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5131 bnx2_netif_stop(bp);
5132 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5133 bnx2_free_skbs(bp);
5134
5135 if (bnx2_test_registers(bp) != 0) {
5136 buf[0] = 1;
5137 etest->flags |= ETH_TEST_FL_FAILED;
5138 }
5139 if (bnx2_test_memory(bp) != 0) {
5140 buf[1] = 1;
5141 etest->flags |= ETH_TEST_FL_FAILED;
5142 }
5143 if (bnx2_test_loopback(bp) != 0) {
5144 buf[2] = 1;
5145 etest->flags |= ETH_TEST_FL_FAILED;
5146 }
5147
5148 if (!netif_running(bp->dev)) {
5149 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5150 }
5151 else {
5152 bnx2_init_nic(bp);
5153 bnx2_netif_start(bp);
5154 }
5155
5156 /* wait for link up */
5157 msleep_interruptible(3000);
5158 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5159 msleep_interruptible(4000);
5160 }
5161
5162 if (bnx2_test_nvram(bp) != 0) {
5163 buf[3] = 1;
5164 etest->flags |= ETH_TEST_FL_FAILED;
5165 }
5166 if (bnx2_test_intr(bp) != 0) {
5167 buf[4] = 1;
5168 etest->flags |= ETH_TEST_FL_FAILED;
5169 }
5170
5171 if (bnx2_test_link(bp) != 0) {
5172 buf[5] = 1;
5173 etest->flags |= ETH_TEST_FL_FAILED;
5174
5175 }
5176 }
5177
5178 static void
5179 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5180 {
5181 switch (stringset) {
5182 case ETH_SS_STATS:
5183 memcpy(buf, bnx2_stats_str_arr,
5184 sizeof(bnx2_stats_str_arr));
5185 break;
5186 case ETH_SS_TEST:
5187 memcpy(buf, bnx2_tests_str_arr,
5188 sizeof(bnx2_tests_str_arr));
5189 break;
5190 }
5191 }
5192
5193 static int
5194 bnx2_get_stats_count(struct net_device *dev)
5195 {
5196 return BNX2_NUM_STATS;
5197 }
5198
5199 static void
5200 bnx2_get_ethtool_stats(struct net_device *dev,
5201 struct ethtool_stats *stats, u64 *buf)
5202 {
5203 struct bnx2 *bp = dev->priv;
5204 int i;
5205 u32 *hw_stats = (u32 *) bp->stats_blk;
5206 u8 *stats_len_arr = NULL;
5207
5208 if (hw_stats == NULL) {
5209 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5210 return;
5211 }
5212
5213 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5214 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5215 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5216 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5217 stats_len_arr = bnx2_5706_stats_len_arr;
5218 else
5219 stats_len_arr = bnx2_5708_stats_len_arr;
5220
5221 for (i = 0; i < BNX2_NUM_STATS; i++) {
5222 if (stats_len_arr[i] == 0) {
5223 /* skip this counter */
5224 buf[i] = 0;
5225 continue;
5226 }
5227 if (stats_len_arr[i] == 4) {
5228 /* 4-byte counter */
5229 buf[i] = (u64)
5230 *(hw_stats + bnx2_stats_offset_arr[i]);
5231 continue;
5232 }
5233 /* 8-byte counter */
5234 buf[i] = (((u64) *(hw_stats +
5235 bnx2_stats_offset_arr[i])) << 32) +
5236 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5237 }
5238 }
5239
5240 static int
5241 bnx2_phys_id(struct net_device *dev, u32 data)
5242 {
5243 struct bnx2 *bp = dev->priv;
5244 int i;
5245 u32 save;
5246
5247 if (data == 0)
5248 data = 2;
5249
5250 save = REG_RD(bp, BNX2_MISC_CFG);
5251 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5252
5253 for (i = 0; i < (data * 2); i++) {
5254 if ((i % 2) == 0) {
5255 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5256 }
5257 else {
5258 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5259 BNX2_EMAC_LED_1000MB_OVERRIDE |
5260 BNX2_EMAC_LED_100MB_OVERRIDE |
5261 BNX2_EMAC_LED_10MB_OVERRIDE |
5262 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5263 BNX2_EMAC_LED_TRAFFIC);
5264 }
5265 msleep_interruptible(500);
5266 if (signal_pending(current))
5267 break;
5268 }
5269 REG_WR(bp, BNX2_EMAC_LED, 0);
5270 REG_WR(bp, BNX2_MISC_CFG, save);
5271 return 0;
5272 }
5273
5274 static struct ethtool_ops bnx2_ethtool_ops = {
5275 .get_settings = bnx2_get_settings,
5276 .set_settings = bnx2_set_settings,
5277 .get_drvinfo = bnx2_get_drvinfo,
5278 .get_wol = bnx2_get_wol,
5279 .set_wol = bnx2_set_wol,
5280 .nway_reset = bnx2_nway_reset,
5281 .get_link = ethtool_op_get_link,
5282 .get_eeprom_len = bnx2_get_eeprom_len,
5283 .get_eeprom = bnx2_get_eeprom,
5284 .set_eeprom = bnx2_set_eeprom,
5285 .get_coalesce = bnx2_get_coalesce,
5286 .set_coalesce = bnx2_set_coalesce,
5287 .get_ringparam = bnx2_get_ringparam,
5288 .set_ringparam = bnx2_set_ringparam,
5289 .get_pauseparam = bnx2_get_pauseparam,
5290 .set_pauseparam = bnx2_set_pauseparam,
5291 .get_rx_csum = bnx2_get_rx_csum,
5292 .set_rx_csum = bnx2_set_rx_csum,
5293 .get_tx_csum = ethtool_op_get_tx_csum,
5294 .set_tx_csum = ethtool_op_set_tx_csum,
5295 .get_sg = ethtool_op_get_sg,
5296 .set_sg = ethtool_op_set_sg,
5297 #ifdef BCM_TSO
5298 .get_tso = ethtool_op_get_tso,
5299 .set_tso = ethtool_op_set_tso,
5300 #endif
5301 .self_test_count = bnx2_self_test_count,
5302 .self_test = bnx2_self_test,
5303 .get_strings = bnx2_get_strings,
5304 .phys_id = bnx2_phys_id,
5305 .get_stats_count = bnx2_get_stats_count,
5306 .get_ethtool_stats = bnx2_get_ethtool_stats,
5307 .get_perm_addr = ethtool_op_get_perm_addr,
5308 };
5309
5310 /* Called with rtnl_lock */
5311 static int
5312 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5313 {
5314 struct mii_ioctl_data *data = if_mii(ifr);
5315 struct bnx2 *bp = dev->priv;
5316 int err;
5317
5318 switch(cmd) {
5319 case SIOCGMIIPHY:
5320 data->phy_id = bp->phy_addr;
5321
5322 /* fallthru */
5323 case SIOCGMIIREG: {
5324 u32 mii_regval;
5325
5326 spin_lock_bh(&bp->phy_lock);
5327 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5328 spin_unlock_bh(&bp->phy_lock);
5329
5330 data->val_out = mii_regval;
5331
5332 return err;
5333 }
5334
5335 case SIOCSMIIREG:
5336 if (!capable(CAP_NET_ADMIN))
5337 return -EPERM;
5338
5339 spin_lock_bh(&bp->phy_lock);
5340 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5341 spin_unlock_bh(&bp->phy_lock);
5342
5343 return err;
5344
5345 default:
5346 /* do nothing */
5347 break;
5348 }
5349 return -EOPNOTSUPP;
5350 }
5351
5352 /* Called with rtnl_lock */
5353 static int
5354 bnx2_change_mac_addr(struct net_device *dev, void *p)
5355 {
5356 struct sockaddr *addr = p;
5357 struct bnx2 *bp = dev->priv;
5358
5359 if (!is_valid_ether_addr(addr->sa_data))
5360 return -EINVAL;
5361
5362 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5363 if (netif_running(dev))
5364 bnx2_set_mac_addr(bp);
5365
5366 return 0;
5367 }
5368
5369 /* Called with rtnl_lock */
5370 static int
5371 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5372 {
5373 struct bnx2 *bp = dev->priv;
5374
5375 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5376 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5377 return -EINVAL;
5378
5379 dev->mtu = new_mtu;
5380 if (netif_running(dev)) {
5381 bnx2_netif_stop(bp);
5382
5383 bnx2_init_nic(bp);
5384
5385 bnx2_netif_start(bp);
5386 }
5387 return 0;
5388 }
5389
5390 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5391 static void
5392 poll_bnx2(struct net_device *dev)
5393 {
5394 struct bnx2 *bp = dev->priv;
5395
5396 disable_irq(bp->pdev->irq);
5397 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5398 enable_irq(bp->pdev->irq);
5399 }
5400 #endif
5401
5402 static int __devinit
5403 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5404 {
5405 struct bnx2 *bp;
5406 unsigned long mem_len;
5407 int rc;
5408 u32 reg;
5409
5410 SET_MODULE_OWNER(dev);
5411 SET_NETDEV_DEV(dev, &pdev->dev);
5412 bp = dev->priv;
5413
5414 bp->flags = 0;
5415 bp->phy_flags = 0;
5416
5417 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5418 rc = pci_enable_device(pdev);
5419 if (rc) {
5420 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5421 goto err_out;
5422 }
5423
5424 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5425 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5426 "aborting.\n");
5427 rc = -ENODEV;
5428 goto err_out_disable;
5429 }
5430
5431 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5432 if (rc) {
5433 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5434 goto err_out_disable;
5435 }
5436
5437 pci_set_master(pdev);
5438
5439 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5440 if (bp->pm_cap == 0) {
5441 printk(KERN_ERR PFX "Cannot find power management capability, "
5442 "aborting.\n");
5443 rc = -EIO;
5444 goto err_out_release;
5445 }
5446
5447 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5448 if (bp->pcix_cap == 0) {
5449 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5450 rc = -EIO;
5451 goto err_out_release;
5452 }
5453
5454 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5455 bp->flags |= USING_DAC_FLAG;
5456 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5457 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5458 "failed, aborting.\n");
5459 rc = -EIO;
5460 goto err_out_release;
5461 }
5462 }
5463 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5464 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5465 rc = -EIO;
5466 goto err_out_release;
5467 }
5468
5469 bp->dev = dev;
5470 bp->pdev = pdev;
5471
5472 spin_lock_init(&bp->phy_lock);
5473 spin_lock_init(&bp->tx_lock);
5474 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5475
5476 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5477 mem_len = MB_GET_CID_ADDR(17);
5478 dev->mem_end = dev->mem_start + mem_len;
5479 dev->irq = pdev->irq;
5480
5481 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5482
5483 if (!bp->regview) {
5484 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5485 rc = -ENOMEM;
5486 goto err_out_release;
5487 }
5488
5489 /* Configure byte swap and enable write to the reg_window registers.
5490 * Rely on CPU to do target byte swapping on big endian systems
5491 * The chip's target access swapping will not swap all accesses
5492 */
5493 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5494 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5495 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5496
5497 bnx2_set_power_state(bp, PCI_D0);
5498
5499 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5500
5501 /* Get bus information. */
5502 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5503 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5504 u32 clkreg;
5505
5506 bp->flags |= PCIX_FLAG;
5507
5508 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5509
5510 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5511 switch (clkreg) {
5512 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5513 bp->bus_speed_mhz = 133;
5514 break;
5515
5516 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5517 bp->bus_speed_mhz = 100;
5518 break;
5519
5520 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5521 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5522 bp->bus_speed_mhz = 66;
5523 break;
5524
5525 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5526 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5527 bp->bus_speed_mhz = 50;
5528 break;
5529
5530 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5531 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5532 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5533 bp->bus_speed_mhz = 33;
5534 break;
5535 }
5536 }
5537 else {
5538 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5539 bp->bus_speed_mhz = 66;
5540 else
5541 bp->bus_speed_mhz = 33;
5542 }
5543
5544 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5545 bp->flags |= PCI_32BIT_FLAG;
5546
5547 /* 5706A0 may falsely detect SERR and PERR. */
5548 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5549 reg = REG_RD(bp, PCI_COMMAND);
5550 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5551 REG_WR(bp, PCI_COMMAND, reg);
5552 }
5553 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5554 !(bp->flags & PCIX_FLAG)) {
5555
5556 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5557 "aborting.\n");
5558 goto err_out_unmap;
5559 }
5560
5561 bnx2_init_nvram(bp);
5562
5563 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5564
5565 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5566 BNX2_SHM_HDR_SIGNATURE_SIG)
5567 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5568 else
5569 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5570
5571 /* Get the permanent MAC address. First we need to make sure the
5572 * firmware is actually running.
5573 */
5574 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5575
5576 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5577 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5578 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5579 rc = -ENODEV;
5580 goto err_out_unmap;
5581 }
5582
5583 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5584
5585 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5586 bp->mac_addr[0] = (u8) (reg >> 8);
5587 bp->mac_addr[1] = (u8) reg;
5588
5589 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5590 bp->mac_addr[2] = (u8) (reg >> 24);
5591 bp->mac_addr[3] = (u8) (reg >> 16);
5592 bp->mac_addr[4] = (u8) (reg >> 8);
5593 bp->mac_addr[5] = (u8) reg;
5594
5595 bp->tx_ring_size = MAX_TX_DESC_CNT;
5596 bp->rx_ring_size = 100;
5597
5598 bp->rx_csum = 1;
5599
5600 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5601
5602 bp->tx_quick_cons_trip_int = 20;
5603 bp->tx_quick_cons_trip = 20;
5604 bp->tx_ticks_int = 80;
5605 bp->tx_ticks = 80;
5606
5607 bp->rx_quick_cons_trip_int = 6;
5608 bp->rx_quick_cons_trip = 6;
5609 bp->rx_ticks_int = 18;
5610 bp->rx_ticks = 18;
5611
5612 bp->stats_ticks = 1000000 & 0xffff00;
5613
5614 bp->timer_interval = HZ;
5615 bp->current_interval = HZ;
5616
5617 bp->phy_addr = 1;
5618
5619 /* Disable WOL support if we are running on a SERDES chip. */
5620 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5621 bp->phy_flags |= PHY_SERDES_FLAG;
5622 bp->flags |= NO_WOL_FLAG;
5623 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5624 bp->phy_addr = 2;
5625 reg = REG_RD_IND(bp, bp->shmem_base +
5626 BNX2_SHARED_HW_CFG_CONFIG);
5627 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5628 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5629 }
5630 }
5631
5632 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5633 bp->tx_quick_cons_trip_int =
5634 bp->tx_quick_cons_trip;
5635 bp->tx_ticks_int = bp->tx_ticks;
5636 bp->rx_quick_cons_trip_int =
5637 bp->rx_quick_cons_trip;
5638 bp->rx_ticks_int = bp->rx_ticks;
5639 bp->comp_prod_trip_int = bp->comp_prod_trip;
5640 bp->com_ticks_int = bp->com_ticks;
5641 bp->cmd_ticks_int = bp->cmd_ticks;
5642 }
5643
5644 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5645 bp->req_line_speed = 0;
5646 if (bp->phy_flags & PHY_SERDES_FLAG) {
5647 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5648
5649 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5650 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5651 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5652 bp->autoneg = 0;
5653 bp->req_line_speed = bp->line_speed = SPEED_1000;
5654 bp->req_duplex = DUPLEX_FULL;
5655 }
5656 }
5657 else {
5658 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5659 }
5660
5661 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5662
5663 init_timer(&bp->timer);
5664 bp->timer.expires = RUN_AT(bp->timer_interval);
5665 bp->timer.data = (unsigned long) bp;
5666 bp->timer.function = bnx2_timer;
5667
5668 return 0;
5669
5670 err_out_unmap:
5671 if (bp->regview) {
5672 iounmap(bp->regview);
5673 bp->regview = NULL;
5674 }
5675
5676 err_out_release:
5677 pci_release_regions(pdev);
5678
5679 err_out_disable:
5680 pci_disable_device(pdev);
5681 pci_set_drvdata(pdev, NULL);
5682
5683 err_out:
5684 return rc;
5685 }
5686
5687 static int __devinit
5688 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5689 {
5690 static int version_printed = 0;
5691 struct net_device *dev = NULL;
5692 struct bnx2 *bp;
5693 int rc, i;
5694
5695 if (version_printed++ == 0)
5696 printk(KERN_INFO "%s", version);
5697
5698 /* dev zeroed in init_etherdev */
5699 dev = alloc_etherdev(sizeof(*bp));
5700
5701 if (!dev)
5702 return -ENOMEM;
5703
5704 rc = bnx2_init_board(pdev, dev);
5705 if (rc < 0) {
5706 free_netdev(dev);
5707 return rc;
5708 }
5709
5710 dev->open = bnx2_open;
5711 dev->hard_start_xmit = bnx2_start_xmit;
5712 dev->stop = bnx2_close;
5713 dev->get_stats = bnx2_get_stats;
5714 dev->set_multicast_list = bnx2_set_rx_mode;
5715 dev->do_ioctl = bnx2_ioctl;
5716 dev->set_mac_address = bnx2_change_mac_addr;
5717 dev->change_mtu = bnx2_change_mtu;
5718 dev->tx_timeout = bnx2_tx_timeout;
5719 dev->watchdog_timeo = TX_TIMEOUT;
5720 #ifdef BCM_VLAN
5721 dev->vlan_rx_register = bnx2_vlan_rx_register;
5722 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5723 #endif
5724 dev->poll = bnx2_poll;
5725 dev->ethtool_ops = &bnx2_ethtool_ops;
5726 dev->weight = 64;
5727
5728 bp = dev->priv;
5729
5730 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5731 dev->poll_controller = poll_bnx2;
5732 #endif
5733
5734 if ((rc = register_netdev(dev))) {
5735 printk(KERN_ERR PFX "Cannot register net device\n");
5736 if (bp->regview)
5737 iounmap(bp->regview);
5738 pci_release_regions(pdev);
5739 pci_disable_device(pdev);
5740 pci_set_drvdata(pdev, NULL);
5741 free_netdev(dev);
5742 return rc;
5743 }
5744
5745 pci_set_drvdata(pdev, dev);
5746
5747 memcpy(dev->dev_addr, bp->mac_addr, 6);
5748 memcpy(dev->perm_addr, bp->mac_addr, 6);
5749 bp->name = board_info[ent->driver_data].name,
5750 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5751 "IRQ %d, ",
5752 dev->name,
5753 bp->name,
5754 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5755 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5756 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5757 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5758 bp->bus_speed_mhz,
5759 dev->base_addr,
5760 bp->pdev->irq);
5761
5762 printk("node addr ");
5763 for (i = 0; i < 6; i++)
5764 printk("%2.2x", dev->dev_addr[i]);
5765 printk("\n");
5766
5767 dev->features |= NETIF_F_SG;
5768 if (bp->flags & USING_DAC_FLAG)
5769 dev->features |= NETIF_F_HIGHDMA;
5770 dev->features |= NETIF_F_IP_CSUM;
5771 #ifdef BCM_VLAN
5772 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5773 #endif
5774 #ifdef BCM_TSO
5775 dev->features |= NETIF_F_TSO;
5776 #endif
5777
5778 netif_carrier_off(bp->dev);
5779
5780 return 0;
5781 }
5782
5783 static void __devexit
5784 bnx2_remove_one(struct pci_dev *pdev)
5785 {
5786 struct net_device *dev = pci_get_drvdata(pdev);
5787 struct bnx2 *bp = dev->priv;
5788
5789 flush_scheduled_work();
5790
5791 unregister_netdev(dev);
5792
5793 if (bp->regview)
5794 iounmap(bp->regview);
5795
5796 free_netdev(dev);
5797 pci_release_regions(pdev);
5798 pci_disable_device(pdev);
5799 pci_set_drvdata(pdev, NULL);
5800 }
5801
5802 static int
5803 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5804 {
5805 struct net_device *dev = pci_get_drvdata(pdev);
5806 struct bnx2 *bp = dev->priv;
5807 u32 reset_code;
5808
5809 if (!netif_running(dev))
5810 return 0;
5811
5812 bnx2_netif_stop(bp);
5813 netif_device_detach(dev);
5814 del_timer_sync(&bp->timer);
5815 if (bp->wol)
5816 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5817 else
5818 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5819 bnx2_reset_chip(bp, reset_code);
5820 bnx2_free_skbs(bp);
5821 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5822 return 0;
5823 }
5824
5825 static int
5826 bnx2_resume(struct pci_dev *pdev)
5827 {
5828 struct net_device *dev = pci_get_drvdata(pdev);
5829 struct bnx2 *bp = dev->priv;
5830
5831 if (!netif_running(dev))
5832 return 0;
5833
5834 bnx2_set_power_state(bp, PCI_D0);
5835 netif_device_attach(dev);
5836 bnx2_init_nic(bp);
5837 bnx2_netif_start(bp);
5838 return 0;
5839 }
5840
5841 static struct pci_driver bnx2_pci_driver = {
5842 .name = DRV_MODULE_NAME,
5843 .id_table = bnx2_pci_tbl,
5844 .probe = bnx2_init_one,
5845 .remove = __devexit_p(bnx2_remove_one),
5846 .suspend = bnx2_suspend,
5847 .resume = bnx2_resume,
5848 };
5849
5850 static int __init bnx2_init(void)
5851 {
5852 return pci_module_init(&bnx2_pci_driver);
5853 }
5854
5855 static void __exit bnx2_cleanup(void)
5856 {
5857 pci_unregister_driver(&bnx2_pci_driver);
5858 }
5859
5860 module_init(bnx2_init);
5861 module_exit(bnx2_cleanup);
5862
5863
5864
WRT350N Kernel Patches