x86: introduce native_set_pte_atomic() on 64-bit too
[wrt350n-kernel.git] / include / asm-arm / arch-at91 / at91_ecc.h
blobff93df516d6df11c419bf4767c3860aa941d392a
1 /*
2 * include/asm-arm/arch-at91/at91_ecc.h
4 * Error Corrected Code Controller (ECC) - System peripherals regsters.
5 * Based on AT91SAM9260 datasheet revision B.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef AT91_ECC_H
14 #define AT91_ECC_H
16 #define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
17 #define AT91_ECC_RST (1 << 0) /* Reset parity */
19 #define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
20 #define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
21 #define AT91_ECC_PAGESIZE_528 (0)
22 #define AT91_ECC_PAGESIZE_1056 (1)
23 #define AT91_ECC_PAGESIZE_2112 (2)
24 #define AT91_ECC_PAGESIZE_4224 (3)
26 #define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
27 #define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
28 #define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
29 #define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
31 #define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
32 #define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
33 #define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
35 #define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
36 #define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
38 #endif