include/asm-powerpc/pasemi_dma.h

   1 /*
   2  * Copyright (C) 2006 PA Semi, Inc
   3  *
   4  * Hardware register layout and descriptor formats for the on-board
   5  * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
   6  * drivers.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  20  */
  21
  22 #ifndef ASM_PASEMI_DMA_H
  23 #define ASM_PASEMI_DMA_H
  24
  25 /* status register layout in IOB region, at 0xfb800000 */
  26 struct pasdma_status {
  27         u64 rx_sta[64];         /* RX channel status */
  28         u64 tx_sta[20];         /* TX channel status */
  29 };
  30
  31
  32 /* All these registers live in the PCI configuration space for the DMA PCI
  33  * device. Use the normal PCI config access functions for them.
  34  */
  35 enum {
  36         PAS_DMA_CAP_TXCH  = 0x44,       /* Transmit Channel Info      */
  37         PAS_DMA_CAP_RXCH  = 0x48,       /* Transmit Channel Info      */
  38         PAS_DMA_CAP_IFI   = 0x4c,       /* Interface Info             */
  39         PAS_DMA_COM_TXCMD = 0x100,      /* Transmit Command Register  */
  40         PAS_DMA_COM_TXSTA = 0x104,      /* Transmit Status Register   */
  41         PAS_DMA_COM_RXCMD = 0x108,      /* Receive Command Register   */
  42         PAS_DMA_COM_RXSTA = 0x10c,      /* Receive Status Register    */
  43 };
  44
  45
  46 #define PAS_DMA_CAP_TXCH_TCHN_M 0x00ff0000 /* # of TX channels */
  47 #define PAS_DMA_CAP_TXCH_TCHN_S 16
  48
  49 #define PAS_DMA_CAP_RXCH_RCHN_M 0x00ff0000 /* # of RX channels */
  50 #define PAS_DMA_CAP_RXCH_RCHN_S 16
  51
  52 #define PAS_DMA_CAP_IFI_IOFF_M  0xff000000 /* Cfg reg for intf pointers */
  53 #define PAS_DMA_CAP_IFI_IOFF_S  24
  54 #define PAS_DMA_CAP_IFI_NIN_M   0x00ff0000 /* # of interfaces */
  55 #define PAS_DMA_CAP_IFI_NIN_S   16
  56
  57 #define PAS_DMA_COM_TXCMD_EN    0x00000001 /* enable */
  58 #define PAS_DMA_COM_TXSTA_ACT   0x00000001 /* active */
  59 #define PAS_DMA_COM_RXCMD_EN    0x00000001 /* enable */
  60 #define PAS_DMA_COM_RXSTA_ACT   0x00000001 /* active */
  61
  62
  63 /* Per-interface and per-channel registers */
  64 #define _PAS_DMA_RXINT_STRIDE           0x20
  65 #define PAS_DMA_RXINT_RCMDSTA(i)        (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
  66 #define    PAS_DMA_RXINT_RCMDSTA_EN     0x00000001
  67 #define    PAS_DMA_RXINT_RCMDSTA_ST     0x00000002
  68 #define    PAS_DMA_RXINT_RCMDSTA_MBT    0x00000008
  69 #define    PAS_DMA_RXINT_RCMDSTA_MDR    0x00000010
  70 #define    PAS_DMA_RXINT_RCMDSTA_MOO    0x00000020
  71 #define    PAS_DMA_RXINT_RCMDSTA_MBP    0x00000040
  72 #define    PAS_DMA_RXINT_RCMDSTA_BT     0x00000800
  73 #define    PAS_DMA_RXINT_RCMDSTA_DR     0x00001000
  74 #define    PAS_DMA_RXINT_RCMDSTA_OO     0x00002000
  75 #define    PAS_DMA_RXINT_RCMDSTA_BP     0x00004000
  76 #define    PAS_DMA_RXINT_RCMDSTA_TB     0x00008000
  77 #define    PAS_DMA_RXINT_RCMDSTA_ACT    0x00010000
  78 #define    PAS_DMA_RXINT_RCMDSTA_DROPS_M        0xfffe0000
  79 #define    PAS_DMA_RXINT_RCMDSTA_DROPS_S        17
  80 #define PAS_DMA_RXINT_CFG(i)            (0x204+(i)*_PAS_DMA_RXINT_STRIDE)
  81 #define    PAS_DMA_RXINT_CFG_RBP        0x80000000
  82 #define    PAS_DMA_RXINT_CFG_ITRR       0x40000000
  83 #define    PAS_DMA_RXINT_CFG_DHL_M      0x07000000
  84 #define    PAS_DMA_RXINT_CFG_DHL_S      24
  85 #define    PAS_DMA_RXINT_CFG_DHL(x)     (((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
  86                                          PAS_DMA_RXINT_CFG_DHL_M)
  87 #define    PAS_DMA_RXINT_CFG_ITR        0x00400000
  88 #define    PAS_DMA_RXINT_CFG_LW         0x00200000
  89 #define    PAS_DMA_RXINT_CFG_L2         0x00100000
  90 #define    PAS_DMA_RXINT_CFG_HEN        0x00080000
  91 #define    PAS_DMA_RXINT_CFG_WIF        0x00000002
  92 #define    PAS_DMA_RXINT_CFG_WIL        0x00000001
  93
  94 #define PAS_DMA_RXINT_INCR(i)           (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
  95 #define    PAS_DMA_RXINT_INCR_INCR_M    0x0000ffff
  96 #define    PAS_DMA_RXINT_INCR_INCR_S    0
  97 #define    PAS_DMA_RXINT_INCR_INCR(x)   ((x) & 0x0000ffff)
  98 #define PAS_DMA_RXINT_BASEL(i)          (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
  99 #define    PAS_DMA_RXINT_BASEL_BRBL(x)  ((x) & ~0x3f)
 100 #define PAS_DMA_RXINT_BASEU(i)          (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
 101 #define    PAS_DMA_RXINT_BASEU_BRBH(x)  ((x) & 0xfff)
 102 #define    PAS_DMA_RXINT_BASEU_SIZ_M    0x3fff0000      /* # of cache lines worth of buffer ring */
 103 #define    PAS_DMA_RXINT_BASEU_SIZ_S    16              /* 0 = 16K */
 104 #define    PAS_DMA_RXINT_BASEU_SIZ(x)   (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
 105                                          PAS_DMA_RXINT_BASEU_SIZ_M)
 106
 107
 108 #define _PAS_DMA_TXCHAN_STRIDE  0x20    /* Size per channel             */
 109 #define _PAS_DMA_TXCHAN_TCMDSTA 0x300   /* Command / Status             */
 110 #define _PAS_DMA_TXCHAN_CFG     0x304   /* Configuration                */
 111 #define _PAS_DMA_TXCHAN_DSCRBU  0x308   /* Descriptor BU Allocation     */
 112 #define _PAS_DMA_TXCHAN_INCR    0x310   /* Descriptor increment         */
 113 #define _PAS_DMA_TXCHAN_CNT     0x314   /* Descriptor count/offset      */
 114 #define _PAS_DMA_TXCHAN_BASEL   0x318   /* Descriptor ring base (low)   */
 115 #define _PAS_DMA_TXCHAN_BASEU   0x31c   /*                      (high)  */
 116 #define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
 117 #define    PAS_DMA_TXCHAN_TCMDSTA_EN    0x00000001      /* Enabled */
 118 #define    PAS_DMA_TXCHAN_TCMDSTA_ST    0x00000002      /* Stop interface */
 119 #define    PAS_DMA_TXCHAN_TCMDSTA_ACT   0x00010000      /* Active */
 120 #define    PAS_DMA_TXCHAN_TCMDSTA_SZ    0x00000800
 121 #define    PAS_DMA_TXCHAN_TCMDSTA_DB    0x00000400
 122 #define    PAS_DMA_TXCHAN_TCMDSTA_DE    0x00000200
 123 #define    PAS_DMA_TXCHAN_TCMDSTA_DA    0x00000100
 124 #define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
 125 #define    PAS_DMA_TXCHAN_CFG_TY_IFACE  0x00000000      /* Type = interface */
 126 #define    PAS_DMA_TXCHAN_CFG_TATTR_M   0x0000003c
 127 #define    PAS_DMA_TXCHAN_CFG_TATTR_S   2
 128 #define    PAS_DMA_TXCHAN_CFG_TATTR(x)  (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
 129                                          PAS_DMA_TXCHAN_CFG_TATTR_M)
 130 #define    PAS_DMA_TXCHAN_CFG_WT_M      0x000001c0
 131 #define    PAS_DMA_TXCHAN_CFG_WT_S      6
 132 #define    PAS_DMA_TXCHAN_CFG_WT(x)     (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
 133                                          PAS_DMA_TXCHAN_CFG_WT_M)
 134 #define    PAS_DMA_TXCHAN_CFG_TRD       0x00010000      /* translate data */
 135 #define    PAS_DMA_TXCHAN_CFG_TRR       0x00008000      /* translate rings */
 136 #define    PAS_DMA_TXCHAN_CFG_UP        0x00004000      /* update tx descr when sent */
 137 #define    PAS_DMA_TXCHAN_CFG_CL        0x00002000      /* Clean last line */
 138 #define    PAS_DMA_TXCHAN_CFG_CF        0x00001000      /* Clean first line */
 139 #define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
 140 #define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
 141 #define    PAS_DMA_TXCHAN_BASEL_BRBL_M  0xffffffc0
 142 #define    PAS_DMA_TXCHAN_BASEL_BRBL_S  0
 143 #define    PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
 144                                          PAS_DMA_TXCHAN_BASEL_BRBL_M)
 145 #define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
 146 #define    PAS_DMA_TXCHAN_BASEU_BRBH_M  0x00000fff
 147 #define    PAS_DMA_TXCHAN_BASEU_BRBH_S  0
 148 #define    PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
 149                                          PAS_DMA_TXCHAN_BASEU_BRBH_M)
 150 /* # of cache lines worth of buffer ring */
 151 #define    PAS_DMA_TXCHAN_BASEU_SIZ_M   0x3fff0000
 152 #define    PAS_DMA_TXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
 153 #define    PAS_DMA_TXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
 154                                          PAS_DMA_TXCHAN_BASEU_SIZ_M)
 155
 156 #define _PAS_DMA_RXCHAN_STRIDE  0x20    /* Size per channel             */
 157 #define _PAS_DMA_RXCHAN_CCMDSTA 0x800   /* Command / Status             */
 158 #define _PAS_DMA_RXCHAN_CFG     0x804   /* Configuration                */
 159 #define _PAS_DMA_RXCHAN_INCR    0x810   /* Descriptor increment         */
 160 #define _PAS_DMA_RXCHAN_CNT     0x814   /* Descriptor count/offset      */
 161 #define _PAS_DMA_RXCHAN_BASEL   0x818   /* Descriptor ring base (low)   */
 162 #define _PAS_DMA_RXCHAN_BASEU   0x81c   /*                      (high)  */
 163 #define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
 164 #define    PAS_DMA_RXCHAN_CCMDSTA_EN    0x00000001      /* Enabled */
 165 #define    PAS_DMA_RXCHAN_CCMDSTA_ST    0x00000002      /* Stop interface */
 166 #define    PAS_DMA_RXCHAN_CCMDSTA_ACT   0x00010000      /* Active */
 167 #define    PAS_DMA_RXCHAN_CCMDSTA_DU    0x00020000
 168 #define    PAS_DMA_RXCHAN_CCMDSTA_OD    0x00002000
 169 #define    PAS_DMA_RXCHAN_CCMDSTA_FD    0x00001000
 170 #define    PAS_DMA_RXCHAN_CCMDSTA_DT    0x00000800
 171 #define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
 172 #define    PAS_DMA_RXCHAN_CFG_CTR       0x00000400
 173 #define    PAS_DMA_RXCHAN_CFG_HBU_M     0x00000380
 174 #define    PAS_DMA_RXCHAN_CFG_HBU_S     7
 175 #define    PAS_DMA_RXCHAN_CFG_HBU(x)    (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
 176                                          PAS_DMA_RXCHAN_CFG_HBU_M)
 177 #define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
 178 #define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
 179 #define    PAS_DMA_RXCHAN_BASEL_BRBL_M  0xffffffc0
 180 #define    PAS_DMA_RXCHAN_BASEL_BRBL_S  0
 181 #define    PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
 182                                          PAS_DMA_RXCHAN_BASEL_BRBL_M)
 183 #define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
 184 #define    PAS_DMA_RXCHAN_BASEU_BRBH_M  0x00000fff
 185 #define    PAS_DMA_RXCHAN_BASEU_BRBH_S  0
 186 #define    PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
 187                                          PAS_DMA_RXCHAN_BASEU_BRBH_M)
 188 /* # of cache lines worth of buffer ring */
 189 #define    PAS_DMA_RXCHAN_BASEU_SIZ_M   0x3fff0000
 190 #define    PAS_DMA_RXCHAN_BASEU_SIZ_S   16              /* 0 = 16K */
 191 #define    PAS_DMA_RXCHAN_BASEU_SIZ(x)  (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
 192                                          PAS_DMA_RXCHAN_BASEU_SIZ_M)
 193
 194 #define    PAS_STATUS_PCNT_M            0x000000000000ffffull
 195 #define    PAS_STATUS_PCNT_S            0
 196 #define    PAS_STATUS_DCNT_M            0x00000000ffff0000ull
 197 #define    PAS_STATUS_DCNT_S            16
 198 #define    PAS_STATUS_BPCNT_M           0x0000ffff00000000ull
 199 #define    PAS_STATUS_BPCNT_S           32
 200 #define    PAS_STATUS_CAUSE_M           0xf000000000000000ull
 201 #define    PAS_STATUS_TIMER             0x1000000000000000ull
 202 #define    PAS_STATUS_ERROR             0x2000000000000000ull
 203 #define    PAS_STATUS_SOFT              0x4000000000000000ull
 204 #define    PAS_STATUS_INT               0x8000000000000000ull
 205
 206 #define PAS_IOB_COM_PKTHDRCNT           0x120
 207 #define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M      0x0fff0000
 208 #define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S      16
 209 #define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M      0x00000fff
 210 #define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S      0
 211
 212 #define PAS_IOB_DMA_RXCH_CFG(i)         (0x1100 + (i)*4)
 213 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M         0x00000fff
 214 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S         0
 215 #define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
 216                                                  PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
 217 #define PAS_IOB_DMA_TXCH_CFG(i)         (0x1200 + (i)*4)
 218 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M         0x00000fff
 219 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S         0
 220 #define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)        (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
 221                                                  PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
 222 #define PAS_IOB_DMA_RXCH_STAT(i)        (0x1300 + (i)*4)
 223 #define    PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
 224 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M       0x00000fff
 225 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S       0
 226 #define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
 227                                                  PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
 228 #define PAS_IOB_DMA_TXCH_STAT(i)        (0x1400 + (i)*4)
 229 #define    PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
 230 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M       0x00000fff
 231 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S       0
 232 #define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)      (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
 233                                                  PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
 234 #define PAS_IOB_DMA_RXCH_RESET(i)       (0x1500 + (i)*4)
 235 #define    PAS_IOB_DMA_RXCH_RESET_PCNT_M        0xffff0000
 236 #define    PAS_IOB_DMA_RXCH_RESET_PCNT_S        16
 237 #define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
 238                                                  PAS_IOB_DMA_RXCH_RESET_PCNT_M)
 239 #define    PAS_IOB_DMA_RXCH_RESET_PCNTRST       0x00000020
 240 #define    PAS_IOB_DMA_RXCH_RESET_DCNTRST       0x00000010
 241 #define    PAS_IOB_DMA_RXCH_RESET_TINTC         0x00000008
 242 #define    PAS_IOB_DMA_RXCH_RESET_DINTC         0x00000004
 243 #define    PAS_IOB_DMA_RXCH_RESET_SINTC         0x00000002
 244 #define    PAS_IOB_DMA_RXCH_RESET_PINTC         0x00000001
 245 #define PAS_IOB_DMA_TXCH_RESET(i)       (0x1600 + (i)*4)
 246 #define    PAS_IOB_DMA_TXCH_RESET_PCNT_M        0xffff0000
 247 #define    PAS_IOB_DMA_TXCH_RESET_PCNT_S        16
 248 #define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)       (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
 249                                                  PAS_IOB_DMA_TXCH_RESET_PCNT_M)
 250 #define    PAS_IOB_DMA_TXCH_RESET_PCNTRST       0x00000020
 251 #define    PAS_IOB_DMA_TXCH_RESET_DCNTRST       0x00000010
 252 #define    PAS_IOB_DMA_TXCH_RESET_TINTC         0x00000008
 253 #define    PAS_IOB_DMA_TXCH_RESET_DINTC         0x00000004
 254 #define    PAS_IOB_DMA_TXCH_RESET_SINTC         0x00000002
 255 #define    PAS_IOB_DMA_TXCH_RESET_PINTC         0x00000001
 256
 257 #define PAS_IOB_DMA_COM_TIMEOUTCFG              0x1700
 258 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M    0x00ffffff
 259 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S    0
 260 #define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)   (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
 261                                                  PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
 262
 263 /* Transmit descriptor fields */
 264 #define XCT_MACTX_T             0x8000000000000000ull
 265 #define XCT_MACTX_ST            0x4000000000000000ull
 266 #define XCT_MACTX_NORES         0x0000000000000000ull
 267 #define XCT_MACTX_8BRES         0x1000000000000000ull
 268 #define XCT_MACTX_24BRES        0x2000000000000000ull
 269 #define XCT_MACTX_40BRES        0x3000000000000000ull
 270 #define XCT_MACTX_I             0x0800000000000000ull
 271 #define XCT_MACTX_O             0x0400000000000000ull
 272 #define XCT_MACTX_E             0x0200000000000000ull
 273 #define XCT_MACTX_VLAN_M        0x0180000000000000ull
 274 #define XCT_MACTX_VLAN_NOP      0x0000000000000000ull
 275 #define XCT_MACTX_VLAN_REMOVE   0x0080000000000000ull
 276 #define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
 277 #define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
 278 #define XCT_MACTX_CRC_M         0x0060000000000000ull
 279 #define XCT_MACTX_CRC_NOP       0x0000000000000000ull
 280 #define XCT_MACTX_CRC_INSERT    0x0020000000000000ull
 281 #define XCT_MACTX_CRC_PAD       0x0040000000000000ull
 282 #define XCT_MACTX_CRC_REPLACE   0x0060000000000000ull
 283 #define XCT_MACTX_SS            0x0010000000000000ull
 284 #define XCT_MACTX_LLEN_M        0x00007fff00000000ull
 285 #define XCT_MACTX_LLEN_S        32ull
 286 #define XCT_MACTX_LLEN(x)       ((((long)(x)) << XCT_MACTX_LLEN_S) & \
 287                                  XCT_MACTX_LLEN_M)
 288 #define XCT_MACTX_IPH_M         0x00000000f8000000ull
 289 #define XCT_MACTX_IPH_S         27ull
 290 #define XCT_MACTX_IPH(x)        ((((long)(x)) << XCT_MACTX_IPH_S) & \
 291                                  XCT_MACTX_IPH_M)
 292 #define XCT_MACTX_IPO_M         0x0000000007c00000ull
 293 #define XCT_MACTX_IPO_S         22ull
 294 #define XCT_MACTX_IPO(x)        ((((long)(x)) << XCT_MACTX_IPO_S) & \
 295                                  XCT_MACTX_IPO_M)
 296 #define XCT_MACTX_CSUM_M        0x0000000000000060ull
 297 #define XCT_MACTX_CSUM_NOP      0x0000000000000000ull
 298 #define XCT_MACTX_CSUM_TCP      0x0000000000000040ull
 299 #define XCT_MACTX_CSUM_UDP      0x0000000000000060ull
 300 #define XCT_MACTX_V6            0x0000000000000010ull
 301 #define XCT_MACTX_C             0x0000000000000004ull
 302 #define XCT_MACTX_AL2           0x0000000000000002ull
 303
 304 /* Receive descriptor fields */
 305 #define XCT_MACRX_T             0x8000000000000000ull
 306 #define XCT_MACRX_ST            0x4000000000000000ull
 307 #define XCT_MACRX_RR_M          0x3000000000000000ull
 308 #define XCT_MACRX_RR_NORES      0x0000000000000000ull
 309 #define XCT_MACRX_RR_8BRES      0x1000000000000000ull
 310 #define XCT_MACRX_O             0x0400000000000000ull
 311 #define XCT_MACRX_E             0x0200000000000000ull
 312 #define XCT_MACRX_FF            0x0100000000000000ull
 313 #define XCT_MACRX_PF            0x0080000000000000ull
 314 #define XCT_MACRX_OB            0x0040000000000000ull
 315 #define XCT_MACRX_OD            0x0020000000000000ull
 316 #define XCT_MACRX_FS            0x0010000000000000ull
 317 #define XCT_MACRX_NB_M          0x000fc00000000000ull
 318 #define XCT_MACRX_NB_S          46ULL
 319 #define XCT_MACRX_NB(x)         ((((long)(x)) << XCT_MACRX_NB_S) & \
 320                                  XCT_MACRX_NB_M)
 321 #define XCT_MACRX_LLEN_M        0x00003fff00000000ull
 322 #define XCT_MACRX_LLEN_S        32ULL
 323 #define XCT_MACRX_LLEN(x)       ((((long)(x)) << XCT_MACRX_LLEN_S) & \
 324                                  XCT_MACRX_LLEN_M)
 325 #define XCT_MACRX_CRC           0x0000000080000000ull
 326 #define XCT_MACRX_LEN_M         0x0000000060000000ull
 327 #define XCT_MACRX_LEN_TOOSHORT  0x0000000020000000ull
 328 #define XCT_MACRX_LEN_BELOWMIN  0x0000000040000000ull
 329 #define XCT_MACRX_LEN_TRUNC     0x0000000060000000ull
 330 #define XCT_MACRX_CAST_M        0x0000000018000000ull
 331 #define XCT_MACRX_CAST_UNI      0x0000000000000000ull
 332 #define XCT_MACRX_CAST_MULTI    0x0000000008000000ull
 333 #define XCT_MACRX_CAST_BROAD    0x0000000010000000ull
 334 #define XCT_MACRX_CAST_PAUSE    0x0000000018000000ull
 335 #define XCT_MACRX_VLC_M         0x0000000006000000ull
 336 #define XCT_MACRX_FM            0x0000000001000000ull
 337 #define XCT_MACRX_HTY_M         0x0000000000c00000ull
 338 #define XCT_MACRX_HTY_IPV4_OK   0x0000000000000000ull
 339 #define XCT_MACRX_HTY_IPV6      0x0000000000400000ull
 340 #define XCT_MACRX_HTY_IPV4_BAD  0x0000000000800000ull
 341 #define XCT_MACRX_HTY_NONIP     0x0000000000c00000ull
 342 #define XCT_MACRX_IPP_M         0x00000000003f0000ull
 343 #define XCT_MACRX_IPP_S         16
 344 #define XCT_MACRX_CSUM_M        0x000000000000ffffull
 345 #define XCT_MACRX_CSUM_S        0
 346
 347 #define XCT_PTR_T               0x8000000000000000ull
 348 #define XCT_PTR_LEN_M           0x7ffff00000000000ull
 349 #define XCT_PTR_LEN_S           44
 350 #define XCT_PTR_LEN(x)          ((((long)(x)) << XCT_PTR_LEN_S) & \
 351                                  XCT_PTR_LEN_M)
 352 #define XCT_PTR_ADDR_M          0x00000fffffffffffull
 353 #define XCT_PTR_ADDR_S          0
 354 #define XCT_PTR_ADDR(x)         ((((long)(x)) << XCT_PTR_ADDR_S) & \
 355                                  XCT_PTR_ADDR_M)
 356
 357 /* Receive interface 8byte result fields */
 358 #define XCT_RXRES_8B_L4O_M      0xff00000000000000ull
 359 #define XCT_RXRES_8B_L4O_S      56
 360 #define XCT_RXRES_8B_RULE_M     0x00ffff0000000000ull
 361 #define XCT_RXRES_8B_RULE_S     40
 362 #define XCT_RXRES_8B_EVAL_M     0x000000ffff000000ull
 363 #define XCT_RXRES_8B_EVAL_S     24
 364 #define XCT_RXRES_8B_HTYPE_M    0x0000000000f00000ull
 365 #define XCT_RXRES_8B_HASH_M     0x00000000000fffffull
 366 #define XCT_RXRES_8B_HASH_S     0
 367
 368 /* Receive interface buffer fields */
 369 #define XCT_RXB_LEN_M           0x0ffff00000000000ull
 370 #define XCT_RXB_LEN_S           44
 371 #define XCT_RXB_LEN(x)          ((((long)(x)) << XCT_RXB_LEN_S) & \
 372                                  XCT_RXB_LEN_M)
 373 #define XCT_RXB_ADDR_M          0x00000fffffffffffull
 374 #define XCT_RXB_ADDR_S          0
 375 #define XCT_RXB_ADDR(x)         ((((long)(x)) << XCT_RXB_ADDR_S) & \
 376                                  XCT_RXB_ADDR_M)
 377
 378 /* Copy descriptor fields */
 379 #define XCT_COPY_T              0x8000000000000000ull
 380 #define XCT_COPY_ST             0x4000000000000000ull
 381 #define XCT_COPY_RR_M           0x3000000000000000ull
 382 #define XCT_COPY_RR_NORES       0x0000000000000000ull
 383 #define XCT_COPY_RR_8BRES       0x1000000000000000ull
 384 #define XCT_COPY_RR_24BRES      0x2000000000000000ull
 385 #define XCT_COPY_RR_40BRES      0x3000000000000000ull
 386 #define XCT_COPY_I              0x0800000000000000ull
 387 #define XCT_COPY_O              0x0400000000000000ull
 388 #define XCT_COPY_E              0x0200000000000000ull
 389 #define XCT_COPY_STY_ZERO       0x01c0000000000000ull
 390 #define XCT_COPY_DTY_PREF       0x0038000000000000ull
 391 #define XCT_COPY_LLEN_M         0x0007ffff00000000ull
 392 #define XCT_COPY_LLEN_S         32
 393 #define XCT_COPY_LLEN(x)        ((((long)(x)) << XCT_COPY_LLEN_S) & \
 394                                  XCT_COPY_LLEN_M)
 395 #define XCT_COPY_SE             0x0000000000000001ull
 396
 397 /* Control descriptor fields */
 398 #define CTRL_CMD_T              0x8000000000000000ull
 399 #define CTRL_CMD_META_EVT       0x2000000000000000ull
 400 #define CTRL_CMD_O              0x0400000000000000ull
 401 #define CTRL_CMD_REG_M          0x000000000000000full
 402 #define CTRL_CMD_REG_S          0
 403 #define CTRL_CMD_REG(x)         ((((long)(x)) << CTRL_CMD_REG_S) & \
 404                                  CTRL_CMD_REG_M)
 405
 406
 407
 408 /* Prototypes for the shared DMA functions in the platform code. */
 409
 410 /* DMA TX Channel type. Right now only limitations used are event types 0/1,
 411  * for event-triggered DMA transactions.
 412  */
 413
 414 enum pasemi_dmachan_type {
 415         RXCHAN = 0,             /* Any RX chan */
 416         TXCHAN = 1,             /* Any TX chan */
 417         TXCHAN_EVT0 = 0x1001,   /* TX chan in event class 0 (chan 0-9) */
 418         TXCHAN_EVT1 = 0x2001,   /* TX chan in event class 1 (chan 10-19) */
 419 };
 420
 421 struct pasemi_dmachan {
 422         int              chno;          /* Channel number */
 423         enum pasemi_dmachan_type chan_type;     /* TX / RX */
 424         u64             *status;        /* Ptr to cacheable status */
 425         int              irq;           /* IRQ used by channel */
 426         unsigned int     ring_size;     /* size of allocated ring */
 427         dma_addr_t       ring_dma;      /* DMA address for ring */
 428         u64             *ring_virt;     /* Virt address for ring */
 429         void            *priv;          /* Ptr to start of client struct */
 430 };
 431
 432 /* Read/write the different registers in the I/O Bridge, Ethernet
 433  * and DMA Controller
 434  */
 435 extern unsigned int pasemi_read_iob_reg(unsigned int reg);
 436 extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);
 437
 438 extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
 439 extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);
 440
 441 extern unsigned int pasemi_read_dma_reg(unsigned int reg);
 442 extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);
 443
 444 /* Channel management routines */
 445
 446 extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
 447                                    int total_size, int offset);
 448 extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);
 449
 450 extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
 451                                   const u32 cmdsta);
 452 extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);
 453
 454 /* Common routines to allocate rings and buffers */
 455
 456 extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
 457 extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);
 458
 459 extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
 460                                   dma_addr_t *handle);
 461 extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
 462                                 dma_addr_t *handle);
 463
 464 /* Initialize the library, must be called before any other functions */
 465 extern int pasemi_dma_init(void);
 466
 467 #endif /* ASM_PASEMI_DMA_H */