x86: introduce native_set_pte_atomic() on 64-bit too
[wrt350n-kernel.git] / include / asm-s390 / tlb.h
blob618693cfc10f2047b710378210c4842d671f2678
1 #ifndef _S390_TLB_H
2 #define _S390_TLB_H
4 /*
5 * TLB flushing on s390 is complicated. The following requirement
6 * from the principles of operation is the most arduous:
8 * "A valid table entry must not be changed while it is attached
9 * to any CPU and may be used for translation by that CPU except to
10 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
11 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
12 * table entry, or (3) make a change by means of a COMPARE AND SWAP
13 * AND PURGE instruction that purges the TLB."
15 * The modification of a pte of an active mm struct therefore is
16 * a two step process: i) invalidate the pte, ii) store the new pte.
17 * This is true for the page protection bit as well.
18 * The only possible optimization is to flush at the beginning of
19 * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
21 * Pages used for the page tables is a different story. FIXME: more
24 #include <linux/mm.h>
25 #include <linux/swap.h>
26 #include <asm/processor.h>
27 #include <asm/pgalloc.h>
28 #include <asm/smp.h>
29 #include <asm/tlbflush.h>
31 #ifndef CONFIG_SMP
32 #define TLB_NR_PTRS 1
33 #else
34 #define TLB_NR_PTRS 508
35 #endif
37 struct mmu_gather {
38 struct mm_struct *mm;
39 unsigned int fullmm;
40 unsigned int nr_ptes;
41 unsigned int nr_pmds;
42 void *array[TLB_NR_PTRS];
45 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
47 static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
48 unsigned int full_mm_flush)
50 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
52 tlb->mm = mm;
53 tlb->fullmm = full_mm_flush || (num_online_cpus() == 1) ||
54 (atomic_read(&mm->mm_users) <= 1 && mm == current->active_mm);
55 tlb->nr_ptes = 0;
56 tlb->nr_pmds = TLB_NR_PTRS;
57 if (tlb->fullmm)
58 __tlb_flush_mm(mm);
59 return tlb;
62 static inline void tlb_flush_mmu(struct mmu_gather *tlb,
63 unsigned long start, unsigned long end)
65 if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pmds < TLB_NR_PTRS))
66 __tlb_flush_mm(tlb->mm);
67 while (tlb->nr_ptes > 0)
68 pte_free(tlb->array[--tlb->nr_ptes]);
69 while (tlb->nr_pmds < TLB_NR_PTRS)
70 pmd_free((pmd_t *) tlb->array[tlb->nr_pmds++]);
73 static inline void tlb_finish_mmu(struct mmu_gather *tlb,
74 unsigned long start, unsigned long end)
76 tlb_flush_mmu(tlb, start, end);
78 /* keep the page table cache within bounds */
79 check_pgt_cache();
81 put_cpu_var(mmu_gathers);
85 * Release the page cache reference for a pte removed by
86 * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
87 * has already been freed, so just do free_page_and_swap_cache.
89 static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
91 free_page_and_swap_cache(page);
95 * pte_free_tlb frees a pte table and clears the CRSTE for the
96 * page table from the tlb.
98 static inline void pte_free_tlb(struct mmu_gather *tlb, struct page *page)
100 if (!tlb->fullmm) {
101 tlb->array[tlb->nr_ptes++] = page;
102 if (tlb->nr_ptes >= tlb->nr_pmds)
103 tlb_flush_mmu(tlb, 0, 0);
104 } else
105 pte_free(page);
109 * pmd_free_tlb frees a pmd table and clears the CRSTE for the
110 * segment table entry from the tlb.
112 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd)
114 #ifdef __s390x__
115 if (!tlb->fullmm) {
116 tlb->array[--tlb->nr_pmds] = (struct page *) pmd;
117 if (tlb->nr_ptes >= tlb->nr_pmds)
118 tlb_flush_mmu(tlb, 0, 0);
119 } else
120 pmd_free(pmd);
121 #endif
124 #define pud_free_tlb(tlb, pud) do { } while (0)
126 #define tlb_start_vma(tlb, vma) do { } while (0)
127 #define tlb_end_vma(tlb, vma) do { } while (0)
128 #define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0)
129 #define tlb_migrate_finish(mm) do { } while (0)
131 #endif /* _S390_TLB_H */