x86: introduce native_set_pte_atomic() on 64-bit too
[wrt350n-kernel.git] / include / video / cvisionppc.h
blob11250eee9e98946e6cc1af7a03a3aef0d53c841b
1 /*
2 * Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer
3 * driver.
5 * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
6 * --------------------------------------------------------------------------
7 * $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $
8 * --------------------------------------------------------------------------
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive
11 * for more details.
14 #ifndef CVISIONPPC_H
15 #define CVISIONPPC_H
17 #ifndef PM2FB_H
18 #include "pm2fb.h"
19 #endif
21 struct cvppc_par {
22 unsigned char* pci_config;
23 unsigned char* pci_bridge;
24 u32 user_flags;
27 #define CSPPC_PCI_BRIDGE 0xfffe0000
28 #define CSPPC_BRIDGE_ENDIAN 0x0000
29 #define CSPPC_BRIDGE_INT 0x0010
31 #define CVPPC_PCI_CONFIG 0xfffc0000
32 #define CVPPC_ROM_ADDRESS 0xe2000001
33 #define CVPPC_REGS_REGION 0xef000000
34 #define CVPPC_FB_APERTURE_ONE 0xe0000000
35 #define CVPPC_FB_APERTURE_TWO 0xe1000000
36 #define CVPPC_FB_SIZE 0x00800000
37 #define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
38 #define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */
39 #define CVPPC_MEMCLOCK 83000 /* in KHz */
41 /* CVPPC_BRIDGE_ENDIAN */
42 #define CSPPCF_BRIDGE_BIG_ENDIAN 0x02
44 /* CVPPC_BRIDGE_INT */
45 #define CSPPCF_BRIDGE_ACTIVE_INT2 0x01
47 #endif /* CVISIONPPC_H */
49 /*****************************************************************************
50 * That's all folks!
51 *****************************************************************************/