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[PARISC] fix "ENTRY" macro redefinition
[wrt350n-kernel.git] / drivers / ata / pata_via.c
blobe4c71f76bd55ba701eea332594707880e3480f16
1 /*
2 * pata_via.c - VIA PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Documentation
7 * Most chipset documentation available under NDA only
8 *
9 * VIA version guide
10 * VIA VT82C561 - early design, uses ata_generic currently
11 * VIA VT82C576 - MWDMA, 33Mhz
12 * VIA VT82C586 - MWDMA, 33Mhz
13 * VIA VT82C586a - Added UDMA to 33Mhz
14 * VIA VT82C586b - UDMA33
15 * VIA VT82C596a - Nonfunctional UDMA66
16 * VIA VT82C596b - Working UDMA66
17 * VIA VT82C686 - Nonfunctional UDMA66
18 * VIA VT82C686a - Working UDMA66
19 * VIA VT82C686b - Updated to UDMA100
20 * VIA VT8231 - UDMA100
21 * VIA VT8233 - UDMA100
22 * VIA VT8233a - UDMA133
23 * VIA VT8233c - UDMA100
24 * VIA VT8235 - UDMA133
25 * VIA VT8237 - UDMA133
26 * VIA VT8237S - UDMA133
27 * VIA VT8251 - UDMA133
28 *
29 * Most registers remain compatible across chips. Others start reserved
30 * and acquire sensible semantics if set to 1 (eg cable detect). A few
31 * exceptions exist, notably around the FIFO settings.
32 *
33 * One additional quirk of the VIA design is that like ALi they use few
34 * PCI IDs for a lot of chips.
35 *
36 * Based heavily on:
37 *
38 * Version 3.38
39 *
40 * VIA IDE driver for Linux. Supported southbridges:
41 *
42 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
43 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
44 * vt8235, vt8237
45 *
46 * Copyright (c) 2000-2002 Vojtech Pavlik
47 *
48 * Based on the work of:
49 * Michel Aubry
50 * Jeff Garzik
51 * Andre Hedrick
52
53 */
54
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <scsi/scsi_host.h>
62 #include <linux/libata.h>
63
64 #define DRV_NAME "pata_via"
65 #define DRV_VERSION "0.3.1"
66
67 /*
68 * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx
69 * driver.
70 */
71
72 enum {
73 VIA_UDMA = 0x007,
74 VIA_UDMA_NONE = 0x000,
75 VIA_UDMA_33 = 0x001,
76 VIA_UDMA_66 = 0x002,
77 VIA_UDMA_100 = 0x003,
78 VIA_UDMA_133 = 0x004,
79 VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */
80 VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */
81 VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */
82 VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */
83 VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */
84 VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */
85 VIA_NO_ENABLES = 0x400, /* Has no enablebits */
86 };
87
88 /*
89 * VIA SouthBridge chips.
90 */
91
92 static const struct via_isa_bridge {
93 const char *name;
94 u16 id;
95 u8 rev_min;
96 u8 rev_max;
97 u16 flags;
98 } via_isa_bridges[] = {
99 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
100 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
101 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
102 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES},
103 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
104 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
105 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
106 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
107 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
108 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
109 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
110 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
111 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
112 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
113 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
114 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
115 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
116 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
117 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
118 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
119 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
120 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
121 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
122 { NULL }
123 };
124
125 /**
126 * via_cable_detect - cable detection
127 * @ap: ATA port
128 *
129 * Perform cable detection. Actually for the VIA case the BIOS
130 * already did this for us. We read the values provided by the
131 * BIOS. If you are using an 8235 in a non-PC configuration you
132 * may need to update this code.
133 *
134 * Hotplug also impacts on this.
135 */
136
137 static int via_cable_detect(struct ata_port *ap) {
138 const struct via_isa_bridge *config = ap->host->private_data;
139 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140 u32 ata66;
141
142 /* Early chips are 40 wire */
143 if ((config->flags & VIA_UDMA) < VIA_UDMA_66)
144 return ATA_CBL_PATA40;
145 /* UDMA 66 chips have only drive side logic */
146 else if((config->flags & VIA_UDMA) < VIA_UDMA_100)
147 return ATA_CBL_PATA_UNK;
148 /* UDMA 100 or later */
149 pci_read_config_dword(pdev, 0x50, &ata66);
150 /* Check both the drive cable reporting bits, we might not have
151 two drives */
152 if (ata66 & (0x10100000 >> (16 * ap->port_no)))
153 return ATA_CBL_PATA80;
154 return ATA_CBL_PATA40;
155 }
156
157 static int via_pre_reset(struct ata_port *ap, unsigned long deadline)
158 {
159 const struct via_isa_bridge *config = ap->host->private_data;
160
161 if (!(config->flags & VIA_NO_ENABLES)) {
162 static const struct pci_bits via_enable_bits[] = {
163 { 0x40, 1, 0x02, 0x02 },
164 { 0x40, 1, 0x01, 0x01 }
165 };
166 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
167 if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no]))
168 return -ENOENT;
169 }
170
171 return ata_std_prereset(ap, deadline);
172 }
173
174
175 /**
176 * via_error_handler - reset for VIA chips
177 * @ap: ATA port
178 *
179 * Handle the reset callback for the later chips with cable detect
180 */
181
182 static void via_error_handler(struct ata_port *ap)
183 {
184 ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
185 }
186
187 /**
188 * via_do_set_mode - set initial PIO mode data
189 * @ap: ATA interface
190 * @adev: ATA device
191 * @mode: ATA mode being programmed
192 * @tdiv: Clocks per PCI clock
193 * @set_ast: Set to program address setup
194 * @udma_type: UDMA mode/format of registers
195 *
196 * Program the VIA registers for DMA and PIO modes. Uses the ata timing
197 * support in order to compute modes.
198 *
199 * FIXME: Hotplug will require we serialize multiple mode changes
200 * on the two channels.
201 */
202
203 static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type)
204 {
205 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
206 struct ata_device *peer = ata_dev_pair(adev);
207 struct ata_timing t, p;
208 static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */
209 unsigned long T = 1000000000 / via_clock;
210 unsigned long UT = T/tdiv;
211 int ut;
212 int offset = 3 - (2*ap->port_no) - adev->devno;
213
214
215 /* Calculate the timing values we require */
216 ata_timing_compute(adev, mode, &t, T, UT);
217
218 /* We share 8bit timing so we must merge the constraints */
219 if (peer) {
220 if (peer->pio_mode) {
221 ata_timing_compute(peer, peer->pio_mode, &p, T, UT);
222 ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT);
223 }
224 }
225
226 /* Address setup is programmable but breaks on UDMA133 setups */
227 if (set_ast) {
228 u8 setup; /* 2 bits per drive */
229 int shift = 2 * offset;
230
231 pci_read_config_byte(pdev, 0x4C, &setup);
232 setup &= ~(3 << shift);
233 setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */
234 pci_write_config_byte(pdev, 0x4C, setup);
235 }
236
237 /* Load the PIO mode bits */
238 pci_write_config_byte(pdev, 0x4F - ap->port_no,
239 ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1));
240 pci_write_config_byte(pdev, 0x48 + offset,
241 ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1));
242
243 /* Load the UDMA bits according to type */
244 switch(udma_type) {
245 default:
246 /* BUG() ? */
247 /* fall through */
248 case 33:
249 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03;
250 break;
251 case 66:
252 ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f;
253 break;
254 case 100:
255 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
256 break;
257 case 133:
258 ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07;
259 break;
260 }
261 /* Set UDMA unless device is not UDMA capable */
262 if (udma_type)
263 pci_write_config_byte(pdev, 0x50 + offset, ut);
264 }
265
266 static void via_set_piomode(struct ata_port *ap, struct ata_device *adev)
267 {
268 const struct via_isa_bridge *config = ap->host->private_data;
269 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
270 int mode = config->flags & VIA_UDMA;
271 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
272 static u8 udma[5] = { 0, 33, 66, 100, 133 };
273
274 via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]);
275 }
276
277 static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev)
278 {
279 const struct via_isa_bridge *config = ap->host->private_data;
280 int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1;
281 int mode = config->flags & VIA_UDMA;
282 static u8 tclock[5] = { 1, 1, 2, 3, 4 };
283 static u8 udma[5] = { 0, 33, 66, 100, 133 };
284
285 via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]);
286 }
287
288 static struct scsi_host_template via_sht = {
289 .module = THIS_MODULE,
290 .name = DRV_NAME,
291 .ioctl = ata_scsi_ioctl,
292 .queuecommand = ata_scsi_queuecmd,
293 .can_queue = ATA_DEF_QUEUE,
294 .this_id = ATA_SHT_THIS_ID,
295 .sg_tablesize = LIBATA_MAX_PRD,
296 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
297 .emulated = ATA_SHT_EMULATED,
298 .use_clustering = ATA_SHT_USE_CLUSTERING,
299 .proc_name = DRV_NAME,
300 .dma_boundary = ATA_DMA_BOUNDARY,
301 .slave_configure = ata_scsi_slave_config,
302 .slave_destroy = ata_scsi_slave_destroy,
303 .bios_param = ata_std_bios_param,
304 };
305
306 static struct ata_port_operations via_port_ops = {
307 .port_disable = ata_port_disable,
308 .set_piomode = via_set_piomode,
309 .set_dmamode = via_set_dmamode,
310 .mode_filter = ata_pci_default_filter,
311
312 .tf_load = ata_tf_load,
313 .tf_read = ata_tf_read,
314 .check_status = ata_check_status,
315 .exec_command = ata_exec_command,
316 .dev_select = ata_std_dev_select,
317
318 .freeze = ata_bmdma_freeze,
319 .thaw = ata_bmdma_thaw,
320 .error_handler = via_error_handler,
321 .post_internal_cmd = ata_bmdma_post_internal_cmd,
322 .cable_detect = via_cable_detect,
323
324 .bmdma_setup = ata_bmdma_setup,
325 .bmdma_start = ata_bmdma_start,
326 .bmdma_stop = ata_bmdma_stop,
327 .bmdma_status = ata_bmdma_status,
328
329 .qc_prep = ata_qc_prep,
330 .qc_issue = ata_qc_issue_prot,
331
332 .data_xfer = ata_data_xfer,
333
334 .irq_handler = ata_interrupt,
335 .irq_clear = ata_bmdma_irq_clear,
336 .irq_on = ata_irq_on,
337 .irq_ack = ata_irq_ack,
338
339 .port_start = ata_port_start,
340 };
341
342 static struct ata_port_operations via_port_ops_noirq = {
343 .port_disable = ata_port_disable,
344 .set_piomode = via_set_piomode,
345 .set_dmamode = via_set_dmamode,
346 .mode_filter = ata_pci_default_filter,
347
348 .tf_load = ata_tf_load,
349 .tf_read = ata_tf_read,
350 .check_status = ata_check_status,
351 .exec_command = ata_exec_command,
352 .dev_select = ata_std_dev_select,
353
354 .freeze = ata_bmdma_freeze,
355 .thaw = ata_bmdma_thaw,
356 .error_handler = via_error_handler,
357 .post_internal_cmd = ata_bmdma_post_internal_cmd,
358 .cable_detect = via_cable_detect,
359
360 .bmdma_setup = ata_bmdma_setup,
361 .bmdma_start = ata_bmdma_start,
362 .bmdma_stop = ata_bmdma_stop,
363 .bmdma_status = ata_bmdma_status,
364
365 .qc_prep = ata_qc_prep,
366 .qc_issue = ata_qc_issue_prot,
367
368 .data_xfer = ata_data_xfer_noirq,
369
370 .irq_handler = ata_interrupt,
371 .irq_clear = ata_bmdma_irq_clear,
372 .irq_on = ata_irq_on,
373 .irq_ack = ata_irq_ack,
374
375 .port_start = ata_port_start,
376 };
377
378 /**
379 * via_config_fifo - set up the FIFO
380 * @pdev: PCI device
381 * @flags: configuration flags
382 *
383 * Set the FIFO properties for this device if neccessary. Used both on
384 * set up and on and the resume path
385 */
386
387 static void via_config_fifo(struct pci_dev *pdev, unsigned int flags)
388 {
389 u8 enable;
390
391 /* 0x40 low bits indicate enabled channels */
392 pci_read_config_byte(pdev, 0x40 , &enable);
393 enable &= 3;
394
395 if (flags & VIA_SET_FIFO) {
396 static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20};
397 u8 fifo;
398
399 pci_read_config_byte(pdev, 0x43, &fifo);
400
401 /* Clear PREQ# until DDACK# for errata */
402 if (flags & VIA_BAD_PREQ)
403 fifo &= 0x7F;
404 else
405 fifo &= 0x9f;
406 /* Turn on FIFO for enabled channels */
407 fifo |= fifo_setting[enable];
408 pci_write_config_byte(pdev, 0x43, fifo);
409 }
410 }
411
412 /**
413 * via_init_one - discovery callback
414 * @pdev: PCI device
415 * @id: PCI table info
416 *
417 * A VIA IDE interface has been discovered. Figure out what revision
418 * and perform configuration work before handing it to the ATA layer
419 */
420
421 static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
422 {
423 /* Early VIA without UDMA support */
424 static const struct ata_port_info via_mwdma_info = {
425 .sht = &via_sht,
426 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
427 .pio_mask = 0x1f,
428 .mwdma_mask = 0x07,
429 .port_ops = &via_port_ops
430 };
431 /* Ditto with IRQ masking required */
432 static const struct ata_port_info via_mwdma_info_borked = {
433 .sht = &via_sht,
434 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
435 .pio_mask = 0x1f,
436 .mwdma_mask = 0x07,
437 .port_ops = &via_port_ops_noirq,
438 };
439 /* VIA UDMA 33 devices (and borked 66) */
440 static const struct ata_port_info via_udma33_info = {
441 .sht = &via_sht,
442 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
443 .pio_mask = 0x1f,
444 .mwdma_mask = 0x07,
445 .udma_mask = 0x7,
446 .port_ops = &via_port_ops
447 };
448 /* VIA UDMA 66 devices */
449 static const struct ata_port_info via_udma66_info = {
450 .sht = &via_sht,
451 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
452 .pio_mask = 0x1f,
453 .mwdma_mask = 0x07,
454 .udma_mask = 0x1f,
455 .port_ops = &via_port_ops
456 };
457 /* VIA UDMA 100 devices */
458 static const struct ata_port_info via_udma100_info = {
459 .sht = &via_sht,
460 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
461 .pio_mask = 0x1f,
462 .mwdma_mask = 0x07,
463 .udma_mask = 0x3f,
464 .port_ops = &via_port_ops
465 };
466 /* UDMA133 with bad AST (All current 133) */
467 static const struct ata_port_info via_udma133_info = {
468 .sht = &via_sht,
469 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING,
470 .pio_mask = 0x1f,
471 .mwdma_mask = 0x07,
472 .udma_mask = 0x7f, /* FIXME: should check north bridge */
473 .port_ops = &via_port_ops
474 };
475 struct ata_port_info type;
476 const struct ata_port_info *ppi[] = { &type, NULL };
477 struct pci_dev *isa = NULL;
478 const struct via_isa_bridge *config;
479 static int printed_version;
480 u8 t;
481 u8 enable;
482 u32 timing;
483
484 if (!printed_version++)
485 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
486
487 /* To find out how the IDE will behave and what features we
488 actually have to look at the bridge not the IDE controller */
489 for (config = via_isa_bridges; config->id; config++)
490 if ((isa = pci_get_device(PCI_VENDOR_ID_VIA +
491 !!(config->flags & VIA_BAD_ID),
492 config->id, NULL))) {
493
494 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
495 if (t >= config->rev_min &&
496 t <= config->rev_max)
497 break;
498 pci_dev_put(isa);
499 }
500
501 if (!config->id) {
502 printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n");
503 return -ENODEV;
504 }
505 pci_dev_put(isa);
506
507 /* 0x40 low bits indicate enabled channels */
508 pci_read_config_byte(pdev, 0x40 , &enable);
509 enable &= 3;
510 if (enable == 0) {
511 return -ENODEV;
512 }
513
514 /* Initialise the FIFO for the enabled channels. */
515 via_config_fifo(pdev, config->flags);
516
517 /* Clock set up */
518 switch(config->flags & VIA_UDMA) {
519 case VIA_UDMA_NONE:
520 if (config->flags & VIA_NO_UNMASK)
521 type = via_mwdma_info_borked;
522 else
523 type = via_mwdma_info;
524 break;
525 case VIA_UDMA_33:
526 type = via_udma33_info;
527 break;
528 case VIA_UDMA_66:
529 type = via_udma66_info;
530 /* The 66 MHz devices require we enable the clock */
531 pci_read_config_dword(pdev, 0x50, &timing);
532 timing |= 0x80008;
533 pci_write_config_dword(pdev, 0x50, timing);
534 break;
535 case VIA_UDMA_100:
536 type = via_udma100_info;
537 break;
538 case VIA_UDMA_133:
539 type = via_udma133_info;
540 break;
541 default:
542 WARN_ON(1);
543 return -ENODEV;
544 }
545
546 if (config->flags & VIA_BAD_CLK66) {
547 /* Disable the 66MHz clock on problem devices */
548 pci_read_config_dword(pdev, 0x50, &timing);
549 timing &= ~0x80008;
550 pci_write_config_dword(pdev, 0x50, timing);
551 }
552
553 /* We have established the device type, now fire it up */
554 type.private_data = (void *)config;
555
556 return ata_pci_init_one(pdev, ppi);
557 }
558
559 #ifdef CONFIG_PM
560 /**
561 * via_reinit_one - reinit after resume
562 * @pdev; PCI device
563 *
564 * Called when the VIA PATA device is resumed. We must then
565 * reconfigure the fifo and other setup we may have altered. In
566 * addition the kernel needs to have the resume methods on PCI
567 * quirk supported.
568 */
569
570 static int via_reinit_one(struct pci_dev *pdev)
571 {
572 u32 timing;
573 struct ata_host *host = dev_get_drvdata(&pdev->dev);
574 const struct via_isa_bridge *config = host->private_data;
575
576 via_config_fifo(pdev, config->flags);
577
578 if ((config->flags & VIA_UDMA) == VIA_UDMA_66) {
579 /* The 66 MHz devices require we enable the clock */
580 pci_read_config_dword(pdev, 0x50, &timing);
581 timing |= 0x80008;
582 pci_write_config_dword(pdev, 0x50, timing);
583 }
584 if (config->flags & VIA_BAD_CLK66) {
585 /* Disable the 66MHz clock on problem devices */
586 pci_read_config_dword(pdev, 0x50, &timing);
587 timing &= ~0x80008;
588 pci_write_config_dword(pdev, 0x50, timing);
589 }
590 return ata_pci_device_resume(pdev);
591 }
592 #endif
593
594 static const struct pci_device_id via[] = {
595 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), },
596 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), },
597 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), },
598 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), },
599
600 { },
601 };
602
603 static struct pci_driver via_pci_driver = {
604 .name = DRV_NAME,
605 .id_table = via,
606 .probe = via_init_one,
607 .remove = ata_pci_remove_one,
608 #ifdef CONFIG_PM
609 .suspend = ata_pci_device_suspend,
610 .resume = via_reinit_one,
611 #endif
612 };
613
614 static int __init via_init(void)
615 {
616 return pci_register_driver(&via_pci_driver);
617 }
618
619 static void __exit via_exit(void)
620 {
621 pci_unregister_driver(&via_pci_driver);
622 }
623
624 MODULE_AUTHOR("Alan Cox");
625 MODULE_DESCRIPTION("low-level driver for VIA PATA");
626 MODULE_LICENSE("GPL");
627 MODULE_DEVICE_TABLE(pci, via);
628 MODULE_VERSION(DRV_VERSION);
629
630 module_init(via_init);
631 module_exit(via_exit);
WRT350N Kernel Patches