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[PARISC] fix "ENTRY" macro redefinition
[wrt350n-kernel.git] / drivers / net / netxen / netxen_nic_hw.c
blobbaff17a24d633ba8a5eec76c9ad7dab9b8a73aaa
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #define DEFINE_GLOBAL_RECV_CRB
37 #include "netxen_nic_phan_reg.h"
38
39
40 #include <net/ip.h>
41
42 struct netxen_recv_crb recv_crb_registers[] = {
43 /*
44 * Instance 0.
45 */
46 {
47 /* rcv_desc_crb: */
48 {
49 {
50 /* crb_rcv_producer_offset: */
51 NETXEN_NIC_REG(0x100),
52 /* crb_rcv_consumer_offset: */
53 NETXEN_NIC_REG(0x104),
54 /* crb_gloablrcv_ring: */
55 NETXEN_NIC_REG(0x108),
56 /* crb_rcv_ring_size */
57 NETXEN_NIC_REG(0x10c),
58
59 },
60 /* Jumbo frames */
61 {
62 /* crb_rcv_producer_offset: */
63 NETXEN_NIC_REG(0x110),
64 /* crb_rcv_consumer_offset: */
65 NETXEN_NIC_REG(0x114),
66 /* crb_gloablrcv_ring: */
67 NETXEN_NIC_REG(0x118),
68 /* crb_rcv_ring_size */
69 NETXEN_NIC_REG(0x11c),
70 },
71 /* LRO */
72 {
73 /* crb_rcv_producer_offset: */
74 NETXEN_NIC_REG(0x120),
75 /* crb_rcv_consumer_offset: */
76 NETXEN_NIC_REG(0x124),
77 /* crb_gloablrcv_ring: */
78 NETXEN_NIC_REG(0x128),
79 /* crb_rcv_ring_size */
80 NETXEN_NIC_REG(0x12c),
81 }
82 },
83 /* crb_rcvstatus_ring: */
84 NETXEN_NIC_REG(0x130),
85 /* crb_rcv_status_producer: */
86 NETXEN_NIC_REG(0x134),
87 /* crb_rcv_status_consumer: */
88 NETXEN_NIC_REG(0x138),
89 /* crb_rcvpeg_state: */
90 NETXEN_NIC_REG(0x13c),
91 /* crb_status_ring_size */
92 NETXEN_NIC_REG(0x140),
93
94 },
95 /*
96 * Instance 1,
97 */
98 {
99 /* rcv_desc_crb: */
100 {
101 {
102 /* crb_rcv_producer_offset: */
103 NETXEN_NIC_REG(0x144),
104 /* crb_rcv_consumer_offset: */
105 NETXEN_NIC_REG(0x148),
106 /* crb_globalrcv_ring: */
107 NETXEN_NIC_REG(0x14c),
108 /* crb_rcv_ring_size */
109 NETXEN_NIC_REG(0x150),
110
111 },
112 /* Jumbo frames */
113 {
114 /* crb_rcv_producer_offset: */
115 NETXEN_NIC_REG(0x154),
116 /* crb_rcv_consumer_offset: */
117 NETXEN_NIC_REG(0x158),
118 /* crb_globalrcv_ring: */
119 NETXEN_NIC_REG(0x15c),
120 /* crb_rcv_ring_size */
121 NETXEN_NIC_REG(0x160),
122 },
123 /* LRO */
124 {
125 /* crb_rcv_producer_offset: */
126 NETXEN_NIC_REG(0x164),
127 /* crb_rcv_consumer_offset: */
128 NETXEN_NIC_REG(0x168),
129 /* crb_globalrcv_ring: */
130 NETXEN_NIC_REG(0x16c),
131 /* crb_rcv_ring_size */
132 NETXEN_NIC_REG(0x170),
133 }
134
135 },
136 /* crb_rcvstatus_ring: */
137 NETXEN_NIC_REG(0x174),
138 /* crb_rcv_status_producer: */
139 NETXEN_NIC_REG(0x178),
140 /* crb_rcv_status_consumer: */
141 NETXEN_NIC_REG(0x17c),
142 /* crb_rcvpeg_state: */
143 NETXEN_NIC_REG(0x180),
144 /* crb_status_ring_size */
145 NETXEN_NIC_REG(0x184),
146 },
147 /*
148 * Instance 2,
149 */
150 {
151 {
152 {
153 /* crb_rcv_producer_offset: */
154 NETXEN_NIC_REG(0x1d8),
155 /* crb_rcv_consumer_offset: */
156 NETXEN_NIC_REG(0x1dc),
157 /* crb_gloablrcv_ring: */
158 NETXEN_NIC_REG(0x1f0),
159 /* crb_rcv_ring_size */
160 NETXEN_NIC_REG(0x1f4),
161 },
162 /* Jumbo frames */
163 {
164 /* crb_rcv_producer_offset: */
165 NETXEN_NIC_REG(0x1f8),
166 /* crb_rcv_consumer_offset: */
167 NETXEN_NIC_REG(0x1fc),
168 /* crb_gloablrcv_ring: */
169 NETXEN_NIC_REG(0x200),
170 /* crb_rcv_ring_size */
171 NETXEN_NIC_REG(0x204),
172 },
173 /* LRO */
174 {
175 /* crb_rcv_producer_offset: */
176 NETXEN_NIC_REG(0x208),
177 /* crb_rcv_consumer_offset: */
178 NETXEN_NIC_REG(0x20c),
179 /* crb_gloablrcv_ring: */
180 NETXEN_NIC_REG(0x210),
181 /* crb_rcv_ring_size */
182 NETXEN_NIC_REG(0x214),
183 }
184 },
185 /* crb_rcvstatus_ring: */
186 NETXEN_NIC_REG(0x218),
187 /* crb_rcv_status_producer: */
188 NETXEN_NIC_REG(0x21c),
189 /* crb_rcv_status_consumer: */
190 NETXEN_NIC_REG(0x220),
191 /* crb_rcvpeg_state: */
192 NETXEN_NIC_REG(0x224),
193 /* crb_status_ring_size */
194 NETXEN_NIC_REG(0x228),
195 },
196 /*
197 * Instance 3,
198 */
199 {
200 {
201 {
202 /* crb_rcv_producer_offset: */
203 NETXEN_NIC_REG(0x22c),
204 /* crb_rcv_consumer_offset: */
205 NETXEN_NIC_REG(0x230),
206 /* crb_gloablrcv_ring: */
207 NETXEN_NIC_REG(0x234),
208 /* crb_rcv_ring_size */
209 NETXEN_NIC_REG(0x238),
210 },
211 /* Jumbo frames */
212 {
213 /* crb_rcv_producer_offset: */
214 NETXEN_NIC_REG(0x23c),
215 /* crb_rcv_consumer_offset: */
216 NETXEN_NIC_REG(0x240),
217 /* crb_gloablrcv_ring: */
218 NETXEN_NIC_REG(0x244),
219 /* crb_rcv_ring_size */
220 NETXEN_NIC_REG(0x248),
221 },
222 /* LRO */
223 {
224 /* crb_rcv_producer_offset: */
225 NETXEN_NIC_REG(0x24c),
226 /* crb_rcv_consumer_offset: */
227 NETXEN_NIC_REG(0x250),
228 /* crb_gloablrcv_ring: */
229 NETXEN_NIC_REG(0x254),
230 /* crb_rcv_ring_size */
231 NETXEN_NIC_REG(0x258),
232 }
233 },
234 /* crb_rcvstatus_ring: */
235 NETXEN_NIC_REG(0x25c),
236 /* crb_rcv_status_producer: */
237 NETXEN_NIC_REG(0x260),
238 /* crb_rcv_status_consumer: */
239 NETXEN_NIC_REG(0x264),
240 /* crb_rcvpeg_state: */
241 NETXEN_NIC_REG(0x268),
242 /* crb_status_ring_size */
243 NETXEN_NIC_REG(0x26c),
244 },
245 };
246
247 u64 ctx_addr_sig_regs[][3] = {
248 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
249 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
250 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
251 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
252 };
253
254
255 /* PCI Windowing for DDR regions. */
256
257 #define ADDR_IN_RANGE(addr, low, high) \
258 (((addr) <= (high)) && ((addr) >= (low)))
259
260 #define NETXEN_FLASH_BASE (BOOTLD_START)
261 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
262 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
263 #define NETXEN_MIN_MTU 64
264 #define NETXEN_ETH_FCS_SIZE 4
265 #define NETXEN_ENET_HEADER_SIZE 14
266 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
267 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
268 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
269 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
270
271 #define lower32(x) ((u32)((x) & 0xffffffff))
272 #define upper32(x) \
273 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
274
275 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
276 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
277 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
278 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
279
280 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
281
282 unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
283 unsigned long long addr);
284 void netxen_free_hw_resources(struct netxen_adapter *adapter);
285
286 int netxen_nic_set_mac(struct net_device *netdev, void *p)
287 {
288 struct netxen_adapter *adapter = netdev_priv(netdev);
289 struct sockaddr *addr = p;
290
291 if (netif_running(netdev))
292 return -EBUSY;
293
294 if (!is_valid_ether_addr(addr->sa_data))
295 return -EADDRNOTAVAIL;
296
297 DPRINTK(INFO, "valid ether addr\n");
298 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
299
300 if (adapter->macaddr_set)
301 adapter->macaddr_set(adapter, addr->sa_data);
302
303 return 0;
304 }
305
306 /*
307 * netxen_nic_set_multi - Multicast
308 */
309 void netxen_nic_set_multi(struct net_device *netdev)
310 {
311 struct netxen_adapter *adapter = netdev_priv(netdev);
312 struct dev_mc_list *mc_ptr;
313
314 mc_ptr = netdev->mc_list;
315 if (netdev->flags & IFF_PROMISC) {
316 if (adapter->set_promisc)
317 adapter->set_promisc(adapter,
318 NETXEN_NIU_PROMISC_MODE);
319 } else {
320 if (adapter->unset_promisc)
321 adapter->unset_promisc(adapter,
322 NETXEN_NIU_NON_PROMISC_MODE);
323 }
324 }
325
326 /*
327 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
328 * @returns 0 on success, negative on failure
329 */
330 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
331 {
332 struct netxen_adapter *adapter = netdev_priv(netdev);
333 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
334
335 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
336 printk(KERN_ERR "%s: %s %d is not supported.\n",
337 netxen_nic_driver_name, netdev->name, mtu);
338 return -EINVAL;
339 }
340
341 if (adapter->set_mtu)
342 adapter->set_mtu(adapter, mtu);
343 netdev->mtu = mtu;
344
345 return 0;
346 }
347
348 /*
349 * check if the firmware has been downloaded and ready to run and
350 * setup the address for the descriptors in the adapter
351 */
352 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
353 {
354 struct netxen_hardware_context *hw = &adapter->ahw;
355 u32 state = 0;
356 void *addr;
357 int loops = 0, err = 0;
358 int ctx, ring;
359 struct netxen_recv_context *recv_ctx;
360 struct netxen_rcv_desc_ctx *rcv_desc;
361 int func_id = adapter->portnum;
362
363 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
364 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
365 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
366 pci_base_offset(adapter, NETXEN_CRB_CAM));
367 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
368 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
369
370
371 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
372 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
373 loops = 0;
374 state = 0;
375 /* Window 1 call */
376 state = readl(NETXEN_CRB_NORMALIZE(adapter,
377 recv_crb_registers[ctx].
378 crb_rcvpeg_state));
379 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
380 udelay(100);
381 /* Window 1 call */
382 state = readl(NETXEN_CRB_NORMALIZE(adapter,
383 recv_crb_registers
384 [ctx].
385 crb_rcvpeg_state));
386 loops++;
387 }
388 if (loops >= 20) {
389 printk(KERN_ERR "Rcv Peg initialization not complete:"
390 "%x.\n", state);
391 err = -EIO;
392 return err;
393 }
394 }
395 DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
396
397 addr = netxen_alloc(adapter->ahw.pdev,
398 sizeof(struct netxen_ring_ctx) +
399 sizeof(uint32_t),
400 (dma_addr_t *) & adapter->ctx_desc_phys_addr,
401 &adapter->ctx_desc_pdev);
402
403 printk(KERN_INFO "ctx_desc_phys_addr: 0x%llx\n",
404 (unsigned long long) adapter->ctx_desc_phys_addr);
405 if (addr == NULL) {
406 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
407 err = -ENOMEM;
408 return err;
409 }
410 memset(addr, 0, sizeof(struct netxen_ring_ctx));
411 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
412 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
413 adapter->ctx_desc->cmd_consumer_offset =
414 cpu_to_le64(adapter->ctx_desc_phys_addr +
415 sizeof(struct netxen_ring_ctx));
416 adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
417 sizeof(struct netxen_ring_ctx));
418
419 addr = netxen_alloc(adapter->ahw.pdev,
420 sizeof(struct cmd_desc_type0) *
421 adapter->max_tx_desc_count,
422 (dma_addr_t *) & hw->cmd_desc_phys_addr,
423 &adapter->ahw.cmd_desc_pdev);
424 printk(KERN_INFO "cmd_desc_phys_addr: 0x%llx\n",
425 (unsigned long long) hw->cmd_desc_phys_addr);
426
427 if (addr == NULL) {
428 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
429 netxen_free_hw_resources(adapter);
430 return -ENOMEM;
431 }
432
433 adapter->ctx_desc->cmd_ring_addr =
434 cpu_to_le64(hw->cmd_desc_phys_addr);
435 adapter->ctx_desc->cmd_ring_size =
436 cpu_to_le32(adapter->max_tx_desc_count);
437
438 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
439
440 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
441 recv_ctx = &adapter->recv_ctx[ctx];
442
443 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
444 rcv_desc = &recv_ctx->rcv_desc[ring];
445 addr = netxen_alloc(adapter->ahw.pdev,
446 RCV_DESC_RINGSIZE,
447 &rcv_desc->phys_addr,
448 &rcv_desc->phys_pdev);
449 if (addr == NULL) {
450 DPRINTK(ERR, "bad return from "
451 "pci_alloc_consistent\n");
452 netxen_free_hw_resources(adapter);
453 err = -ENOMEM;
454 return err;
455 }
456 rcv_desc->desc_head = (struct rcv_desc *)addr;
457 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
458 cpu_to_le64(rcv_desc->phys_addr);
459 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
460 cpu_to_le32(rcv_desc->max_rx_desc_count);
461 }
462
463 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
464 &recv_ctx->rcv_status_desc_phys_addr,
465 &recv_ctx->rcv_status_desc_pdev);
466 if (addr == NULL) {
467 DPRINTK(ERR, "bad return from"
468 " pci_alloc_consistent\n");
469 netxen_free_hw_resources(adapter);
470 err = -ENOMEM;
471 return err;
472 }
473 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
474 adapter->ctx_desc->sts_ring_addr =
475 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
476 adapter->ctx_desc->sts_ring_size =
477 cpu_to_le32(adapter->max_rx_desc_count);
478
479 }
480 /* Window = 1 */
481
482 writel(lower32(adapter->ctx_desc_phys_addr),
483 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
484 writel(upper32(adapter->ctx_desc_phys_addr),
485 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
486 writel(NETXEN_CTX_SIGNATURE | func_id,
487 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
488 return err;
489 }
490
491 void netxen_free_hw_resources(struct netxen_adapter *adapter)
492 {
493 struct netxen_recv_context *recv_ctx;
494 struct netxen_rcv_desc_ctx *rcv_desc;
495 int ctx, ring;
496
497 if (adapter->ctx_desc != NULL) {
498 pci_free_consistent(adapter->ctx_desc_pdev,
499 sizeof(struct netxen_ring_ctx) +
500 sizeof(uint32_t),
501 adapter->ctx_desc,
502 adapter->ctx_desc_phys_addr);
503 adapter->ctx_desc = NULL;
504 }
505
506 if (adapter->ahw.cmd_desc_head != NULL) {
507 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
508 sizeof(struct cmd_desc_type0) *
509 adapter->max_tx_desc_count,
510 adapter->ahw.cmd_desc_head,
511 adapter->ahw.cmd_desc_phys_addr);
512 adapter->ahw.cmd_desc_head = NULL;
513 }
514
515 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
516 recv_ctx = &adapter->recv_ctx[ctx];
517 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
518 rcv_desc = &recv_ctx->rcv_desc[ring];
519
520 if (rcv_desc->desc_head != NULL) {
521 pci_free_consistent(rcv_desc->phys_pdev,
522 RCV_DESC_RINGSIZE,
523 rcv_desc->desc_head,
524 rcv_desc->phys_addr);
525 rcv_desc->desc_head = NULL;
526 }
527 }
528
529 if (recv_ctx->rcv_status_desc_head != NULL) {
530 pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
531 STATUS_DESC_RINGSIZE,
532 recv_ctx->rcv_status_desc_head,
533 recv_ctx->
534 rcv_status_desc_phys_addr);
535 recv_ctx->rcv_status_desc_head = NULL;
536 }
537 }
538 }
539
540 void netxen_tso_check(struct netxen_adapter *adapter,
541 struct cmd_desc_type0 *desc, struct sk_buff *skb)
542 {
543 if (desc->mss) {
544 desc->total_hdr_length = (sizeof(struct ethhdr) +
545 ip_hdrlen(skb) + tcp_hdrlen(skb));
546 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
547 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
548 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
549 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
550 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
551 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
552 } else {
553 return;
554 }
555 }
556 desc->tcp_hdr_offset = skb_transport_offset(skb);
557 desc->ip_hdr_offset = skb_network_offset(skb);
558 }
559
560 int netxen_is_flash_supported(struct netxen_adapter *adapter)
561 {
562 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
563 int addr, val01, val02, i, j;
564
565 /* if the flash size less than 4Mb, make huge war cry and die */
566 for (j = 1; j < 4; j++) {
567 addr = j * NETXEN_NIC_WINDOW_MARGIN;
568 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
569 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
570 && netxen_rom_fast_read(adapter, (addr + locs[i]),
571 &val02) == 0) {
572 if (val01 == val02)
573 return -1;
574 } else
575 return -1;
576 }
577 }
578
579 return 0;
580 }
581
582 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
583 int size, u32 * buf)
584 {
585 int i, addr;
586 u32 *ptr32;
587
588 addr = base;
589 ptr32 = buf;
590 for (i = 0; i < size / sizeof(u32); i++) {
591 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
592 return -1;
593 *ptr32 = cpu_to_le32(*ptr32);
594 ptr32++;
595 addr += sizeof(u32);
596 }
597 if ((char *)buf + size > (char *)ptr32) {
598 u32 local;
599
600 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
601 return -1;
602 local = cpu_to_le32(local);
603 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
604 }
605
606 return 0;
607 }
608
609 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
610 {
611 u32 *pmac = (u32 *) & mac[0];
612
613 if (netxen_get_flash_block(adapter,
614 USER_START +
615 offsetof(struct netxen_new_user_info,
616 mac_addr),
617 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
618 return -1;
619 }
620 if (*mac == ~0ULL) {
621 if (netxen_get_flash_block(adapter,
622 USER_START_OLD +
623 offsetof(struct netxen_user_old_info,
624 mac_addr),
625 FLASH_NUM_PORTS * sizeof(u64),
626 pmac) == -1)
627 return -1;
628 if (*mac == ~0ULL)
629 return -1;
630 }
631 return 0;
632 }
633
634 /*
635 * Changes the CRB window to the specified window.
636 */
637 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
638 {
639 void __iomem *offset;
640 u32 tmp;
641 int count = 0;
642
643 if (adapter->curr_window == wndw)
644 return;
645 switch(adapter->ahw.pci_func) {
646 case 0:
647 offset = PCI_OFFSET_SECOND_RANGE(adapter,
648 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
649 break;
650 case 1:
651 offset = PCI_OFFSET_SECOND_RANGE(adapter,
652 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
653 break;
654 case 2:
655 offset = PCI_OFFSET_SECOND_RANGE(adapter,
656 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
657 break;
658 case 3:
659 offset = PCI_OFFSET_SECOND_RANGE(adapter,
660 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
661 break;
662 default:
663 printk(KERN_INFO "Changing the window for PCI function"
664 "%d\n", adapter->ahw.pci_func);
665 offset = PCI_OFFSET_SECOND_RANGE(adapter,
666 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
667 break;
668 }
669 /*
670 * Move the CRB window.
671 * We need to write to the "direct access" region of PCI
672 * to avoid a race condition where the window register has
673 * not been successfully written across CRB before the target
674 * register address is received by PCI. The direct region bypasses
675 * the CRB bus.
676 */
677
678 if (wndw & 0x1)
679 wndw = NETXEN_WINDOW_ONE;
680
681 writel(wndw, offset);
682
683 /* MUST make sure window is set before we forge on... */
684 while ((tmp = readl(offset)) != wndw) {
685 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
686 "registered properly: 0x%08x.\n",
687 netxen_nic_driver_name, __FUNCTION__, tmp);
688 mdelay(1);
689 if (count >= 10)
690 break;
691 count++;
692 }
693
694 if (wndw == NETXEN_WINDOW_ONE)
695 adapter->curr_window = 1;
696 else
697 adapter->curr_window = 0;
698 }
699
700 void netxen_load_firmware(struct netxen_adapter *adapter)
701 {
702 int i;
703 u32 data, size = 0;
704 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
705 u64 off;
706 void __iomem *addr;
707
708 size = NETXEN_FIRMWARE_LEN;
709 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
710
711 for (i = 0; i < size; i++) {
712 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
713 DPRINTK(ERR,
714 "Error in netxen_rom_fast_read(). Will skip"
715 "loading flash image\n");
716 return;
717 }
718 off = netxen_nic_pci_set_window(adapter, memaddr);
719 addr = pci_base_offset(adapter, off);
720 writel(data, addr);
721 flashaddr += 4;
722 memaddr += 4;
723 }
724 udelay(100);
725 /* make sure Casper is powered on */
726 writel(0x3fff,
727 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
728 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
729
730 udelay(100);
731 }
732
733 int
734 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
735 int len)
736 {
737 void __iomem *addr;
738
739 if (ADDR_IN_WINDOW1(off)) {
740 addr = NETXEN_CRB_NORMALIZE(adapter, off);
741 } else { /* Window 0 */
742 addr = pci_base_offset(adapter, off);
743 netxen_nic_pci_change_crbwindow(adapter, 0);
744 }
745
746 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
747 " data %llx len %d\n",
748 pci_base(adapter, off), off, addr,
749 *(unsigned long long *)data, len);
750 if (!addr) {
751 netxen_nic_pci_change_crbwindow(adapter, 1);
752 return 1;
753 }
754
755 switch (len) {
756 case 1:
757 writeb(*(u8 *) data, addr);
758 break;
759 case 2:
760 writew(*(u16 *) data, addr);
761 break;
762 case 4:
763 writel(*(u32 *) data, addr);
764 break;
765 case 8:
766 writeq(*(u64 *) data, addr);
767 break;
768 default:
769 DPRINTK(INFO,
770 "writing data %lx to offset %llx, num words=%d\n",
771 *(unsigned long *)data, off, (len >> 3));
772
773 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
774 (len >> 3));
775 break;
776 }
777 if (!ADDR_IN_WINDOW1(off))
778 netxen_nic_pci_change_crbwindow(adapter, 1);
779
780 return 0;
781 }
782
783 int
784 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
785 int len)
786 {
787 void __iomem *addr;
788
789 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
790 addr = NETXEN_CRB_NORMALIZE(adapter, off);
791 } else { /* Window 0 */
792 addr = pci_base_offset(adapter, off);
793 netxen_nic_pci_change_crbwindow(adapter, 0);
794 }
795
796 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
797 pci_base(adapter, off), off, addr);
798 if (!addr) {
799 netxen_nic_pci_change_crbwindow(adapter, 1);
800 return 1;
801 }
802 switch (len) {
803 case 1:
804 *(u8 *) data = readb(addr);
805 break;
806 case 2:
807 *(u16 *) data = readw(addr);
808 break;
809 case 4:
810 *(u32 *) data = readl(addr);
811 break;
812 case 8:
813 *(u64 *) data = readq(addr);
814 break;
815 default:
816 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
817 (len >> 3));
818 break;
819 }
820 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
821
822 if (!ADDR_IN_WINDOW1(off))
823 netxen_nic_pci_change_crbwindow(adapter, 1);
824
825 return 0;
826 }
827
828 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
829 { /* Only for window 1 */
830 void __iomem *addr;
831
832 addr = NETXEN_CRB_NORMALIZE(adapter, off);
833 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
834 pci_base(adapter, off), off, addr, val);
835 writel(val, addr);
836
837 }
838
839 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
840 { /* Only for window 1 */
841 void __iomem *addr;
842 int val;
843
844 addr = NETXEN_CRB_NORMALIZE(adapter, off);
845 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
846 pci_base(adapter, off), off, addr);
847 val = readl(addr);
848 writel(val, addr);
849
850 return val;
851 }
852
853 /* Change the window to 0, write and change back to window 1. */
854 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
855 {
856 void __iomem *addr;
857
858 netxen_nic_pci_change_crbwindow(adapter, 0);
859 addr = pci_base_offset(adapter, index);
860 writel(value, addr);
861 netxen_nic_pci_change_crbwindow(adapter, 1);
862 }
863
864 /* Change the window to 0, read and change back to window 1. */
865 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
866 {
867 void __iomem *addr;
868
869 addr = pci_base_offset(adapter, index);
870
871 netxen_nic_pci_change_crbwindow(adapter, 0);
872 *value = readl(addr);
873 netxen_nic_pci_change_crbwindow(adapter, 1);
874 }
875
876 int netxen_pci_set_window_warning_count = 0;
877
878 unsigned long
879 netxen_nic_pci_set_window(struct netxen_adapter *adapter,
880 unsigned long long addr)
881 {
882 static int ddr_mn_window = -1;
883 static int qdr_sn_window = -1;
884 int window;
885
886 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
887 /* DDR network side */
888 addr -= NETXEN_ADDR_DDR_NET;
889 window = (addr >> 25) & 0x3ff;
890 if (ddr_mn_window != window) {
891 ddr_mn_window = window;
892 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
893 NETXEN_PCIX_PH_REG
894 (PCIX_MN_WINDOW)));
895 /* MUST make sure window is set before we forge on... */
896 readl(PCI_OFFSET_SECOND_RANGE(adapter,
897 NETXEN_PCIX_PH_REG
898 (PCIX_MN_WINDOW)));
899 }
900 addr -= (window * NETXEN_WINDOW_ONE);
901 addr += NETXEN_PCI_DDR_NET;
902 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
903 addr -= NETXEN_ADDR_OCM0;
904 addr += NETXEN_PCI_OCM0;
905 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
906 addr -= NETXEN_ADDR_OCM1;
907 addr += NETXEN_PCI_OCM1;
908 } else
909 if (ADDR_IN_RANGE
910 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
911 /* QDR network side */
912 addr -= NETXEN_ADDR_QDR_NET;
913 window = (addr >> 22) & 0x3f;
914 if (qdr_sn_window != window) {
915 qdr_sn_window = window;
916 writel((window << 22),
917 PCI_OFFSET_SECOND_RANGE(adapter,
918 NETXEN_PCIX_PH_REG
919 (PCIX_SN_WINDOW)));
920 /* MUST make sure window is set before we forge on... */
921 readl(PCI_OFFSET_SECOND_RANGE(adapter,
922 NETXEN_PCIX_PH_REG
923 (PCIX_SN_WINDOW)));
924 }
925 addr -= (window * 0x400000);
926 addr += NETXEN_PCI_QDR_NET;
927 } else {
928 /*
929 * peg gdb frequently accesses memory that doesn't exist,
930 * this limits the chit chat so debugging isn't slowed down.
931 */
932 if ((netxen_pci_set_window_warning_count++ < 8)
933 || (netxen_pci_set_window_warning_count % 64 == 0))
934 printk("%s: Warning:netxen_nic_pci_set_window()"
935 " Unknown address range!\n",
936 netxen_nic_driver_name);
937
938 }
939 return addr;
940 }
941
942 int
943 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
944 {
945 if (netxen_rom_fast_write(adapter, PXE_START, 0) == -1) {
946 printk(KERN_ERR "%s: erase pxe failed\n",
947 netxen_nic_driver_name);
948 return -1;
949 }
950 return 0;
951 }
952
953 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
954 {
955 int rv = 0;
956 int addr = BRDCFG_START;
957 struct netxen_board_info *boardinfo;
958 int index;
959 u32 *ptr32;
960
961 boardinfo = &adapter->ahw.boardcfg;
962 ptr32 = (u32 *) boardinfo;
963
964 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
965 index++) {
966 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
967 return -EIO;
968 }
969 ptr32++;
970 addr += sizeof(u32);
971 }
972 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
973 printk("%s: ERROR reading %s board config."
974 " Read %x, expected %x\n", netxen_nic_driver_name,
975 netxen_nic_driver_name,
976 boardinfo->magic, NETXEN_BDINFO_MAGIC);
977 rv = -1;
978 }
979 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
980 printk("%s: Unknown board config version."
981 " Read %x, expected %x\n", netxen_nic_driver_name,
982 boardinfo->header_version, NETXEN_BDINFO_VERSION);
983 rv = -1;
984 }
985
986 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
987 switch ((netxen_brdtype_t) boardinfo->board_type) {
988 case NETXEN_BRDTYPE_P2_SB35_4G:
989 adapter->ahw.board_type = NETXEN_NIC_GBE;
990 break;
991 case NETXEN_BRDTYPE_P2_SB31_10G:
992 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
993 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
994 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
995 adapter->ahw.board_type = NETXEN_NIC_XGBE;
996 break;
997 case NETXEN_BRDTYPE_P1_BD:
998 case NETXEN_BRDTYPE_P1_SB:
999 case NETXEN_BRDTYPE_P1_SMAX:
1000 case NETXEN_BRDTYPE_P1_SOCK:
1001 adapter->ahw.board_type = NETXEN_NIC_GBE;
1002 break;
1003 default:
1004 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
1005 boardinfo->board_type);
1006 break;
1007 }
1008
1009 return rv;
1010 }
1011
1012 /* NIU access sections */
1013
1014 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1015 {
1016 netxen_nic_write_w0(adapter,
1017 NETXEN_NIU_GB_MAX_FRAME_SIZE(
1018 physical_port[adapter->portnum]), new_mtu);
1019 return 0;
1020 }
1021
1022 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1023 {
1024 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1025 if (physical_port[adapter->portnum] == 0)
1026 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1027 new_mtu);
1028 else
1029 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
1030 new_mtu);
1031 return 0;
1032 }
1033
1034 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1035 {
1036 netxen_niu_gbe_init_port(adapter, physical_port[adapter->portnum]);
1037 }
1038
1039 void
1040 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
1041 int data)
1042 {
1043 void __iomem *addr;
1044
1045 if (ADDR_IN_WINDOW1(off)) {
1046 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1047 } else {
1048 netxen_nic_pci_change_crbwindow(adapter, 0);
1049 addr = pci_base_offset(adapter, off);
1050 writel(data, addr);
1051 netxen_nic_pci_change_crbwindow(adapter, 1);
1052 }
1053 }
1054
1055 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1056 {
1057 __u32 status;
1058 __u32 autoneg;
1059 __u32 mode;
1060
1061 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1062 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1063 if (adapter->phy_read
1064 && adapter->
1065 phy_read(adapter,
1066 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1067 &status) == 0) {
1068 if (netxen_get_phy_link(status)) {
1069 switch (netxen_get_phy_speed(status)) {
1070 case 0:
1071 adapter->link_speed = SPEED_10;
1072 break;
1073 case 1:
1074 adapter->link_speed = SPEED_100;
1075 break;
1076 case 2:
1077 adapter->link_speed = SPEED_1000;
1078 break;
1079 default:
1080 adapter->link_speed = -1;
1081 break;
1082 }
1083 switch (netxen_get_phy_duplex(status)) {
1084 case 0:
1085 adapter->link_duplex = DUPLEX_HALF;
1086 break;
1087 case 1:
1088 adapter->link_duplex = DUPLEX_FULL;
1089 break;
1090 default:
1091 adapter->link_duplex = -1;
1092 break;
1093 }
1094 if (adapter->phy_read
1095 && adapter->
1096 phy_read(adapter,
1097 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1098 &autoneg) != 0)
1099 adapter->link_autoneg = autoneg;
1100 } else
1101 goto link_down;
1102 } else {
1103 link_down:
1104 adapter->link_speed = -1;
1105 adapter->link_duplex = -1;
1106 }
1107 }
1108 }
1109
1110 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1111 {
1112 int valid = 1;
1113 u32 fw_major = 0;
1114 u32 fw_minor = 0;
1115 u32 fw_build = 0;
1116 char brd_name[NETXEN_MAX_SHORT_NAME];
1117 struct netxen_new_user_info user_info;
1118 int i, addr = USER_START;
1119 __le32 *ptr32;
1120
1121 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1122 if (board_info->magic != NETXEN_BDINFO_MAGIC) {
1123 printk
1124 ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
1125 board_info->magic, NETXEN_BDINFO_MAGIC);
1126 valid = 0;
1127 }
1128 if (board_info->header_version != NETXEN_BDINFO_VERSION) {
1129 printk("NetXen Unknown board config version."
1130 " Read %x, expected %x\n",
1131 board_info->header_version, NETXEN_BDINFO_VERSION);
1132 valid = 0;
1133 }
1134 if (valid) {
1135 ptr32 = (u32 *) & user_info;
1136 for (i = 0;
1137 i < sizeof(struct netxen_new_user_info) / sizeof(u32);
1138 i++) {
1139 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1140 printk("%s: ERROR reading %s board userarea.\n",
1141 netxen_nic_driver_name,
1142 netxen_nic_driver_name);
1143 return;
1144 }
1145 ptr32++;
1146 addr += sizeof(u32);
1147 }
1148 get_brd_name_by_type(board_info->board_type, brd_name);
1149
1150 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1151 brd_name, user_info.serial_num, board_info->chip_id);
1152
1153 printk("NetXen %s Board #%d, Chip id 0x%x\n",
1154 board_info->board_type == 0x0b ? "XGB" : "GBE",
1155 board_info->board_num, board_info->chip_id);
1156 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1157 NETXEN_FW_VERSION_MAJOR));
1158 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1159 NETXEN_FW_VERSION_MINOR));
1160 fw_build =
1161 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1162
1163 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
1164 fw_build);
1165 }
1166 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1167 printk(KERN_ERR "The mismatch in driver version and firmware "
1168 "version major number\n"
1169 "Driver version major number = %d \t"
1170 "Firmware version major number = %d \n",
1171 _NETXEN_NIC_LINUX_MAJOR, fw_major);
1172 adapter->driver_mismatch = 1;
1173 }
1174 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1175 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1176 printk(KERN_ERR "The mismatch in driver version and firmware "
1177 "version minor number\n"
1178 "Driver version minor number = %d \t"
1179 "Firmware version minor number = %d \n",
1180 _NETXEN_NIC_LINUX_MINOR, fw_minor);
1181 adapter->driver_mismatch = 1;
1182 }
1183 if (adapter->driver_mismatch)
1184 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
1185 fw_major, fw_minor);
1186 }
1187
WRT350N Kernel Patches