?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PARISC] fix "ENTRY" macro redefinition
[wrt350n-kernel.git] / drivers / net / netxen / netxen_nic_niu.c
blobcef90a78351e91d51d5bb5f2c8c758cd979592bf
1 /*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Provides access to the Network Interface Unit h/w block.
31 *
32 */
33
34 #include "netxen_nic.h"
35
36 #define NETXEN_GB_MAC_SOFT_RESET 0x80000000
37 #define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
38 #define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
39 #define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
40
41 static long phy_lock_timeout = 100000000;
42
43 static inline int phy_lock(struct netxen_adapter *adapter)
44 {
45 int i;
46 int done = 0, timeout = 0;
47
48 while (!done) {
49 done =
50 readl(pci_base_offset
51 (adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK)));
52 if (done == 1)
53 break;
54 if (timeout >= phy_lock_timeout) {
55 return -1;
56 }
57 timeout++;
58 if (!in_atomic())
59 schedule();
60 else {
61 for (i = 0; i < 20; i++)
62 cpu_relax();
63 }
64 }
65
66 writel(PHY_LOCK_DRIVER,
67 NETXEN_CRB_NORMALIZE(adapter, NETXEN_PHY_LOCK_ID));
68 return 0;
69 }
70
71 static inline int phy_unlock(struct netxen_adapter *adapter)
72 {
73 readl(pci_base_offset(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK)));
74
75 return 0;
76 }
77
78 /*
79 * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
80 * mii management interface.
81 *
82 * Note: The MII management interface goes through port 0.
83 * Individual phys are addressed as follows:
84 * @param phy [15:8] phy id
85 * @param reg [7:0] register number
86 *
87 * @returns 0 on success
88 * -1 on error
89 *
90 */
91 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
92 __u32 * readval)
93 {
94 long timeout = 0;
95 long result = 0;
96 long restore = 0;
97 long phy = physical_port[adapter->portnum];
98 __u32 address;
99 __u32 command;
100 __u32 status;
101 __u32 mac_cfg0;
102
103 if (phy_lock(adapter) != 0) {
104 return -1;
105 }
106
107 /*
108 * MII mgmt all goes through port 0 MAC interface,
109 * so it cannot be in reset
110 */
111
112 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
113 &mac_cfg0, 4))
114 return -EIO;
115 if (netxen_gb_get_soft_reset(mac_cfg0)) {
116 __u32 temp;
117 temp = 0;
118 netxen_gb_tx_reset_pb(temp);
119 netxen_gb_rx_reset_pb(temp);
120 netxen_gb_tx_reset_mac(temp);
121 netxen_gb_rx_reset_mac(temp);
122 if (netxen_nic_hw_write_wx(adapter,
123 NETXEN_NIU_GB_MAC_CONFIG_0(0),
124 &temp, 4))
125 return -EIO;
126 restore = 1;
127 }
128
129 address = 0;
130 netxen_gb_mii_mgmt_reg_addr(address, reg);
131 netxen_gb_mii_mgmt_phy_addr(address, phy);
132 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
133 &address, 4))
134 return -EIO;
135 command = 0; /* turn off any prior activity */
136 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
137 &command, 4))
138 return -EIO;
139 /* send read command */
140 netxen_gb_mii_mgmt_set_read_cycle(command);
141 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
142 &command, 4))
143 return -EIO;
144
145 status = 0;
146 do {
147 if (netxen_nic_hw_read_wx(adapter,
148 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
149 &status, 4))
150 return -EIO;
151 timeout++;
152 } while ((netxen_get_gb_mii_mgmt_busy(status)
153 || netxen_get_gb_mii_mgmt_notvalid(status))
154 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
155
156 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
157 if (netxen_nic_hw_read_wx(adapter,
158 NETXEN_NIU_GB_MII_MGMT_STATUS(0),
159 readval, 4))
160 return -EIO;
161 result = 0;
162 } else
163 result = -1;
164
165 if (restore)
166 if (netxen_nic_hw_write_wx(adapter,
167 NETXEN_NIU_GB_MAC_CONFIG_0(0),
168 &mac_cfg0, 4))
169 return -EIO;
170 phy_unlock(adapter);
171 return result;
172 }
173
174 /*
175 * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
176 * mii management interface.
177 *
178 * Note: The MII management interface goes through port 0.
179 * Individual phys are addressed as follows:
180 * @param phy [15:8] phy id
181 * @param reg [7:0] register number
182 *
183 * @returns 0 on success
184 * -1 on error
185 *
186 */
187 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
188 __u32 val)
189 {
190 long timeout = 0;
191 long result = 0;
192 long restore = 0;
193 long phy = physical_port[adapter->portnum];
194 __u32 address;
195 __u32 command;
196 __u32 status;
197 __u32 mac_cfg0;
198
199 /*
200 * MII mgmt all goes through port 0 MAC interface, so it
201 * cannot be in reset
202 */
203
204 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0),
205 &mac_cfg0, 4))
206 return -EIO;
207 if (netxen_gb_get_soft_reset(mac_cfg0)) {
208 __u32 temp;
209 temp = 0;
210 netxen_gb_tx_reset_pb(temp);
211 netxen_gb_rx_reset_pb(temp);
212 netxen_gb_tx_reset_mac(temp);
213 netxen_gb_rx_reset_mac(temp);
214
215 if (netxen_nic_hw_write_wx(adapter,
216 NETXEN_NIU_GB_MAC_CONFIG_0(0),
217 &temp, 4))
218 return -EIO;
219 restore = 1;
220 }
221
222 command = 0; /* turn off any prior activity */
223 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0),
224 &command, 4))
225 return -EIO;
226
227 address = 0;
228 netxen_gb_mii_mgmt_reg_addr(address, reg);
229 netxen_gb_mii_mgmt_phy_addr(address, phy);
230 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0),
231 &address, 4))
232 return -EIO;
233
234 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0),
235 &val, 4))
236 return -EIO;
237
238 status = 0;
239 do {
240 if (netxen_nic_hw_read_wx(adapter,
241 NETXEN_NIU_GB_MII_MGMT_INDICATE(0),
242 &status, 4))
243 return -EIO;
244 timeout++;
245 } while ((netxen_get_gb_mii_mgmt_busy(status))
246 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
247
248 if (timeout < NETXEN_NIU_PHY_WAITMAX)
249 result = 0;
250 else
251 result = -EIO;
252
253 /* restore the state of port 0 MAC in case we tampered with it */
254 if (restore)
255 if (netxen_nic_hw_write_wx(adapter,
256 NETXEN_NIU_GB_MAC_CONFIG_0(0),
257 &mac_cfg0, 4))
258 return -EIO;
259
260 return result;
261 }
262
263 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
264 {
265 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x3f);
266 return 0;
267 }
268
269 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
270 {
271 int result = 0;
272 __u32 enable = 0;
273 netxen_set_phy_int_link_status_changed(enable);
274 netxen_set_phy_int_autoneg_completed(enable);
275 netxen_set_phy_int_speed_changed(enable);
276
277 if (0 !=
278 netxen_niu_gbe_phy_write(adapter,
279 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
280 enable))
281 result = -EIO;
282
283 return result;
284 }
285
286 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
287 {
288 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_INT_MASK, 0x7f);
289 return 0;
290 }
291
292 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter)
293 {
294 int result = 0;
295 if (0 !=
296 netxen_niu_gbe_phy_write(adapter,
297 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
298 result = -EIO;
299
300 return result;
301 }
302
303 int netxen_niu_xgbe_clear_phy_interrupts(struct netxen_adapter *adapter)
304 {
305 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_ACTIVE_INT, -1);
306 return 0;
307 }
308
309 int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
310 {
311 int result = 0;
312 if (0 !=
313 netxen_niu_gbe_phy_write(adapter,
314 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
315 -EIO))
316 result = -EIO;
317
318 return result;
319 }
320
321 /*
322 * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
323 *
324 */
325 void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
326 int port, long enable)
327 {
328 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
329 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
330 0x80000000);
331 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
332 0x0000f0025);
333 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
334 0xf1ff);
335 netxen_crb_writelit_adapter(adapter,
336 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
337 netxen_crb_writelit_adapter(adapter,
338 NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
339 netxen_crb_writelit_adapter(adapter,
340 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
343
344 if (enable) {
345 /*
346 * Do NOT enable flow control until a suitable solution for
347 * shutting down pause frames is found.
348 */
349 netxen_crb_writelit_adapter(adapter,
350 NETXEN_NIU_GB_MAC_CONFIG_0(port),
351 0x5);
352 }
353
354 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
355 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
356 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
357 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
358 }
359
360 /*
361 * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
362 */
363 void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
364 int port, long enable)
365 {
366 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_MODE, 0x2);
367 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
368 0x80000000);
369 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
370 0x0000f0025);
371 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port),
372 0xf2ff);
373 netxen_crb_writelit_adapter(adapter,
374 NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
377 netxen_crb_writelit_adapter(adapter,
378 (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
379 netxen_crb_writelit_adapter(adapter,
380 NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
381
382 if (enable) {
383 /*
384 * Do NOT enable flow control until a suitable solution for
385 * shutting down pause frames is found.
386 */
387 netxen_crb_writelit_adapter(adapter,
388 NETXEN_NIU_GB_MAC_CONFIG_0(port),
389 0x5);
390 }
391
392 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
393 printk(KERN_ERR PFX "ERROR enabling PHY interrupts\n");
394 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
395 printk(KERN_ERR PFX "ERROR clearing PHY interrupts\n");
396 }
397
398 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
399 {
400 int result = 0;
401 __u32 status;
402 if (adapter->disable_phy_interrupts)
403 adapter->disable_phy_interrupts(adapter);
404 mdelay(2);
405
406 if (0 ==
407 netxen_niu_gbe_phy_read(adapter,
408 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
409 &status)) {
410 if (netxen_get_phy_link(status)) {
411 if (netxen_get_phy_speed(status) == 2) {
412 netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
413 } else if ((netxen_get_phy_speed(status) == 1)
414 || (netxen_get_phy_speed(status) == 0)) {
415 netxen_niu_gbe_set_mii_mode(adapter, port, 1);
416 } else {
417 result = -1;
418 }
419
420 } else {
421 /*
422 * We don't have link. Cable must be unconnected.
423 * Enable phy interrupts so we take action when
424 * plugged in.
425 */
426
427 netxen_crb_writelit_adapter(adapter,
428 NETXEN_NIU_GB_MAC_CONFIG_0
429 (port),
430 NETXEN_GB_MAC_SOFT_RESET);
431 netxen_crb_writelit_adapter(adapter,
432 NETXEN_NIU_GB_MAC_CONFIG_0
433 (port),
434 NETXEN_GB_MAC_RESET_PROT_BLK
435 | NETXEN_GB_MAC_ENABLE_TX_RX
436 |
437 NETXEN_GB_MAC_PAUSED_FRMS);
438 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
439 printk(KERN_ERR PFX
440 "ERROR clearing PHY interrupts\n");
441 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
442 printk(KERN_ERR PFX
443 "ERROR enabling PHY interrupts\n");
444 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
445 printk(KERN_ERR PFX
446 "ERROR clearing PHY interrupts\n");
447 result = -1;
448 }
449 } else {
450 result = -EIO;
451 }
452 return result;
453 }
454
455 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
456 {
457 u32 reg;
458 u32 portnum = physical_port[adapter->portnum];
459
460 netxen_crb_writelit_adapter(adapter,
461 NETXEN_NIU_XGE_CONFIG_0+(0x10000*portnum), 0x5);
462 netxen_nic_hw_read_wx(adapter,
463 NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), &reg, 4);
464 reg = (reg & ~0x2000UL);
465 netxen_crb_writelit_adapter(adapter,
466 NETXEN_NIU_XGE_CONFIG_1+(0x10000*portnum), reg);
467
468 return 0;
469 }
470
471 /*
472 * netxen_niu_gbe_handle_phy_interrupt - Handles GbE PHY interrupts
473 * @param enable 0 means don't enable the port
474 * 1 means enable (or re-enable) the port
475 */
476 int netxen_niu_gbe_handle_phy_interrupt(struct netxen_adapter *adapter,
477 int port, long enable)
478 {
479 int result = 0;
480 __u32 int_src;
481
482 printk(KERN_INFO PFX "NETXEN: Handling PHY interrupt on port %d"
483 " (device enable = %d)\n", (int)port, (int)enable);
484
485 /*
486 * The read of the PHY INT status will clear the pending
487 * interrupt status
488 */
489 if (netxen_niu_gbe_phy_read(adapter,
490 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
491 &int_src) != 0)
492 result = -EINVAL;
493 else {
494 printk(KERN_INFO PFX "PHY Interrupt source = 0x%x \n", int_src);
495 if (netxen_get_phy_int_jabber(int_src))
496 printk(KERN_INFO PFX "jabber Interrupt ");
497 if (netxen_get_phy_int_polarity_changed(int_src))
498 printk(KERN_INFO PFX "polarity changed ");
499 if (netxen_get_phy_int_energy_detect(int_src))
500 printk(KERN_INFO PFX "energy detect \n");
501 if (netxen_get_phy_int_downshift(int_src))
502 printk(KERN_INFO PFX "downshift \n");
503 if (netxen_get_phy_int_mdi_xover_changed(int_src))
504 printk(KERN_INFO PFX "mdi_xover_changed ");
505 if (netxen_get_phy_int_fifo_over_underflow(int_src))
506 printk(KERN_INFO PFX "fifo_over_underflow ");
507 if (netxen_get_phy_int_false_carrier(int_src))
508 printk(KERN_INFO PFX "false_carrier ");
509 if (netxen_get_phy_int_symbol_error(int_src))
510 printk(KERN_INFO PFX "symbol_error ");
511 if (netxen_get_phy_int_autoneg_completed(int_src))
512 printk(KERN_INFO PFX "autoneg_completed ");
513 if (netxen_get_phy_int_page_received(int_src))
514 printk(KERN_INFO PFX "page_received ");
515 if (netxen_get_phy_int_duplex_changed(int_src))
516 printk(KERN_INFO PFX "duplex_changed ");
517 if (netxen_get_phy_int_autoneg_error(int_src))
518 printk(KERN_INFO PFX "autoneg_error ");
519 if ((netxen_get_phy_int_speed_changed(int_src))
520 || (netxen_get_phy_int_link_status_changed(int_src))) {
521 __u32 status;
522
523 printk(KERN_INFO PFX
524 "speed_changed or link status changed");
525 if (netxen_niu_gbe_phy_read
526 (adapter,
527 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
528 &status) == 0) {
529 if (netxen_get_phy_speed(status) == 2) {
530 printk
531 (KERN_INFO PFX "Link speed changed"
532 " to 1000 Mbps\n");
533 netxen_niu_gbe_set_gmii_mode(adapter,
534 port,
535 enable);
536 } else if (netxen_get_phy_speed(status) == 1) {
537 printk
538 (KERN_INFO PFX "Link speed changed"
539 " to 100 Mbps\n");
540 netxen_niu_gbe_set_mii_mode(adapter,
541 port,
542 enable);
543 } else if (netxen_get_phy_speed(status) == 0) {
544 printk
545 (KERN_INFO PFX "Link speed changed"
546 " to 10 Mbps\n");
547 netxen_niu_gbe_set_mii_mode(adapter,
548 port,
549 enable);
550 } else {
551 printk(KERN_ERR PFX "ERROR reading"
552 "PHY status. Illegal speed.\n");
553 result = -1;
554 }
555 } else {
556 printk(KERN_ERR PFX
557 "ERROR reading PHY status.\n");
558 result = -1;
559 }
560
561 }
562 printk(KERN_INFO "\n");
563 }
564 return result;
565 }
566
567 /*
568 * Return the current station MAC address.
569 * Note that the passed-in value must already be in network byte order.
570 */
571 int netxen_niu_macaddr_get(struct netxen_adapter *adapter,
572 netxen_ethernet_macaddr_t * addr)
573 {
574 u32 stationhigh;
575 u32 stationlow;
576 int phy = physical_port[adapter->portnum];
577 u8 val[8];
578
579 if (addr == NULL)
580 return -EINVAL;
581 if ((phy < 0) || (phy > 3))
582 return -EINVAL;
583
584 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy),
585 &stationhigh, 4))
586 return -EIO;
587 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy),
588 &stationlow, 4))
589 return -EIO;
590 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
591 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
592
593 memcpy(addr, val + 2, 6);
594
595 return 0;
596 }
597
598 /*
599 * Set the station MAC address.
600 * Note that the passed-in value must already be in network byte order.
601 */
602 int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
603 netxen_ethernet_macaddr_t addr)
604 {
605 u8 temp[4];
606 u32 val;
607 int phy = physical_port[adapter->portnum];
608 unsigned char mac_addr[6];
609 int i;
610
611 for (i = 0; i < 10; i++) {
612 temp[0] = temp[1] = 0;
613 memcpy(temp + 2, addr, 2);
614 val = le32_to_cpu(*(__le32 *)temp);
615 if (netxen_nic_hw_write_wx
616 (adapter, NETXEN_NIU_GB_STATION_ADDR_1(phy), &val, 4))
617 return -EIO;
618
619 memcpy(temp, ((u8 *) addr) + 2, sizeof(__le32));
620 val = le32_to_cpu(*(__le32 *)temp);
621 if (netxen_nic_hw_write_wx
622 (adapter, NETXEN_NIU_GB_STATION_ADDR_0(phy), &val, 4))
623 return -2;
624
625 netxen_niu_macaddr_get(adapter,
626 (netxen_ethernet_macaddr_t *) mac_addr);
627 if (memcmp(mac_addr, addr, 6) == 0)
628 break;
629 }
630
631 if (i == 10) {
632 printk(KERN_ERR "%s: cannot set Mac addr for %s\n",
633 netxen_nic_driver_name, adapter->netdev->name);
634 printk(KERN_ERR "MAC address set: "
635 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
636 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
637
638 printk(KERN_ERR "MAC address get: "
639 "%02x:%02x:%02x:%02x:%02x:%02x.\n",
640 mac_addr[0],
641 mac_addr[1],
642 mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
643 }
644 return 0;
645 }
646
647 /* Enable a GbE interface */
648 int netxen_niu_enable_gbe_port(struct netxen_adapter *adapter,
649 int port, netxen_niu_gbe_ifmode_t mode)
650 {
651 __u32 mac_cfg0;
652 __u32 mac_cfg1;
653 __u32 mii_cfg;
654
655 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
656 return -EINVAL;
657
658 mac_cfg0 = 0;
659 netxen_gb_soft_reset(mac_cfg0);
660 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
661 &mac_cfg0, 4))
662 return -EIO;
663 mac_cfg0 = 0;
664 netxen_gb_enable_tx(mac_cfg0);
665 netxen_gb_enable_rx(mac_cfg0);
666 netxen_gb_unset_rx_flowctl(mac_cfg0);
667 netxen_gb_tx_reset_pb(mac_cfg0);
668 netxen_gb_rx_reset_pb(mac_cfg0);
669 netxen_gb_tx_reset_mac(mac_cfg0);
670 netxen_gb_rx_reset_mac(mac_cfg0);
671
672 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
673 &mac_cfg0, 4))
674 return -EIO;
675 mac_cfg1 = 0;
676 netxen_gb_set_preamblelen(mac_cfg1, 0xf);
677 netxen_gb_set_duplex(mac_cfg1);
678 netxen_gb_set_crc_enable(mac_cfg1);
679 netxen_gb_set_padshort(mac_cfg1);
680 netxen_gb_set_checklength(mac_cfg1);
681 netxen_gb_set_hugeframes(mac_cfg1);
682
683 if (mode == NETXEN_NIU_10_100_MB) {
684 netxen_gb_set_intfmode(mac_cfg1, 1);
685 if (netxen_nic_hw_write_wx(adapter,
686 NETXEN_NIU_GB_MAC_CONFIG_1(port),
687 &mac_cfg1, 4))
688 return -EIO;
689
690 /* set mii mode */
691 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
692 (port << 3), 0);
693 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
694 (port << 3), 1);
695
696 } else if (mode == NETXEN_NIU_1000_MB) {
697 netxen_gb_set_intfmode(mac_cfg1, 2);
698 if (netxen_nic_hw_write_wx(adapter,
699 NETXEN_NIU_GB_MAC_CONFIG_1(port),
700 &mac_cfg1, 4))
701 return -EIO;
702 /* set gmii mode */
703 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_MII_MODE +
704 (port << 3), 0);
705 netxen_crb_writelit_adapter(adapter, NETXEN_NIU_GB0_GMII_MODE +
706 (port << 3), 1);
707 }
708 mii_cfg = 0;
709 netxen_gb_set_mii_mgmt_clockselect(mii_cfg, 7);
710 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port),
711 &mii_cfg, 4))
712 return -EIO;
713 mac_cfg0 = 0;
714 netxen_gb_enable_tx(mac_cfg0);
715 netxen_gb_enable_rx(mac_cfg0);
716 netxen_gb_unset_rx_flowctl(mac_cfg0);
717 netxen_gb_unset_tx_flowctl(mac_cfg0);
718
719 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
720 &mac_cfg0, 4))
721 return -EIO;
722 return 0;
723 }
724
725 /* Disable a GbE interface */
726 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
727 {
728 __u32 mac_cfg0;
729 u32 port = physical_port[adapter->portnum];
730
731 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
732 return -EINVAL;
733 mac_cfg0 = 0;
734 netxen_gb_soft_reset(mac_cfg0);
735 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
736 &mac_cfg0, 4))
737 return -EIO;
738 return 0;
739 }
740
741 /* Disable an XG interface */
742 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
743 {
744 __u32 mac_cfg;
745 u32 port = physical_port[adapter->portnum];
746
747 if (port != 0)
748 return -EINVAL;
749 mac_cfg = 0;
750 netxen_xg_soft_reset(mac_cfg);
751 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_CONFIG_0,
752 &mac_cfg, 4))
753 return -EIO;
754 return 0;
755 }
756
757 /* Set promiscuous mode for a GbE interface */
758 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
759 netxen_niu_prom_mode_t mode)
760 {
761 __u32 reg;
762 u32 port = physical_port[adapter->portnum];
763
764 if ((port < 0) || (port > NETXEN_NIU_MAX_GBE_PORTS))
765 return -EINVAL;
766
767 /* save previous contents */
768 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
769 &reg, 4))
770 return -EIO;
771 if (mode == NETXEN_NIU_PROMISC_MODE) {
772 switch (port) {
773 case 0:
774 netxen_clear_gb_drop_gb0(reg);
775 break;
776 case 1:
777 netxen_clear_gb_drop_gb1(reg);
778 break;
779 case 2:
780 netxen_clear_gb_drop_gb2(reg);
781 break;
782 case 3:
783 netxen_clear_gb_drop_gb3(reg);
784 break;
785 default:
786 return -EIO;
787 }
788 } else {
789 switch (port) {
790 case 0:
791 netxen_set_gb_drop_gb0(reg);
792 break;
793 case 1:
794 netxen_set_gb_drop_gb1(reg);
795 break;
796 case 2:
797 netxen_set_gb_drop_gb2(reg);
798 break;
799 case 3:
800 netxen_set_gb_drop_gb3(reg);
801 break;
802 default:
803 return -EIO;
804 }
805 }
806 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_GB_DROP_WRONGADDR,
807 &reg, 4))
808 return -EIO;
809 return 0;
810 }
811
812 /*
813 * Set the MAC address for an XG port
814 * Note that the passed-in value must already be in network byte order.
815 */
816 int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
817 netxen_ethernet_macaddr_t addr)
818 {
819 int phy = physical_port[adapter->portnum];
820 u8 temp[4];
821 u32 val;
822
823 if ((phy < 0) || (phy > NETXEN_NIU_MAX_XG_PORTS))
824 return -EIO;
825
826 temp[0] = temp[1] = 0;
827 switch (phy) {
828 case 0:
829 memcpy(temp + 2, addr, 2);
830 val = le32_to_cpu(*(__le32 *)temp);
831 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
832 &val, 4))
833 return -EIO;
834
835 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
836 val = le32_to_cpu(*(__le32 *)temp);
837 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
838 &val, 4))
839 return -EIO;
840 break;
841
842 case 1:
843 memcpy(temp + 2, addr, 2);
844 val = le32_to_cpu(*(__le32 *)temp);
845 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_1,
846 &val, 4))
847 return -EIO;
848
849 memcpy(&temp, ((u8 *) addr) + 2, sizeof(__le32));
850 val = le32_to_cpu(*(__le32 *)temp);
851 if (netxen_nic_hw_write_wx(adapter, NETXEN_NIU_XG1_STATION_ADDR_0_HI,
852 &val, 4))
853 return -EIO;
854 break;
855
856 default:
857 printk(KERN_ERR "Unknown port %d\n", phy);
858 break;
859 }
860
861 return 0;
862 }
863
864 /*
865 * Return the current station MAC address.
866 * Note that the passed-in value must already be in network byte order.
867 */
868 int netxen_niu_xg_macaddr_get(struct netxen_adapter *adapter,
869 netxen_ethernet_macaddr_t * addr)
870 {
871 int phy = physical_port[adapter->portnum];
872 u32 stationhigh;
873 u32 stationlow;
874 u8 val[8];
875
876 if (addr == NULL)
877 return -EINVAL;
878 if (phy != 0)
879 return -EINVAL;
880
881 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_HI,
882 &stationhigh, 4))
883 return -EIO;
884 if (netxen_nic_hw_read_wx(adapter, NETXEN_NIU_XGE_STATION_ADDR_0_1,
885 &stationlow, 4))
886 return -EIO;
887 ((__le32 *)val)[1] = cpu_to_le32(stationhigh);
888 ((__le32 *)val)[0] = cpu_to_le32(stationlow);
889
890 memcpy(addr, val + 2, 6);
891
892 return 0;
893 }
894
895 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
896 netxen_niu_prom_mode_t mode)
897 {
898 __u32 reg;
899 u32 port = physical_port[adapter->portnum];
900
901 if ((port < 0) || (port > NETXEN_NIU_MAX_XG_PORTS))
902 return -EINVAL;
903
904 if (netxen_nic_hw_read_wx(adapter,
905 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), &reg, 4))
906 return -EIO;
907 if (mode == NETXEN_NIU_PROMISC_MODE)
908 reg = (reg | 0x2000UL);
909 else
910 reg = (reg & ~0x2000UL);
911
912 netxen_crb_writelit_adapter(adapter,
913 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
914
915 return 0;
916 }
WRT350N Kernel Patches