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[PARISC] fix "ENTRY" macro redefinition
[wrt350n-kernel.git] / drivers / net / sky2.c
blob832fd69a0e59b155f4b28fbf5d502ce363d087b8
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.14"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
68
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
86
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
91 static int copybreak __read_mostly = 128;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
99 static int idle_timeout = 0;
100 module_param(idle_timeout, int, 0);
101 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
102
103 static const struct pci_device_id sky2_id_table[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
133 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
134 { 0 }
135 };
136
137 MODULE_DEVICE_TABLE(pci, sky2_id_table);
138
139 /* Avoid conditionals by using array */
140 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
141 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
142 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
143
144 /* This driver supports yukon2 chipset only */
145 static const char *yukon2_name[] = {
146 "XL", /* 0xb3 */
147 "EC Ultra", /* 0xb4 */
148 "Extreme", /* 0xb5 */
149 "EC", /* 0xb6 */
150 "FE", /* 0xb7 */
151 };
152
153 /* Access to external PHY */
154 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
155 {
156 int i;
157
158 gma_write16(hw, port, GM_SMI_DATA, val);
159 gma_write16(hw, port, GM_SMI_CTRL,
160 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
161
162 for (i = 0; i < PHY_RETRIES; i++) {
163 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
164 return 0;
165 udelay(1);
166 }
167
168 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
169 return -ETIMEDOUT;
170 }
171
172 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
173 {
174 int i;
175
176 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
177 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
178
179 for (i = 0; i < PHY_RETRIES; i++) {
180 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
181 *val = gma_read16(hw, port, GM_SMI_DATA);
182 return 0;
183 }
184
185 udelay(1);
186 }
187
188 return -ETIMEDOUT;
189 }
190
191 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
192 {
193 u16 v;
194
195 if (__gm_phy_read(hw, port, reg, &v) != 0)
196 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
197 return v;
198 }
199
200
201 static void sky2_power_on(struct sky2_hw *hw)
202 {
203 /* switch power to VCC (WA for VAUX problem) */
204 sky2_write8(hw, B0_POWER_CTRL,
205 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
206
207 /* disable Core Clock Division, */
208 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
209
210 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
211 /* enable bits are inverted */
212 sky2_write8(hw, B2_Y2_CLK_GATE,
213 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
214 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
215 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
216 else
217 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
218
219 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
220 u32 reg1;
221
222 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
223 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
224 reg1 &= P_ASPM_CONTROL_MSK;
225 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
226 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
227 }
228 }
229
230 static void sky2_power_aux(struct sky2_hw *hw)
231 {
232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
234 else
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240
241 /* switch power to VAUX */
242 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
243 sky2_write8(hw, B0_POWER_CTRL,
244 (PC_VAUX_ENA | PC_VCC_ENA |
245 PC_VAUX_ON | PC_VCC_OFF));
246 }
247
248 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
249 {
250 u16 reg;
251
252 /* disable all GMAC IRQ's */
253 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
254 /* disable PHY IRQs */
255 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
256
257 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
258 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
260 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
261
262 reg = gma_read16(hw, port, GM_RX_CTRL);
263 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
264 gma_write16(hw, port, GM_RX_CTRL, reg);
265 }
266
267 /* flow control to advertise bits */
268 static const u16 copper_fc_adv[] = {
269 [FC_NONE] = 0,
270 [FC_TX] = PHY_M_AN_ASP,
271 [FC_RX] = PHY_M_AN_PC,
272 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
273 };
274
275 /* flow control to advertise bits when using 1000BaseX */
276 static const u16 fiber_fc_adv[] = {
277 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
278 [FC_TX] = PHY_M_P_ASYM_MD_X,
279 [FC_RX] = PHY_M_P_SYM_MD_X,
280 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
281 };
282
283 /* flow control to GMA disable bits */
284 static const u16 gm_fc_disable[] = {
285 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
286 [FC_TX] = GM_GPCR_FC_RX_DIS,
287 [FC_RX] = GM_GPCR_FC_TX_DIS,
288 [FC_BOTH] = 0,
289 };
290
291
292 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293 {
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
296
297 if (sky2->autoneg == AUTONEG_ENABLE
298 && !(hw->chip_id == CHIP_ID_YUKON_XL
299 || hw->chip_id == CHIP_ID_YUKON_EC_U
300 || hw->chip_id == CHIP_ID_YUKON_EX)) {
301 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
302
303 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
304 PHY_M_EC_MAC_S_MSK);
305 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
306
307 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
308 if (hw->chip_id == CHIP_ID_YUKON_EC)
309 /* set downshift counter to 3x and enable downshift */
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
312 /* set master & slave downshift counter to 1x */
313 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (sky2_is_copper(hw)) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
330 /* downshift on PHY 88E1112 and 88E1149 is changed */
331 if (sky2->autoneg == AUTONEG_ENABLE
332 && (hw->chip_id == CHIP_ID_YUKON_XL
333 || hw->chip_id == CHIP_ID_YUKON_EC_U
334 || hw->chip_id == CHIP_ID_YUKON_EX)) {
335 /* set downshift counter to 3x and enable downshift */
336 ctrl &= ~PHY_M_PC_DSC_MSK;
337 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
338 }
339 }
340 } else {
341 /* workaround for deviation #4.88 (CRC errors) */
342 /* disable Automatic Crossover */
343
344 ctrl &= ~PHY_M_PC_MDIX_MSK;
345 }
346
347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
348
349 /* special setup for PHY 88E1112 Fiber */
350 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
351 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
352
353 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 ctrl &= ~PHY_M_MAC_MD_MSK;
357 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 if (hw->pmd_type == 'P') {
361 /* select page 1 to access Fiber registers */
362 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
363
364 /* for SFP-module set SIGDET polarity to low */
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl |= PHY_M_FIB_SIGD_POL;
367 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
368 }
369
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
371 }
372
373 ctrl = PHY_CT_RESET;
374 ct1000 = 0;
375 adv = PHY_AN_CSMA;
376 reg = 0;
377
378 if (sky2->autoneg == AUTONEG_ENABLE) {
379 if (sky2_is_copper(hw)) {
380 if (sky2->advertising & ADVERTISED_1000baseT_Full)
381 ct1000 |= PHY_M_1000C_AFD;
382 if (sky2->advertising & ADVERTISED_1000baseT_Half)
383 ct1000 |= PHY_M_1000C_AHD;
384 if (sky2->advertising & ADVERTISED_100baseT_Full)
385 adv |= PHY_M_AN_100_FD;
386 if (sky2->advertising & ADVERTISED_100baseT_Half)
387 adv |= PHY_M_AN_100_HD;
388 if (sky2->advertising & ADVERTISED_10baseT_Full)
389 adv |= PHY_M_AN_10_FD;
390 if (sky2->advertising & ADVERTISED_10baseT_Half)
391 adv |= PHY_M_AN_10_HD;
392
393 adv |= copper_fc_adv[sky2->flow_mode];
394 } else { /* special defines for FIBER (88E1040S only) */
395 if (sky2->advertising & ADVERTISED_1000baseT_Full)
396 adv |= PHY_M_AN_1000X_AFD;
397 if (sky2->advertising & ADVERTISED_1000baseT_Half)
398 adv |= PHY_M_AN_1000X_AHD;
399
400 adv |= fiber_fc_adv[sky2->flow_mode];
401 }
402
403 /* Restart Auto-negotiation */
404 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
405 } else {
406 /* forced speed/duplex settings */
407 ct1000 = PHY_M_1000C_MSE;
408
409 /* Disable auto update for duplex flow control and speed */
410 reg |= GM_GPCR_AU_ALL_DIS;
411
412 switch (sky2->speed) {
413 case SPEED_1000:
414 ctrl |= PHY_CT_SP1000;
415 reg |= GM_GPCR_SPEED_1000;
416 break;
417 case SPEED_100:
418 ctrl |= PHY_CT_SP100;
419 reg |= GM_GPCR_SPEED_100;
420 break;
421 }
422
423 if (sky2->duplex == DUPLEX_FULL) {
424 reg |= GM_GPCR_DUP_FULL;
425 ctrl |= PHY_CT_DUP_MD;
426 } else if (sky2->speed < SPEED_1000)
427 sky2->flow_mode = FC_NONE;
428
429
430 reg |= gm_fc_disable[sky2->flow_mode];
431
432 /* Forward pause packets to GMAC? */
433 if (sky2->flow_mode & FC_RX)
434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
435 else
436 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
437 }
438
439 gma_write16(hw, port, GM_GP_CTRL, reg);
440
441 if (hw->chip_id != CHIP_ID_YUKON_FE)
442 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
443
444 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
445 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
446
447 /* Setup Phy LED's */
448 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
449 ledover = 0;
450
451 switch (hw->chip_id) {
452 case CHIP_ID_YUKON_FE:
453 /* on 88E3082 these bits are at 11..9 (shifted left) */
454 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
455
456 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
457
458 /* delete ACT LED control bits */
459 ctrl &= ~PHY_M_FELP_LED1_MSK;
460 /* change ACT LED control to blink mode */
461 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
462 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
463 break;
464
465 case CHIP_ID_YUKON_XL:
466 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
467
468 /* select page 3 to access LED control register */
469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
470
471 /* set LED Function Control register */
472 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
473 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
474 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
475 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
476 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
477
478 /* set Polarity Control register */
479 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
480 (PHY_M_POLC_LS1_P_MIX(4) |
481 PHY_M_POLC_IS0_P_MIX(4) |
482 PHY_M_POLC_LOS_CTRL(2) |
483 PHY_M_POLC_INIT_CTRL(2) |
484 PHY_M_POLC_STA1_CTRL(2) |
485 PHY_M_POLC_STA0_CTRL(2)));
486
487 /* restore page register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
489 break;
490
491 case CHIP_ID_YUKON_EC_U:
492 case CHIP_ID_YUKON_EX:
493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
494
495 /* select page 3 to access LED control register */
496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
497
498 /* set LED Function Control register */
499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
501 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
503 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
504
505 /* set Blink Rate in LED Timer Control Register */
506 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
507 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
508 /* restore page register */
509 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
510 break;
511
512 default:
513 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
514 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
515 /* turn off the Rx LED (LED_RX) */
516 ledover &= ~PHY_M_LED_MO_RX;
517 }
518
519 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
520 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
521 /* apply fixes in PHY AFE */
522 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
523
524 /* increase differential signal amplitude in 10BASE-T */
525 gm_phy_write(hw, port, 0x18, 0xaa99);
526 gm_phy_write(hw, port, 0x17, 0x2011);
527
528 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
529 gm_phy_write(hw, port, 0x18, 0xa204);
530 gm_phy_write(hw, port, 0x17, 0x2002);
531
532 /* set page register to 0 */
533 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
534 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
535 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
536
537 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
538 /* turn on 100 Mbps LED (LED_LINK100) */
539 ledover |= PHY_M_LED_MO_100;
540 }
541
542 if (ledover)
543 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
544
545 }
546
547 /* Enable phy interrupt on auto-negotiation complete (or link up) */
548 if (sky2->autoneg == AUTONEG_ENABLE)
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
550 else
551 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
552 }
553
554 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
555 {
556 u32 reg1;
557 static const u32 phy_power[]
558 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
559
560 /* looks like this XL is back asswards .. */
561 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
562 onoff = !onoff;
563
564 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
565 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
566 if (onoff)
567 /* Turn off phy power saving */
568 reg1 &= ~phy_power[port];
569 else
570 reg1 |= phy_power[port];
571
572 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
573 sky2_pci_read32(hw, PCI_DEV_REG1);
574 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
575 udelay(100);
576 }
577
578 /* Force a renegotiation */
579 static void sky2_phy_reinit(struct sky2_port *sky2)
580 {
581 spin_lock_bh(&sky2->phy_lock);
582 sky2_phy_init(sky2->hw, sky2->port);
583 spin_unlock_bh(&sky2->phy_lock);
584 }
585
586 /* Put device in state to listen for Wake On Lan */
587 static void sky2_wol_init(struct sky2_port *sky2)
588 {
589 struct sky2_hw *hw = sky2->hw;
590 unsigned port = sky2->port;
591 enum flow_control save_mode;
592 u16 ctrl;
593 u32 reg1;
594
595 /* Bring hardware out of reset */
596 sky2_write16(hw, B0_CTST, CS_RST_CLR);
597 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
598
599 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
600 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
601
602 /* Force to 10/100
603 * sky2_reset will re-enable on resume
604 */
605 save_mode = sky2->flow_mode;
606 ctrl = sky2->advertising;
607
608 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
609 sky2->flow_mode = FC_NONE;
610 sky2_phy_power(hw, port, 1);
611 sky2_phy_reinit(sky2);
612
613 sky2->flow_mode = save_mode;
614 sky2->advertising = ctrl;
615
616 /* Set GMAC to no flow control and auto update for speed/duplex */
617 gma_write16(hw, port, GM_GP_CTRL,
618 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
619 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
620
621 /* Set WOL address */
622 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
623 sky2->netdev->dev_addr, ETH_ALEN);
624
625 /* Turn on appropriate WOL control bits */
626 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
627 ctrl = 0;
628 if (sky2->wol & WAKE_PHY)
629 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
630 else
631 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
632
633 if (sky2->wol & WAKE_MAGIC)
634 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
635 else
636 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
637
638 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
639 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
640
641 /* Turn on legacy PCI-Express PME mode */
642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
643 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
644 reg1 |= PCI_Y2_PME_LEGACY;
645 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
646 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
647
648 /* block receiver */
649 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
650
651 }
652
653 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
654 {
655 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
656 u16 reg;
657 int i;
658 const u8 *addr = hw->dev[port]->dev_addr;
659
660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664
665 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
666 /* WA DEV_472 -- looks like crossed wires on port 2 */
667 /* clear GMAC 1 Control reset */
668 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
669 do {
670 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
671 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
672 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
673 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
674 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
675 }
676
677 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
678
679 /* Enable Transmit FIFO Underrun */
680 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
681
682 spin_lock_bh(&sky2->phy_lock);
683 sky2_phy_init(hw, port);
684 spin_unlock_bh(&sky2->phy_lock);
685
686 /* MIB clear */
687 reg = gma_read16(hw, port, GM_PHY_ADDR);
688 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
689
690 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
691 gma_read16(hw, port, i);
692 gma_write16(hw, port, GM_PHY_ADDR, reg);
693
694 /* transmit control */
695 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
696
697 /* receive control reg: unicast + multicast + no FCS */
698 gma_write16(hw, port, GM_RX_CTRL,
699 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
700
701 /* transmit flow control */
702 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
703
704 /* transmit parameter */
705 gma_write16(hw, port, GM_TX_PARAM,
706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
707 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
708 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
709 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
710
711 /* serial mode register */
712 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
713 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
714
715 if (hw->dev[port]->mtu > ETH_DATA_LEN)
716 reg |= GM_SMOD_JUMBO_ENA;
717
718 gma_write16(hw, port, GM_SERIAL_MODE, reg);
719
720 /* virtual address for data */
721 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
722
723 /* physical address: used for pause frames */
724 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
725
726 /* ignore counter overflows */
727 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
728 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
729 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
730
731 /* Configure Rx MAC FIFO */
732 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
733 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
734 GMF_OPER_ON | GMF_RX_F_FL_ON);
735
736 /* Flush Rx MAC FIFO on any flow control or error */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
738
739 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
740 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
741
742 /* Configure Tx MAC FIFO */
743 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
744 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
745
746 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
747 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
748 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
749
750 /* set Tx GMAC FIFO Almost Empty Threshold */
751 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
752 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
753
754 if (hw->dev[port]->mtu > ETH_DATA_LEN)
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
756 TX_JUMBO_ENA | TX_STFW_DIS);
757 else
758 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
759 TX_JUMBO_DIS | TX_STFW_ENA);
760 }
761
762 }
763
764 /* Assign Ram Buffer allocation to queue */
765 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
766 {
767 u32 end;
768
769 /* convert from K bytes to qwords used for hw register */
770 start *= 1024/8;
771 space *= 1024/8;
772 end = start + space - 1;
773
774 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
775 sky2_write32(hw, RB_ADDR(q, RB_START), start);
776 sky2_write32(hw, RB_ADDR(q, RB_END), end);
777 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
778 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
779
780 if (q == Q_R1 || q == Q_R2) {
781 u32 tp = space - space/4;
782
783 /* On receive queue's set the thresholds
784 * give receiver priority when > 3/4 full
785 * send pause when down to 2K
786 */
787 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
788 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
789
790 tp = space - 2048/8;
791 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
792 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
793 } else {
794 /* Enable store & forward on Tx queue's because
795 * Tx FIFO is only 1K on Yukon
796 */
797 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
798 }
799
800 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
801 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
802 }
803
804 /* Setup Bus Memory Interface */
805 static void sky2_qset(struct sky2_hw *hw, u16 q)
806 {
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
808 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
809 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
810 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
811 }
812
813 /* Setup prefetch unit registers. This is the interface between
814 * hardware and driver list elements
815 */
816 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
817 u64 addr, u32 last)
818 {
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
821 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
823 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
824 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
825
826 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
827 }
828
829 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
830 {
831 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
832
833 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
834 le->ctrl = 0;
835 return le;
836 }
837
838 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
839 struct sky2_tx_le *le)
840 {
841 return sky2->tx_ring + (le - sky2->tx_le);
842 }
843
844 /* Update chip's next pointer */
845 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
846 {
847 /* Make sure write' to descriptors are complete before we tell hardware */
848 wmb();
849 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
850
851 /* Synchronize I/O on since next processor may write to tail */
852 mmiowb();
853 }
854
855
856 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
857 {
858 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
859 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
860 le->ctrl = 0;
861 return le;
862 }
863
864 /* Return high part of DMA address (could be 32 or 64 bit) */
865 static inline u32 high32(dma_addr_t a)
866 {
867 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
868 }
869
870 /* Build description to hardware for one receive segment */
871 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
872 dma_addr_t map, unsigned len)
873 {
874 struct sky2_rx_le *le;
875 u32 hi = high32(map);
876
877 if (sky2->rx_addr64 != hi) {
878 le = sky2_next_rx(sky2);
879 le->addr = cpu_to_le32(hi);
880 le->opcode = OP_ADDR64 | HW_OWNER;
881 sky2->rx_addr64 = high32(map + len);
882 }
883
884 le = sky2_next_rx(sky2);
885 le->addr = cpu_to_le32((u32) map);
886 le->length = cpu_to_le16(len);
887 le->opcode = op | HW_OWNER;
888 }
889
890 /* Build description to hardware for one possibly fragmented skb */
891 static void sky2_rx_submit(struct sky2_port *sky2,
892 const struct rx_ring_info *re)
893 {
894 int i;
895
896 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
897
898 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
899 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
900 }
901
902
903 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
904 unsigned size)
905 {
906 struct sk_buff *skb = re->skb;
907 int i;
908
909 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
910 pci_unmap_len_set(re, data_size, size);
911
912 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
913 re->frag_addr[i] = pci_map_page(pdev,
914 skb_shinfo(skb)->frags[i].page,
915 skb_shinfo(skb)->frags[i].page_offset,
916 skb_shinfo(skb)->frags[i].size,
917 PCI_DMA_FROMDEVICE);
918 }
919
920 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
921 {
922 struct sk_buff *skb = re->skb;
923 int i;
924
925 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
926 PCI_DMA_FROMDEVICE);
927
928 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
929 pci_unmap_page(pdev, re->frag_addr[i],
930 skb_shinfo(skb)->frags[i].size,
931 PCI_DMA_FROMDEVICE);
932 }
933
934 /* Tell chip where to start receive checksum.
935 * Actually has two checksums, but set both same to avoid possible byte
936 * order problems.
937 */
938 static void rx_set_checksum(struct sky2_port *sky2)
939 {
940 struct sky2_rx_le *le;
941
942 le = sky2_next_rx(sky2);
943 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
944 le->ctrl = 0;
945 le->opcode = OP_TCPSTART | HW_OWNER;
946
947 sky2_write32(sky2->hw,
948 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
949 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
950
951 }
952
953 /*
954 * The RX Stop command will not work for Yukon-2 if the BMU does not
955 * reach the end of packet and since we can't make sure that we have
956 * incoming data, we must reset the BMU while it is not doing a DMA
957 * transfer. Since it is possible that the RX path is still active,
958 * the RX RAM buffer will be stopped first, so any possible incoming
959 * data will not trigger a DMA. After the RAM buffer is stopped, the
960 * BMU is polled until any DMA in progress is ended and only then it
961 * will be reset.
962 */
963 static void sky2_rx_stop(struct sky2_port *sky2)
964 {
965 struct sky2_hw *hw = sky2->hw;
966 unsigned rxq = rxqaddr[sky2->port];
967 int i;
968
969 /* disable the RAM Buffer receive queue */
970 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
971
972 for (i = 0; i < 0xffff; i++)
973 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
974 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
975 goto stopped;
976
977 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
978 sky2->netdev->name);
979 stopped:
980 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
981
982 /* reset the Rx prefetch unit */
983 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
984 mmiowb();
985 }
986
987 /* Clean out receive buffer area, assumes receiver hardware stopped */
988 static void sky2_rx_clean(struct sky2_port *sky2)
989 {
990 unsigned i;
991
992 memset(sky2->rx_le, 0, RX_LE_BYTES);
993 for (i = 0; i < sky2->rx_pending; i++) {
994 struct rx_ring_info *re = sky2->rx_ring + i;
995
996 if (re->skb) {
997 sky2_rx_unmap_skb(sky2->hw->pdev, re);
998 kfree_skb(re->skb);
999 re->skb = NULL;
1000 }
1001 }
1002 }
1003
1004 /* Basic MII support */
1005 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1006 {
1007 struct mii_ioctl_data *data = if_mii(ifr);
1008 struct sky2_port *sky2 = netdev_priv(dev);
1009 struct sky2_hw *hw = sky2->hw;
1010 int err = -EOPNOTSUPP;
1011
1012 if (!netif_running(dev))
1013 return -ENODEV; /* Phy still in reset */
1014
1015 switch (cmd) {
1016 case SIOCGMIIPHY:
1017 data->phy_id = PHY_ADDR_MARV;
1018
1019 /* fallthru */
1020 case SIOCGMIIREG: {
1021 u16 val = 0;
1022
1023 spin_lock_bh(&sky2->phy_lock);
1024 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1025 spin_unlock_bh(&sky2->phy_lock);
1026
1027 data->val_out = val;
1028 break;
1029 }
1030
1031 case SIOCSMIIREG:
1032 if (!capable(CAP_NET_ADMIN))
1033 return -EPERM;
1034
1035 spin_lock_bh(&sky2->phy_lock);
1036 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1037 data->val_in);
1038 spin_unlock_bh(&sky2->phy_lock);
1039 break;
1040 }
1041 return err;
1042 }
1043
1044 #ifdef SKY2_VLAN_TAG_USED
1045 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1046 {
1047 struct sky2_port *sky2 = netdev_priv(dev);
1048 struct sky2_hw *hw = sky2->hw;
1049 u16 port = sky2->port;
1050
1051 netif_tx_lock_bh(dev);
1052
1053 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1054 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1055 sky2->vlgrp = grp;
1056
1057 netif_tx_unlock_bh(dev);
1058 }
1059
1060 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1061 {
1062 struct sky2_port *sky2 = netdev_priv(dev);
1063 struct sky2_hw *hw = sky2->hw;
1064 u16 port = sky2->port;
1065
1066 netif_tx_lock_bh(dev);
1067
1068 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1069 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1070 vlan_group_set_device(sky2->vlgrp, vid, NULL);
1071
1072 netif_tx_unlock_bh(dev);
1073 }
1074 #endif
1075
1076 /*
1077 * Allocate an skb for receiving. If the MTU is large enough
1078 * make the skb non-linear with a fragment list of pages.
1079 *
1080 * It appears the hardware has a bug in the FIFO logic that
1081 * cause it to hang if the FIFO gets overrun and the receive buffer
1082 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1083 * aligned except if slab debugging is enabled.
1084 */
1085 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1086 {
1087 struct sk_buff *skb;
1088 unsigned long p;
1089 int i;
1090
1091 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1092 if (!skb)
1093 goto nomem;
1094
1095 p = (unsigned long) skb->data;
1096 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1097
1098 for (i = 0; i < sky2->rx_nfrags; i++) {
1099 struct page *page = alloc_page(GFP_ATOMIC);
1100
1101 if (!page)
1102 goto free_partial;
1103 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1104 }
1105
1106 return skb;
1107 free_partial:
1108 kfree_skb(skb);
1109 nomem:
1110 return NULL;
1111 }
1112
1113 /*
1114 * Allocate and setup receiver buffer pool.
1115 * Normal case this ends up creating one list element for skb
1116 * in the receive ring. Worst case if using large MTU and each
1117 * allocation falls on a different 64 bit region, that results
1118 * in 6 list elements per ring entry.
1119 * One element is used for checksum enable/disable, and one
1120 * extra to avoid wrap.
1121 */
1122 static int sky2_rx_start(struct sky2_port *sky2)
1123 {
1124 struct sky2_hw *hw = sky2->hw;
1125 struct rx_ring_info *re;
1126 unsigned rxq = rxqaddr[sky2->port];
1127 unsigned i, size, space, thresh;
1128
1129 sky2->rx_put = sky2->rx_next = 0;
1130 sky2_qset(hw, rxq);
1131
1132 /* On PCI express lowering the watermark gives better performance */
1133 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1134 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1135
1136 /* These chips have no ram buffer?
1137 * MAC Rx RAM Read is controlled by hardware */
1138 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1139 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1140 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1141 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1142
1143 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1144
1145 rx_set_checksum(sky2);
1146
1147 /* Space needed for frame data + headers rounded up */
1148 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1149 + 8;
1150
1151 /* Stopping point for hardware truncation */
1152 thresh = (size - 8) / sizeof(u32);
1153
1154 /* Account for overhead of skb - to avoid order > 0 allocation */
1155 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1156 + sizeof(struct skb_shared_info);
1157
1158 sky2->rx_nfrags = space >> PAGE_SHIFT;
1159 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1160
1161 if (sky2->rx_nfrags != 0) {
1162 /* Compute residue after pages */
1163 space = sky2->rx_nfrags << PAGE_SHIFT;
1164
1165 if (space < size)
1166 size -= space;
1167 else
1168 size = 0;
1169
1170 /* Optimize to handle small packets and headers */
1171 if (size < copybreak)
1172 size = copybreak;
1173 if (size < ETH_HLEN)
1174 size = ETH_HLEN;
1175 }
1176 sky2->rx_data_size = size;
1177
1178 /* Fill Rx ring */
1179 for (i = 0; i < sky2->rx_pending; i++) {
1180 re = sky2->rx_ring + i;
1181
1182 re->skb = sky2_rx_alloc(sky2);
1183 if (!re->skb)
1184 goto nomem;
1185
1186 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1187 sky2_rx_submit(sky2, re);
1188 }
1189
1190 /*
1191 * The receiver hangs if it receives frames larger than the
1192 * packet buffer. As a workaround, truncate oversize frames, but
1193 * the register is limited to 9 bits, so if you do frames > 2052
1194 * you better get the MTU right!
1195 */
1196 if (thresh > 0x1ff)
1197 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1198 else {
1199 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1200 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1201 }
1202
1203 /* Tell chip about available buffers */
1204 sky2_put_idx(hw, rxq, sky2->rx_put);
1205 return 0;
1206 nomem:
1207 sky2_rx_clean(sky2);
1208 return -ENOMEM;
1209 }
1210
1211 /* Bring up network interface. */
1212 static int sky2_up(struct net_device *dev)
1213 {
1214 struct sky2_port *sky2 = netdev_priv(dev);
1215 struct sky2_hw *hw = sky2->hw;
1216 unsigned port = sky2->port;
1217 u32 ramsize, imask;
1218 int cap, err = -ENOMEM;
1219 struct net_device *otherdev = hw->dev[sky2->port^1];
1220
1221 /*
1222 * On dual port PCI-X card, there is an problem where status
1223 * can be received out of order due to split transactions
1224 */
1225 if (otherdev && netif_running(otherdev) &&
1226 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1227 struct sky2_port *osky2 = netdev_priv(otherdev);
1228 u16 cmd;
1229
1230 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1231 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1232 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1233
1234 sky2->rx_csum = 0;
1235 osky2->rx_csum = 0;
1236 }
1237
1238 if (netif_msg_ifup(sky2))
1239 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1240
1241 /* must be power of 2 */
1242 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1243 TX_RING_SIZE *
1244 sizeof(struct sky2_tx_le),
1245 &sky2->tx_le_map);
1246 if (!sky2->tx_le)
1247 goto err_out;
1248
1249 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1250 GFP_KERNEL);
1251 if (!sky2->tx_ring)
1252 goto err_out;
1253 sky2->tx_prod = sky2->tx_cons = 0;
1254
1255 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1256 &sky2->rx_le_map);
1257 if (!sky2->rx_le)
1258 goto err_out;
1259 memset(sky2->rx_le, 0, RX_LE_BYTES);
1260
1261 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1262 GFP_KERNEL);
1263 if (!sky2->rx_ring)
1264 goto err_out;
1265
1266 sky2_phy_power(hw, port, 1);
1267
1268 sky2_mac_init(hw, port);
1269
1270 /* Register is number of 4K blocks on internal RAM buffer. */
1271 ramsize = sky2_read8(hw, B2_E_0) * 4;
1272 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1273
1274 if (ramsize > 0) {
1275 u32 rxspace;
1276
1277 if (ramsize < 16)
1278 rxspace = ramsize / 2;
1279 else
1280 rxspace = 8 + (2*(ramsize - 16))/3;
1281
1282 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1283 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1284
1285 /* Make sure SyncQ is disabled */
1286 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1287 RB_RST_SET);
1288 }
1289
1290 sky2_qset(hw, txqaddr[port]);
1291
1292 /* Set almost empty threshold */
1293 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1294 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1295 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1296
1297 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1298 TX_RING_SIZE - 1);
1299
1300 err = sky2_rx_start(sky2);
1301 if (err)
1302 goto err_out;
1303
1304 /* Enable interrupts from phy/mac for port */
1305 imask = sky2_read32(hw, B0_IMSK);
1306 imask |= portirq_msk[port];
1307 sky2_write32(hw, B0_IMSK, imask);
1308
1309 return 0;
1310
1311 err_out:
1312 if (sky2->rx_le) {
1313 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1314 sky2->rx_le, sky2->rx_le_map);
1315 sky2->rx_le = NULL;
1316 }
1317 if (sky2->tx_le) {
1318 pci_free_consistent(hw->pdev,
1319 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1320 sky2->tx_le, sky2->tx_le_map);
1321 sky2->tx_le = NULL;
1322 }
1323 kfree(sky2->tx_ring);
1324 kfree(sky2->rx_ring);
1325
1326 sky2->tx_ring = NULL;
1327 sky2->rx_ring = NULL;
1328 return err;
1329 }
1330
1331 /* Modular subtraction in ring */
1332 static inline int tx_dist(unsigned tail, unsigned head)
1333 {
1334 return (head - tail) & (TX_RING_SIZE - 1);
1335 }
1336
1337 /* Number of list elements available for next tx */
1338 static inline int tx_avail(const struct sky2_port *sky2)
1339 {
1340 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1341 }
1342
1343 /* Estimate of number of transmit list elements required */
1344 static unsigned tx_le_req(const struct sk_buff *skb)
1345 {
1346 unsigned count;
1347
1348 count = sizeof(dma_addr_t) / sizeof(u32);
1349 count += skb_shinfo(skb)->nr_frags * count;
1350
1351 if (skb_is_gso(skb))
1352 ++count;
1353
1354 if (skb->ip_summed == CHECKSUM_PARTIAL)
1355 ++count;
1356
1357 return count;
1358 }
1359
1360 /*
1361 * Put one packet in ring for transmit.
1362 * A single packet can generate multiple list elements, and
1363 * the number of ring elements will probably be less than the number
1364 * of list elements used.
1365 */
1366 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1367 {
1368 struct sky2_port *sky2 = netdev_priv(dev);
1369 struct sky2_hw *hw = sky2->hw;
1370 struct sky2_tx_le *le = NULL;
1371 struct tx_ring_info *re;
1372 unsigned i, len;
1373 dma_addr_t mapping;
1374 u32 addr64;
1375 u16 mss;
1376 u8 ctrl;
1377
1378 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1379 return NETDEV_TX_BUSY;
1380
1381 if (unlikely(netif_msg_tx_queued(sky2)))
1382 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1383 dev->name, sky2->tx_prod, skb->len);
1384
1385 len = skb_headlen(skb);
1386 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1387 addr64 = high32(mapping);
1388
1389 /* Send high bits if changed or crosses boundary */
1390 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1391 le = get_tx_le(sky2);
1392 le->addr = cpu_to_le32(addr64);
1393 le->opcode = OP_ADDR64 | HW_OWNER;
1394 sky2->tx_addr64 = high32(mapping + len);
1395 }
1396
1397 /* Check for TCP Segmentation Offload */
1398 mss = skb_shinfo(skb)->gso_size;
1399 if (mss != 0) {
1400 mss += tcp_optlen(skb); /* TCP options */
1401 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
1402 mss += ETH_HLEN;
1403
1404 if (mss != sky2->tx_last_mss) {
1405 le = get_tx_le(sky2);
1406 le->addr = cpu_to_le32(mss);
1407 le->opcode = OP_LRGLEN | HW_OWNER;
1408 sky2->tx_last_mss = mss;
1409 }
1410 }
1411
1412 ctrl = 0;
1413 #ifdef SKY2_VLAN_TAG_USED
1414 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1415 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1416 if (!le) {
1417 le = get_tx_le(sky2);
1418 le->addr = 0;
1419 le->opcode = OP_VLAN|HW_OWNER;
1420 } else
1421 le->opcode |= OP_VLAN;
1422 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1423 ctrl |= INS_VLAN;
1424 }
1425 #endif
1426
1427 /* Handle TCP checksum offload */
1428 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1429 const unsigned offset = skb_transport_offset(skb);
1430 u32 tcpsum;
1431
1432 tcpsum = offset << 16; /* sum start */
1433 tcpsum |= offset + skb->csum_offset; /* sum write */
1434
1435 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1436 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1437 ctrl |= UDPTCP;
1438
1439 if (tcpsum != sky2->tx_tcpsum) {
1440 sky2->tx_tcpsum = tcpsum;
1441
1442 le = get_tx_le(sky2);
1443 le->addr = cpu_to_le32(tcpsum);
1444 le->length = 0; /* initial checksum value */
1445 le->ctrl = 1; /* one packet */
1446 le->opcode = OP_TCPLISW | HW_OWNER;
1447 }
1448 }
1449
1450 le = get_tx_le(sky2);
1451 le->addr = cpu_to_le32((u32) mapping);
1452 le->length = cpu_to_le16(len);
1453 le->ctrl = ctrl;
1454 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1455
1456 re = tx_le_re(sky2, le);
1457 re->skb = skb;
1458 pci_unmap_addr_set(re, mapaddr, mapping);
1459 pci_unmap_len_set(re, maplen, len);
1460
1461 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1462 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1463
1464 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1465 frag->size, PCI_DMA_TODEVICE);
1466 addr64 = high32(mapping);
1467 if (addr64 != sky2->tx_addr64) {
1468 le = get_tx_le(sky2);
1469 le->addr = cpu_to_le32(addr64);
1470 le->ctrl = 0;
1471 le->opcode = OP_ADDR64 | HW_OWNER;
1472 sky2->tx_addr64 = addr64;
1473 }
1474
1475 le = get_tx_le(sky2);
1476 le->addr = cpu_to_le32((u32) mapping);
1477 le->length = cpu_to_le16(frag->size);
1478 le->ctrl = ctrl;
1479 le->opcode = OP_BUFFER | HW_OWNER;
1480
1481 re = tx_le_re(sky2, le);
1482 re->skb = skb;
1483 pci_unmap_addr_set(re, mapaddr, mapping);
1484 pci_unmap_len_set(re, maplen, frag->size);
1485 }
1486
1487 le->ctrl |= EOP;
1488
1489 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1490 netif_stop_queue(dev);
1491
1492 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1493
1494 dev->trans_start = jiffies;
1495 return NETDEV_TX_OK;
1496 }
1497
1498 /*
1499 * Free ring elements from starting at tx_cons until "done"
1500 *
1501 * NB: the hardware will tell us about partial completion of multi-part
1502 * buffers so make sure not to free skb to early.
1503 */
1504 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1505 {
1506 struct net_device *dev = sky2->netdev;
1507 struct pci_dev *pdev = sky2->hw->pdev;
1508 unsigned idx;
1509
1510 BUG_ON(done >= TX_RING_SIZE);
1511
1512 for (idx = sky2->tx_cons; idx != done;
1513 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1514 struct sky2_tx_le *le = sky2->tx_le + idx;
1515 struct tx_ring_info *re = sky2->tx_ring + idx;
1516
1517 switch(le->opcode & ~HW_OWNER) {
1518 case OP_LARGESEND:
1519 case OP_PACKET:
1520 pci_unmap_single(pdev,
1521 pci_unmap_addr(re, mapaddr),
1522 pci_unmap_len(re, maplen),
1523 PCI_DMA_TODEVICE);
1524 break;
1525 case OP_BUFFER:
1526 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1527 pci_unmap_len(re, maplen),
1528 PCI_DMA_TODEVICE);
1529 break;
1530 }
1531
1532 if (le->ctrl & EOP) {
1533 if (unlikely(netif_msg_tx_done(sky2)))
1534 printk(KERN_DEBUG "%s: tx done %u\n",
1535 dev->name, idx);
1536 sky2->net_stats.tx_packets++;
1537 sky2->net_stats.tx_bytes += re->skb->len;
1538
1539 dev_kfree_skb_any(re->skb);
1540 }
1541
1542 le->opcode = 0; /* paranoia */
1543 }
1544
1545 sky2->tx_cons = idx;
1546 smp_mb();
1547
1548 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1549 netif_wake_queue(dev);
1550 }
1551
1552 /* Cleanup all untransmitted buffers, assume transmitter not running */
1553 static void sky2_tx_clean(struct net_device *dev)
1554 {
1555 struct sky2_port *sky2 = netdev_priv(dev);
1556
1557 netif_tx_lock_bh(dev);
1558 sky2_tx_complete(sky2, sky2->tx_prod);
1559 netif_tx_unlock_bh(dev);
1560 }
1561
1562 /* Network shutdown */
1563 static int sky2_down(struct net_device *dev)
1564 {
1565 struct sky2_port *sky2 = netdev_priv(dev);
1566 struct sky2_hw *hw = sky2->hw;
1567 unsigned port = sky2->port;
1568 u16 ctrl;
1569 u32 imask;
1570
1571 /* Never really got started! */
1572 if (!sky2->tx_le)
1573 return 0;
1574
1575 if (netif_msg_ifdown(sky2))
1576 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1577
1578 /* Stop more packets from being queued */
1579 netif_stop_queue(dev);
1580 netif_carrier_off(dev);
1581
1582 /* Disable port IRQ */
1583 imask = sky2_read32(hw, B0_IMSK);
1584 imask &= ~portirq_msk[port];
1585 sky2_write32(hw, B0_IMSK, imask);
1586
1587 sky2_gmac_reset(hw, port);
1588
1589 /* Stop transmitter */
1590 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1591 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1592
1593 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1594 RB_RST_SET | RB_DIS_OP_MD);
1595
1596 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1597 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1598 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1599
1600 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1601
1602 /* Workaround shared GMAC reset */
1603 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1604 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1605 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1606
1607 /* Disable Force Sync bit and Enable Alloc bit */
1608 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1609 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1610
1611 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1612 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1613 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1614
1615 /* Reset the PCI FIFO of the async Tx queue */
1616 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1617 BMU_RST_SET | BMU_FIFO_RST);
1618
1619 /* Reset the Tx prefetch units */
1620 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1621 PREF_UNIT_RST_SET);
1622
1623 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1624
1625 sky2_rx_stop(sky2);
1626
1627 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1628 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1629
1630 sky2_phy_power(hw, port, 0);
1631
1632 /* turn off LED's */
1633 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1634
1635 synchronize_irq(hw->pdev->irq);
1636
1637 sky2_tx_clean(dev);
1638 sky2_rx_clean(sky2);
1639
1640 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1641 sky2->rx_le, sky2->rx_le_map);
1642 kfree(sky2->rx_ring);
1643
1644 pci_free_consistent(hw->pdev,
1645 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1646 sky2->tx_le, sky2->tx_le_map);
1647 kfree(sky2->tx_ring);
1648
1649 sky2->tx_le = NULL;
1650 sky2->rx_le = NULL;
1651
1652 sky2->rx_ring = NULL;
1653 sky2->tx_ring = NULL;
1654
1655 return 0;
1656 }
1657
1658 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1659 {
1660 if (!sky2_is_copper(hw))
1661 return SPEED_1000;
1662
1663 if (hw->chip_id == CHIP_ID_YUKON_FE)
1664 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1665
1666 switch (aux & PHY_M_PS_SPEED_MSK) {
1667 case PHY_M_PS_SPEED_1000:
1668 return SPEED_1000;
1669 case PHY_M_PS_SPEED_100:
1670 return SPEED_100;
1671 default:
1672 return SPEED_10;
1673 }
1674 }
1675
1676 static void sky2_link_up(struct sky2_port *sky2)
1677 {
1678 struct sky2_hw *hw = sky2->hw;
1679 unsigned port = sky2->port;
1680 u16 reg;
1681 static const char *fc_name[] = {
1682 [FC_NONE] = "none",
1683 [FC_TX] = "tx",
1684 [FC_RX] = "rx",
1685 [FC_BOTH] = "both",
1686 };
1687
1688 /* enable Rx/Tx */
1689 reg = gma_read16(hw, port, GM_GP_CTRL);
1690 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1691 gma_write16(hw, port, GM_GP_CTRL, reg);
1692
1693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1694
1695 netif_carrier_on(sky2->netdev);
1696 netif_wake_queue(sky2->netdev);
1697
1698 /* Turn on link LED */
1699 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1700 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1701
1702 if (hw->chip_id == CHIP_ID_YUKON_XL
1703 || hw->chip_id == CHIP_ID_YUKON_EC_U
1704 || hw->chip_id == CHIP_ID_YUKON_EX) {
1705 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1706 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1707
1708 switch(sky2->speed) {
1709 case SPEED_10:
1710 led |= PHY_M_LEDC_INIT_CTRL(7);
1711 break;
1712
1713 case SPEED_100:
1714 led |= PHY_M_LEDC_STA1_CTRL(7);
1715 break;
1716
1717 case SPEED_1000:
1718 led |= PHY_M_LEDC_STA0_CTRL(7);
1719 break;
1720 }
1721
1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1723 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1724 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1725 }
1726
1727 if (netif_msg_link(sky2))
1728 printk(KERN_INFO PFX
1729 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1730 sky2->netdev->name, sky2->speed,
1731 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1732 fc_name[sky2->flow_status]);
1733 }
1734
1735 static void sky2_link_down(struct sky2_port *sky2)
1736 {
1737 struct sky2_hw *hw = sky2->hw;
1738 unsigned port = sky2->port;
1739 u16 reg;
1740
1741 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1742
1743 reg = gma_read16(hw, port, GM_GP_CTRL);
1744 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1745 gma_write16(hw, port, GM_GP_CTRL, reg);
1746
1747 netif_carrier_off(sky2->netdev);
1748 netif_stop_queue(sky2->netdev);
1749
1750 /* Turn on link LED */
1751 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1752
1753 if (netif_msg_link(sky2))
1754 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1755
1756 sky2_phy_init(hw, port);
1757 }
1758
1759 static enum flow_control sky2_flow(int rx, int tx)
1760 {
1761 if (rx)
1762 return tx ? FC_BOTH : FC_RX;
1763 else
1764 return tx ? FC_TX : FC_NONE;
1765 }
1766
1767 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1768 {
1769 struct sky2_hw *hw = sky2->hw;
1770 unsigned port = sky2->port;
1771 u16 advert, lpa;
1772
1773 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1774 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1775 if (lpa & PHY_M_AN_RF) {
1776 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1777 return -1;
1778 }
1779
1780 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1781 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1782 sky2->netdev->name);
1783 return -1;
1784 }
1785
1786 sky2->speed = sky2_phy_speed(hw, aux);
1787 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1788
1789 /* Since the pause result bits seem to in different positions on
1790 * different chips. look at registers.
1791 */
1792 if (!sky2_is_copper(hw)) {
1793 /* Shift for bits in fiber PHY */
1794 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1795 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1796
1797 if (advert & ADVERTISE_1000XPAUSE)
1798 advert |= ADVERTISE_PAUSE_CAP;
1799 if (advert & ADVERTISE_1000XPSE_ASYM)
1800 advert |= ADVERTISE_PAUSE_ASYM;
1801 if (lpa & LPA_1000XPAUSE)
1802 lpa |= LPA_PAUSE_CAP;
1803 if (lpa & LPA_1000XPAUSE_ASYM)
1804 lpa |= LPA_PAUSE_ASYM;
1805 }
1806
1807 sky2->flow_status = FC_NONE;
1808 if (advert & ADVERTISE_PAUSE_CAP) {
1809 if (lpa & LPA_PAUSE_CAP)
1810 sky2->flow_status = FC_BOTH;
1811 else if (advert & ADVERTISE_PAUSE_ASYM)
1812 sky2->flow_status = FC_RX;
1813 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1814 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1815 sky2->flow_status = FC_TX;
1816 }
1817
1818 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1819 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1820 sky2->flow_status = FC_NONE;
1821
1822 if (sky2->flow_status & FC_TX)
1823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1824 else
1825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1826
1827 return 0;
1828 }
1829
1830 /* Interrupt from PHY */
1831 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1832 {
1833 struct net_device *dev = hw->dev[port];
1834 struct sky2_port *sky2 = netdev_priv(dev);
1835 u16 istatus, phystat;
1836
1837 if (!netif_running(dev))
1838 return;
1839
1840 spin_lock(&sky2->phy_lock);
1841 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1842 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1843
1844 if (netif_msg_intr(sky2))
1845 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1846 sky2->netdev->name, istatus, phystat);
1847
1848 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1849 if (sky2_autoneg_done(sky2, phystat) == 0)
1850 sky2_link_up(sky2);
1851 goto out;
1852 }
1853
1854 if (istatus & PHY_M_IS_LSP_CHANGE)
1855 sky2->speed = sky2_phy_speed(hw, phystat);
1856
1857 if (istatus & PHY_M_IS_DUP_CHANGE)
1858 sky2->duplex =
1859 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1860
1861 if (istatus & PHY_M_IS_LST_CHANGE) {
1862 if (phystat & PHY_M_PS_LINK_UP)
1863 sky2_link_up(sky2);
1864 else
1865 sky2_link_down(sky2);
1866 }
1867 out:
1868 spin_unlock(&sky2->phy_lock);
1869 }
1870
1871 /* Transmit timeout is only called if we are running, carrier is up
1872 * and tx queue is full (stopped).
1873 */
1874 static void sky2_tx_timeout(struct net_device *dev)
1875 {
1876 struct sky2_port *sky2 = netdev_priv(dev);
1877 struct sky2_hw *hw = sky2->hw;
1878
1879 if (netif_msg_timer(sky2))
1880 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1881
1882 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1883 dev->name, sky2->tx_cons, sky2->tx_prod,
1884 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1885 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1886
1887 /* can't restart safely under softirq */
1888 schedule_work(&hw->restart_work);
1889 }
1890
1891 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1892 {
1893 struct sky2_port *sky2 = netdev_priv(dev);
1894 struct sky2_hw *hw = sky2->hw;
1895 unsigned port = sky2->port;
1896 int err;
1897 u16 ctl, mode;
1898 u32 imask;
1899
1900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1901 return -EINVAL;
1902
1903 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1904 return -EINVAL;
1905
1906 if (!netif_running(dev)) {
1907 dev->mtu = new_mtu;
1908 return 0;
1909 }
1910
1911 imask = sky2_read32(hw, B0_IMSK);
1912 sky2_write32(hw, B0_IMSK, 0);
1913
1914 dev->trans_start = jiffies; /* prevent tx timeout */
1915 netif_stop_queue(dev);
1916 netif_poll_disable(hw->dev[0]);
1917
1918 synchronize_irq(hw->pdev->irq);
1919
1920 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1921 if (new_mtu > ETH_DATA_LEN) {
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_ENA | TX_STFW_DIS);
1924 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1925 } else
1926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1927 TX_JUMBO_DIS | TX_STFW_ENA);
1928 }
1929
1930 ctl = gma_read16(hw, port, GM_GP_CTRL);
1931 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1932 sky2_rx_stop(sky2);
1933 sky2_rx_clean(sky2);
1934
1935 dev->mtu = new_mtu;
1936
1937 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1938 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1939
1940 if (dev->mtu > ETH_DATA_LEN)
1941 mode |= GM_SMOD_JUMBO_ENA;
1942
1943 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1944
1945 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1946
1947 err = sky2_rx_start(sky2);
1948 sky2_write32(hw, B0_IMSK, imask);
1949
1950 if (err)
1951 dev_close(dev);
1952 else {
1953 gma_write16(hw, port, GM_GP_CTRL, ctl);
1954
1955 netif_poll_enable(hw->dev[0]);
1956 netif_wake_queue(dev);
1957 }
1958
1959 return err;
1960 }
1961
1962 /* For small just reuse existing skb for next receive */
1963 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1964 const struct rx_ring_info *re,
1965 unsigned length)
1966 {
1967 struct sk_buff *skb;
1968
1969 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1970 if (likely(skb)) {
1971 skb_reserve(skb, 2);
1972 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1973 length, PCI_DMA_FROMDEVICE);
1974 skb_copy_from_linear_data(re->skb, skb->data, length);
1975 skb->ip_summed = re->skb->ip_summed;
1976 skb->csum = re->skb->csum;
1977 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1978 length, PCI_DMA_FROMDEVICE);
1979 re->skb->ip_summed = CHECKSUM_NONE;
1980 skb_put(skb, length);
1981 }
1982 return skb;
1983 }
1984
1985 /* Adjust length of skb with fragments to match received data */
1986 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1987 unsigned int length)
1988 {
1989 int i, num_frags;
1990 unsigned int size;
1991
1992 /* put header into skb */
1993 size = min(length, hdr_space);
1994 skb->tail += size;
1995 skb->len += size;
1996 length -= size;
1997
1998 num_frags = skb_shinfo(skb)->nr_frags;
1999 for (i = 0; i < num_frags; i++) {
2000 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2001
2002 if (length == 0) {
2003 /* don't need this page */
2004 __free_page(frag->page);
2005 --skb_shinfo(skb)->nr_frags;
2006 } else {
2007 size = min(length, (unsigned) PAGE_SIZE);
2008
2009 frag->size = size;
2010 skb->data_len += size;
2011 skb->truesize += size;
2012 skb->len += size;
2013 length -= size;
2014 }
2015 }
2016 }
2017
2018 /* Normal packet - take skb from ring element and put in a new one */
2019 static struct sk_buff *receive_new(struct sky2_port *sky2,
2020 struct rx_ring_info *re,
2021 unsigned int length)
2022 {
2023 struct sk_buff *skb, *nskb;
2024 unsigned hdr_space = sky2->rx_data_size;
2025
2026 pr_debug(PFX "receive new length=%d\n", length);
2027
2028 /* Don't be tricky about reusing pages (yet) */
2029 nskb = sky2_rx_alloc(sky2);
2030 if (unlikely(!nskb))
2031 return NULL;
2032
2033 skb = re->skb;
2034 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2035
2036 prefetch(skb->data);
2037 re->skb = nskb;
2038 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2039
2040 if (skb_shinfo(skb)->nr_frags)
2041 skb_put_frags(skb, hdr_space, length);
2042 else
2043 skb_put(skb, length);
2044 return skb;
2045 }
2046
2047 /*
2048 * Receive one packet.
2049 * For larger packets, get new buffer.
2050 */
2051 static struct sk_buff *sky2_receive(struct net_device *dev,
2052 u16 length, u32 status)
2053 {
2054 struct sky2_port *sky2 = netdev_priv(dev);
2055 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2056 struct sk_buff *skb = NULL;
2057
2058 if (unlikely(netif_msg_rx_status(sky2)))
2059 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2060 dev->name, sky2->rx_next, status, length);
2061
2062 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2063 prefetch(sky2->rx_ring + sky2->rx_next);
2064
2065 if (status & GMR_FS_ANY_ERR)
2066 goto error;
2067
2068 if (!(status & GMR_FS_RX_OK))
2069 goto resubmit;
2070
2071 if (length < copybreak)
2072 skb = receive_copy(sky2, re, length);
2073 else
2074 skb = receive_new(sky2, re, length);
2075 resubmit:
2076 sky2_rx_submit(sky2, re);
2077
2078 return skb;
2079
2080 error:
2081 ++sky2->net_stats.rx_errors;
2082 if (status & GMR_FS_RX_FF_OV) {
2083 sky2->net_stats.rx_over_errors++;
2084 goto resubmit;
2085 }
2086
2087 if (netif_msg_rx_err(sky2) && net_ratelimit())
2088 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2089 dev->name, status, length);
2090
2091 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2092 sky2->net_stats.rx_length_errors++;
2093 if (status & GMR_FS_FRAGMENT)
2094 sky2->net_stats.rx_frame_errors++;
2095 if (status & GMR_FS_CRC_ERR)
2096 sky2->net_stats.rx_crc_errors++;
2097
2098 goto resubmit;
2099 }
2100
2101 /* Transmit complete */
2102 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2103 {
2104 struct sky2_port *sky2 = netdev_priv(dev);
2105
2106 if (netif_running(dev)) {
2107 netif_tx_lock(dev);
2108 sky2_tx_complete(sky2, last);
2109 netif_tx_unlock(dev);
2110 }
2111 }
2112
2113 /* Process status response ring */
2114 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2115 {
2116 struct sky2_port *sky2;
2117 int work_done = 0;
2118 unsigned buf_write[2] = { 0, 0 };
2119 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2120
2121 rmb();
2122
2123 while (hw->st_idx != hwidx) {
2124 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2125 struct net_device *dev;
2126 struct sk_buff *skb;
2127 u32 status;
2128 u16 length;
2129
2130 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2131
2132 BUG_ON(le->link >= 2);
2133 dev = hw->dev[le->link];
2134
2135 sky2 = netdev_priv(dev);
2136 length = le16_to_cpu(le->length);
2137 status = le32_to_cpu(le->status);
2138
2139 switch (le->opcode & ~HW_OWNER) {
2140 case OP_RXSTAT:
2141 skb = sky2_receive(dev, length, status);
2142 if (unlikely(!skb)) {
2143 sky2->net_stats.rx_dropped++;
2144 goto force_update;
2145 }
2146
2147 skb->protocol = eth_type_trans(skb, dev);
2148 sky2->net_stats.rx_packets++;
2149 sky2->net_stats.rx_bytes += skb->len;
2150 dev->last_rx = jiffies;
2151
2152 #ifdef SKY2_VLAN_TAG_USED
2153 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2154 vlan_hwaccel_receive_skb(skb,
2155 sky2->vlgrp,
2156 be16_to_cpu(sky2->rx_tag));
2157 } else
2158 #endif
2159 netif_receive_skb(skb);
2160
2161 /* Update receiver after 16 frames */
2162 if (++buf_write[le->link] == RX_BUF_WRITE) {
2163 force_update:
2164 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2165 buf_write[le->link] = 0;
2166 }
2167
2168 /* Stop after net poll weight */
2169 if (++work_done >= to_do)
2170 goto exit_loop;
2171 break;
2172
2173 #ifdef SKY2_VLAN_TAG_USED
2174 case OP_RXVLAN:
2175 sky2->rx_tag = length;
2176 break;
2177
2178 case OP_RXCHKSVLAN:
2179 sky2->rx_tag = length;
2180 /* fall through */
2181 #endif
2182 case OP_RXCHKS:
2183 if (!sky2->rx_csum)
2184 break;
2185
2186 /* Both checksum counters are programmed to start at
2187 * the same offset, so unless there is a problem they
2188 * should match. This failure is an early indication that
2189 * hardware receive checksumming won't work.
2190 */
2191 if (likely(status >> 16 == (status & 0xffff))) {
2192 skb = sky2->rx_ring[sky2->rx_next].skb;
2193 skb->ip_summed = CHECKSUM_COMPLETE;
2194 skb->csum = status & 0xffff;
2195 } else {
2196 printk(KERN_NOTICE PFX "%s: hardware receive "
2197 "checksum problem (status = %#x)\n",
2198 dev->name, status);
2199 sky2->rx_csum = 0;
2200 sky2_write32(sky2->hw,
2201 Q_ADDR(rxqaddr[le->link], Q_CSR),
2202 BMU_DIS_RX_CHKSUM);
2203 }
2204 break;
2205
2206 case OP_TXINDEXLE:
2207 /* TX index reports status for both ports */
2208 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2209 sky2_tx_done(hw->dev[0], status & 0xfff);
2210 if (hw->dev[1])
2211 sky2_tx_done(hw->dev[1],
2212 ((status >> 24) & 0xff)
2213 | (u16)(length & 0xf) << 8);
2214 break;
2215
2216 default:
2217 if (net_ratelimit())
2218 printk(KERN_WARNING PFX
2219 "unknown status opcode 0x%x\n", le->opcode);
2220 goto exit_loop;
2221 }
2222 }
2223
2224 /* Fully processed status ring so clear irq */
2225 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2226 mmiowb();
2227
2228 exit_loop:
2229 if (buf_write[0]) {
2230 sky2 = netdev_priv(hw->dev[0]);
2231 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2232 }
2233
2234 if (buf_write[1]) {
2235 sky2 = netdev_priv(hw->dev[1]);
2236 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2237 }
2238
2239 return work_done;
2240 }
2241
2242 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2243 {
2244 struct net_device *dev = hw->dev[port];
2245
2246 if (net_ratelimit())
2247 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2248 dev->name, status);
2249
2250 if (status & Y2_IS_PAR_RD1) {
2251 if (net_ratelimit())
2252 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2253 dev->name);
2254 /* Clear IRQ */
2255 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2256 }
2257
2258 if (status & Y2_IS_PAR_WR1) {
2259 if (net_ratelimit())
2260 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2261 dev->name);
2262
2263 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2264 }
2265
2266 if (status & Y2_IS_PAR_MAC1) {
2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2269 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2270 }
2271
2272 if (status & Y2_IS_PAR_RX1) {
2273 if (net_ratelimit())
2274 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2275 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2276 }
2277
2278 if (status & Y2_IS_TCP_TXA1) {
2279 if (net_ratelimit())
2280 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2281 dev->name);
2282 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2283 }
2284 }
2285
2286 static void sky2_hw_intr(struct sky2_hw *hw)
2287 {
2288 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2289
2290 if (status & Y2_IS_TIST_OV)
2291 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2292
2293 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2294 u16 pci_err;
2295
2296 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2297 if (net_ratelimit())
2298 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2299 pci_err);
2300
2301 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2302 sky2_pci_write16(hw, PCI_STATUS,
2303 pci_err | PCI_STATUS_ERROR_BITS);
2304 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2305 }
2306
2307 if (status & Y2_IS_PCI_EXP) {
2308 /* PCI-Express uncorrectable Error occurred */
2309 u32 pex_err;
2310
2311 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2312
2313 if (net_ratelimit())
2314 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2315 pex_err);
2316
2317 /* clear the interrupt */
2318 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2319 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2320 0xffffffffUL);
2321 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2322
2323 if (pex_err & PEX_FATAL_ERRORS) {
2324 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2325 hwmsk &= ~Y2_IS_PCI_EXP;
2326 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2327 }
2328 }
2329
2330 if (status & Y2_HWE_L1_MASK)
2331 sky2_hw_error(hw, 0, status);
2332 status >>= 8;
2333 if (status & Y2_HWE_L1_MASK)
2334 sky2_hw_error(hw, 1, status);
2335 }
2336
2337 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2338 {
2339 struct net_device *dev = hw->dev[port];
2340 struct sky2_port *sky2 = netdev_priv(dev);
2341 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2342
2343 if (netif_msg_intr(sky2))
2344 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2345 dev->name, status);
2346
2347 if (status & GM_IS_RX_CO_OV)
2348 gma_read16(hw, port, GM_RX_IRQ_SRC);
2349
2350 if (status & GM_IS_TX_CO_OV)
2351 gma_read16(hw, port, GM_TX_IRQ_SRC);
2352
2353 if (status & GM_IS_RX_FF_OR) {
2354 ++sky2->net_stats.rx_fifo_errors;
2355 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2356 }
2357
2358 if (status & GM_IS_TX_FF_UR) {
2359 ++sky2->net_stats.tx_fifo_errors;
2360 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2361 }
2362 }
2363
2364 /* This should never happen it is a bug. */
2365 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2366 u16 q, unsigned ring_size)
2367 {
2368 struct net_device *dev = hw->dev[port];
2369 struct sky2_port *sky2 = netdev_priv(dev);
2370 unsigned idx;
2371 const u64 *le = (q == Q_R1 || q == Q_R2)
2372 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2373
2374 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2375 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2376 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2377 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2378
2379 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2380 }
2381
2382 /* If idle then force a fake soft NAPI poll once a second
2383 * to work around cases where sharing an edge triggered interrupt.
2384 */
2385 static inline void sky2_idle_start(struct sky2_hw *hw)
2386 {
2387 if (idle_timeout > 0)
2388 mod_timer(&hw->idle_timer,
2389 jiffies + msecs_to_jiffies(idle_timeout));
2390 }
2391
2392 static void sky2_idle(unsigned long arg)
2393 {
2394 struct sky2_hw *hw = (struct sky2_hw *) arg;
2395 struct net_device *dev = hw->dev[0];
2396
2397 if (__netif_rx_schedule_prep(dev))
2398 __netif_rx_schedule(dev);
2399
2400 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2401 }
2402
2403 /* Hardware/software error handling */
2404 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2405 {
2406 if (net_ratelimit())
2407 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2408
2409 if (status & Y2_IS_HW_ERR)
2410 sky2_hw_intr(hw);
2411
2412 if (status & Y2_IS_IRQ_MAC1)
2413 sky2_mac_intr(hw, 0);
2414
2415 if (status & Y2_IS_IRQ_MAC2)
2416 sky2_mac_intr(hw, 1);
2417
2418 if (status & Y2_IS_CHK_RX1)
2419 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2420
2421 if (status & Y2_IS_CHK_RX2)
2422 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2423
2424 if (status & Y2_IS_CHK_TXA1)
2425 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2426
2427 if (status & Y2_IS_CHK_TXA2)
2428 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2429 }
2430
2431 static int sky2_poll(struct net_device *dev0, int *budget)
2432 {
2433 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2434 int work_limit = min(dev0->quota, *budget);
2435 int work_done = 0;
2436 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2437
2438 if (unlikely(status & Y2_IS_ERROR))
2439 sky2_err_intr(hw, status);
2440
2441 if (status & Y2_IS_IRQ_PHY1)
2442 sky2_phy_intr(hw, 0);
2443
2444 if (status & Y2_IS_IRQ_PHY2)
2445 sky2_phy_intr(hw, 1);
2446
2447 work_done = sky2_status_intr(hw, work_limit);
2448 if (work_done < work_limit) {
2449 netif_rx_complete(dev0);
2450
2451 /* end of interrupt, re-enables also acts as I/O synchronization */
2452 sky2_read32(hw, B0_Y2_SP_LISR);
2453 return 0;
2454 } else {
2455 *budget -= work_done;
2456 dev0->quota -= work_done;
2457 return 1;
2458 }
2459 }
2460
2461 static irqreturn_t sky2_intr(int irq, void *dev_id)
2462 {
2463 struct sky2_hw *hw = dev_id;
2464 struct net_device *dev0 = hw->dev[0];
2465 u32 status;
2466
2467 /* Reading this mask interrupts as side effect */
2468 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2469 if (status == 0 || status == ~0)
2470 return IRQ_NONE;
2471
2472 prefetch(&hw->st_le[hw->st_idx]);
2473 if (likely(__netif_rx_schedule_prep(dev0)))
2474 __netif_rx_schedule(dev0);
2475
2476 return IRQ_HANDLED;
2477 }
2478
2479 #ifdef CONFIG_NET_POLL_CONTROLLER
2480 static void sky2_netpoll(struct net_device *dev)
2481 {
2482 struct sky2_port *sky2 = netdev_priv(dev);
2483 struct net_device *dev0 = sky2->hw->dev[0];
2484
2485 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2486 __netif_rx_schedule(dev0);
2487 }
2488 #endif
2489
2490 /* Chip internal frequency for clock calculations */
2491 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2492 {
2493 switch (hw->chip_id) {
2494 case CHIP_ID_YUKON_EC:
2495 case CHIP_ID_YUKON_EC_U:
2496 case CHIP_ID_YUKON_EX:
2497 return 125; /* 125 Mhz */
2498 case CHIP_ID_YUKON_FE:
2499 return 100; /* 100 Mhz */
2500 default: /* YUKON_XL */
2501 return 156; /* 156 Mhz */
2502 }
2503 }
2504
2505 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2506 {
2507 return sky2_mhz(hw) * us;
2508 }
2509
2510 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2511 {
2512 return clk / sky2_mhz(hw);
2513 }
2514
2515
2516 static int __devinit sky2_init(struct sky2_hw *hw)
2517 {
2518 u8 t8;
2519
2520 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2521
2522 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2523 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2524 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2525 hw->chip_id);
2526 return -EOPNOTSUPP;
2527 }
2528
2529 if (hw->chip_id == CHIP_ID_YUKON_EX)
2530 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2531 "Please report success or failure to <netdev@vger.kernel.org>\n");
2532
2533 /* Make sure and enable all clocks */
2534 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2535 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2536
2537 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2538
2539 /* This rev is really old, and requires untested workarounds */
2540 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2541 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2542 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2543 hw->chip_id, hw->chip_rev);
2544 return -EOPNOTSUPP;
2545 }
2546
2547 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2548 hw->ports = 1;
2549 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2550 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2551 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2552 ++hw->ports;
2553 }
2554
2555 return 0;
2556 }
2557
2558 static void sky2_reset(struct sky2_hw *hw)
2559 {
2560 u16 status;
2561 int i;
2562
2563 /* disable ASF */
2564 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2565 status = sky2_read16(hw, HCU_CCSR);
2566 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2567 HCU_CCSR_UC_STATE_MSK);
2568 sky2_write16(hw, HCU_CCSR, status);
2569 } else
2570 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2571 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2572
2573 /* do a SW reset */
2574 sky2_write8(hw, B0_CTST, CS_RST_SET);
2575 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2576
2577 /* clear PCI errors, if any */
2578 status = sky2_pci_read16(hw, PCI_STATUS);
2579
2580 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2581 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2582
2583
2584 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2585
2586 /* clear any PEX errors */
2587 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2588 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2589
2590
2591 sky2_power_on(hw);
2592
2593 for (i = 0; i < hw->ports; i++) {
2594 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2595 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2596 }
2597
2598 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2599
2600 /* Clear I2C IRQ noise */
2601 sky2_write32(hw, B2_I2C_IRQ, 1);
2602
2603 /* turn off hardware timer (unused) */
2604 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2605 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2606
2607 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2608
2609 /* Turn off descriptor polling */
2610 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2611
2612 /* Turn off receive timestamp */
2613 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2614 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2615
2616 /* enable the Tx Arbiters */
2617 for (i = 0; i < hw->ports; i++)
2618 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2619
2620 /* Initialize ram interface */
2621 for (i = 0; i < hw->ports; i++) {
2622 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2623
2624 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2629 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2632 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2633 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2634 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2635 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2636 }
2637
2638 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2639
2640 for (i = 0; i < hw->ports; i++)
2641 sky2_gmac_reset(hw, i);
2642
2643 memset(hw->st_le, 0, STATUS_LE_BYTES);
2644 hw->st_idx = 0;
2645
2646 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2647 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2648
2649 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2650 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2651
2652 /* Set the list last index */
2653 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2654
2655 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2656 sky2_write8(hw, STAT_FIFO_WM, 16);
2657
2658 /* set Status-FIFO ISR watermark */
2659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2660 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2661 else
2662 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2663
2664 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2665 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2666 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2667
2668 /* enable status unit */
2669 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2670
2671 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2672 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2673 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2674 }
2675
2676 static void sky2_restart(struct work_struct *work)
2677 {
2678 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2679 struct net_device *dev;
2680 int i, err;
2681
2682 dev_dbg(&hw->pdev->dev, "restarting\n");
2683
2684 del_timer_sync(&hw->idle_timer);
2685
2686 rtnl_lock();
2687 sky2_write32(hw, B0_IMSK, 0);
2688 sky2_read32(hw, B0_IMSK);
2689
2690 netif_poll_disable(hw->dev[0]);
2691
2692 for (i = 0; i < hw->ports; i++) {
2693 dev = hw->dev[i];
2694 if (netif_running(dev))
2695 sky2_down(dev);
2696 }
2697
2698 sky2_reset(hw);
2699 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2700 netif_poll_enable(hw->dev[0]);
2701
2702 for (i = 0; i < hw->ports; i++) {
2703 dev = hw->dev[i];
2704 if (netif_running(dev)) {
2705 err = sky2_up(dev);
2706 if (err) {
2707 printk(KERN_INFO PFX "%s: could not restart %d\n",
2708 dev->name, err);
2709 dev_close(dev);
2710 }
2711 }
2712 }
2713
2714 sky2_idle_start(hw);
2715
2716 rtnl_unlock();
2717 }
2718
2719 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2720 {
2721 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2722 }
2723
2724 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2725 {
2726 const struct sky2_port *sky2 = netdev_priv(dev);
2727
2728 wol->supported = sky2_wol_supported(sky2->hw);
2729 wol->wolopts = sky2->wol;
2730 }
2731
2732 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2733 {
2734 struct sky2_port *sky2 = netdev_priv(dev);
2735 struct sky2_hw *hw = sky2->hw;
2736
2737 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2738 return -EOPNOTSUPP;
2739
2740 sky2->wol = wol->wolopts;
2741
2742 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2743 sky2_write32(hw, B0_CTST, sky2->wol
2744 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2745
2746 if (!netif_running(dev))
2747 sky2_wol_init(sky2);
2748 return 0;
2749 }
2750
2751 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2752 {
2753 if (sky2_is_copper(hw)) {
2754 u32 modes = SUPPORTED_10baseT_Half
2755 | SUPPORTED_10baseT_Full
2756 | SUPPORTED_100baseT_Half
2757 | SUPPORTED_100baseT_Full
2758 | SUPPORTED_Autoneg | SUPPORTED_TP;
2759
2760 if (hw->chip_id != CHIP_ID_YUKON_FE)
2761 modes |= SUPPORTED_1000baseT_Half
2762 | SUPPORTED_1000baseT_Full;
2763 return modes;
2764 } else
2765 return SUPPORTED_1000baseT_Half
2766 | SUPPORTED_1000baseT_Full
2767 | SUPPORTED_Autoneg
2768 | SUPPORTED_FIBRE;
2769 }
2770
2771 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2772 {
2773 struct sky2_port *sky2 = netdev_priv(dev);
2774 struct sky2_hw *hw = sky2->hw;
2775
2776 ecmd->transceiver = XCVR_INTERNAL;
2777 ecmd->supported = sky2_supported_modes(hw);
2778 ecmd->phy_address = PHY_ADDR_MARV;
2779 if (sky2_is_copper(hw)) {
2780 ecmd->supported = SUPPORTED_10baseT_Half
2781 | SUPPORTED_10baseT_Full
2782 | SUPPORTED_100baseT_Half
2783 | SUPPORTED_100baseT_Full
2784 | SUPPORTED_1000baseT_Half
2785 | SUPPORTED_1000baseT_Full
2786 | SUPPORTED_Autoneg | SUPPORTED_TP;
2787 ecmd->port = PORT_TP;
2788 ecmd->speed = sky2->speed;
2789 } else {
2790 ecmd->speed = SPEED_1000;
2791 ecmd->port = PORT_FIBRE;
2792 }
2793
2794 ecmd->advertising = sky2->advertising;
2795 ecmd->autoneg = sky2->autoneg;
2796 ecmd->duplex = sky2->duplex;
2797 return 0;
2798 }
2799
2800 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2801 {
2802 struct sky2_port *sky2 = netdev_priv(dev);
2803 const struct sky2_hw *hw = sky2->hw;
2804 u32 supported = sky2_supported_modes(hw);
2805
2806 if (ecmd->autoneg == AUTONEG_ENABLE) {
2807 ecmd->advertising = supported;
2808 sky2->duplex = -1;
2809 sky2->speed = -1;
2810 } else {
2811 u32 setting;
2812
2813 switch (ecmd->speed) {
2814 case SPEED_1000:
2815 if (ecmd->duplex == DUPLEX_FULL)
2816 setting = SUPPORTED_1000baseT_Full;
2817 else if (ecmd->duplex == DUPLEX_HALF)
2818 setting = SUPPORTED_1000baseT_Half;
2819 else
2820 return -EINVAL;
2821 break;
2822 case SPEED_100:
2823 if (ecmd->duplex == DUPLEX_FULL)
2824 setting = SUPPORTED_100baseT_Full;
2825 else if (ecmd->duplex == DUPLEX_HALF)
2826 setting = SUPPORTED_100baseT_Half;
2827 else
2828 return -EINVAL;
2829 break;
2830
2831 case SPEED_10:
2832 if (ecmd->duplex == DUPLEX_FULL)
2833 setting = SUPPORTED_10baseT_Full;
2834 else if (ecmd->duplex == DUPLEX_HALF)
2835 setting = SUPPORTED_10baseT_Half;
2836 else
2837 return -EINVAL;
2838 break;
2839 default:
2840 return -EINVAL;
2841 }
2842
2843 if ((setting & supported) == 0)
2844 return -EINVAL;
2845
2846 sky2->speed = ecmd->speed;
2847 sky2->duplex = ecmd->duplex;
2848 }
2849
2850 sky2->autoneg = ecmd->autoneg;
2851 sky2->advertising = ecmd->advertising;
2852
2853 if (netif_running(dev))
2854 sky2_phy_reinit(sky2);
2855
2856 return 0;
2857 }
2858
2859 static void sky2_get_drvinfo(struct net_device *dev,
2860 struct ethtool_drvinfo *info)
2861 {
2862 struct sky2_port *sky2 = netdev_priv(dev);
2863
2864 strcpy(info->driver, DRV_NAME);
2865 strcpy(info->version, DRV_VERSION);
2866 strcpy(info->fw_version, "N/A");
2867 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2868 }
2869
2870 static const struct sky2_stat {
2871 char name[ETH_GSTRING_LEN];
2872 u16 offset;
2873 } sky2_stats[] = {
2874 { "tx_bytes", GM_TXO_OK_HI },
2875 { "rx_bytes", GM_RXO_OK_HI },
2876 { "tx_broadcast", GM_TXF_BC_OK },
2877 { "rx_broadcast", GM_RXF_BC_OK },
2878 { "tx_multicast", GM_TXF_MC_OK },
2879 { "rx_multicast", GM_RXF_MC_OK },
2880 { "tx_unicast", GM_TXF_UC_OK },
2881 { "rx_unicast", GM_RXF_UC_OK },
2882 { "tx_mac_pause", GM_TXF_MPAUSE },
2883 { "rx_mac_pause", GM_RXF_MPAUSE },
2884 { "collisions", GM_TXF_COL },
2885 { "late_collision",GM_TXF_LAT_COL },
2886 { "aborted", GM_TXF_ABO_COL },
2887 { "single_collisions", GM_TXF_SNG_COL },
2888 { "multi_collisions", GM_TXF_MUL_COL },
2889
2890 { "rx_short", GM_RXF_SHT },
2891 { "rx_runt", GM_RXE_FRAG },
2892 { "rx_64_byte_packets", GM_RXF_64B },
2893 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2894 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2895 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2896 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2897 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2898 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2899 { "rx_too_long", GM_RXF_LNG_ERR },
2900 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2901 { "rx_jabber", GM_RXF_JAB_PKT },
2902 { "rx_fcs_error", GM_RXF_FCS_ERR },
2903
2904 { "tx_64_byte_packets", GM_TXF_64B },
2905 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2906 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2907 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2908 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2909 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2910 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2911 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2912 };
2913
2914 static u32 sky2_get_rx_csum(struct net_device *dev)
2915 {
2916 struct sky2_port *sky2 = netdev_priv(dev);
2917
2918 return sky2->rx_csum;
2919 }
2920
2921 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2922 {
2923 struct sky2_port *sky2 = netdev_priv(dev);
2924
2925 sky2->rx_csum = data;
2926
2927 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2928 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2929
2930 return 0;
2931 }
2932
2933 static u32 sky2_get_msglevel(struct net_device *netdev)
2934 {
2935 struct sky2_port *sky2 = netdev_priv(netdev);
2936 return sky2->msg_enable;
2937 }
2938
2939 static int sky2_nway_reset(struct net_device *dev)
2940 {
2941 struct sky2_port *sky2 = netdev_priv(dev);
2942
2943 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2944 return -EINVAL;
2945
2946 sky2_phy_reinit(sky2);
2947
2948 return 0;
2949 }
2950
2951 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2952 {
2953 struct sky2_hw *hw = sky2->hw;
2954 unsigned port = sky2->port;
2955 int i;
2956
2957 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2958 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2959 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2960 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2961
2962 for (i = 2; i < count; i++)
2963 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2964 }
2965
2966 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2967 {
2968 struct sky2_port *sky2 = netdev_priv(netdev);
2969 sky2->msg_enable = value;
2970 }
2971
2972 static int sky2_get_stats_count(struct net_device *dev)
2973 {
2974 return ARRAY_SIZE(sky2_stats);
2975 }
2976
2977 static void sky2_get_ethtool_stats(struct net_device *dev,
2978 struct ethtool_stats *stats, u64 * data)
2979 {
2980 struct sky2_port *sky2 = netdev_priv(dev);
2981
2982 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2983 }
2984
2985 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2986 {
2987 int i;
2988
2989 switch (stringset) {
2990 case ETH_SS_STATS:
2991 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2992 memcpy(data + i * ETH_GSTRING_LEN,
2993 sky2_stats[i].name, ETH_GSTRING_LEN);
2994 break;
2995 }
2996 }
2997
2998 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2999 {
3000 struct sky2_port *sky2 = netdev_priv(dev);
3001 return &sky2->net_stats;
3002 }
3003
3004 static int sky2_set_mac_address(struct net_device *dev, void *p)
3005 {
3006 struct sky2_port *sky2 = netdev_priv(dev);
3007 struct sky2_hw *hw = sky2->hw;
3008 unsigned port = sky2->port;
3009 const struct sockaddr *addr = p;
3010
3011 if (!is_valid_ether_addr(addr->sa_data))
3012 return -EADDRNOTAVAIL;
3013
3014 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3015 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3016 dev->dev_addr, ETH_ALEN);
3017 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3018 dev->dev_addr, ETH_ALEN);
3019
3020 /* virtual address for data */
3021 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3022
3023 /* physical address: used for pause frames */
3024 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3025
3026 return 0;
3027 }
3028
3029 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3030 {
3031 u32 bit;
3032
3033 bit = ether_crc(ETH_ALEN, addr) & 63;
3034 filter[bit >> 3] |= 1 << (bit & 7);
3035 }
3036
3037 static void sky2_set_multicast(struct net_device *dev)
3038 {
3039 struct sky2_port *sky2 = netdev_priv(dev);
3040 struct sky2_hw *hw = sky2->hw;
3041 unsigned port = sky2->port;
3042 struct dev_mc_list *list = dev->mc_list;
3043 u16 reg;
3044 u8 filter[8];
3045 int rx_pause;
3046 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3047
3048 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3049 memset(filter, 0, sizeof(filter));
3050
3051 reg = gma_read16(hw, port, GM_RX_CTRL);
3052 reg |= GM_RXCR_UCF_ENA;
3053
3054 if (dev->flags & IFF_PROMISC) /* promiscuous */
3055 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3056 else if (dev->flags & IFF_ALLMULTI)
3057 memset(filter, 0xff, sizeof(filter));
3058 else if (dev->mc_count == 0 && !rx_pause)
3059 reg &= ~GM_RXCR_MCF_ENA;
3060 else {
3061 int i;
3062 reg |= GM_RXCR_MCF_ENA;
3063
3064 if (rx_pause)
3065 sky2_add_filter(filter, pause_mc_addr);
3066
3067 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3068 sky2_add_filter(filter, list->dmi_addr);
3069 }
3070
3071 gma_write16(hw, port, GM_MC_ADDR_H1,
3072 (u16) filter[0] | ((u16) filter[1] << 8));
3073 gma_write16(hw, port, GM_MC_ADDR_H2,
3074 (u16) filter[2] | ((u16) filter[3] << 8));
3075 gma_write16(hw, port, GM_MC_ADDR_H3,
3076 (u16) filter[4] | ((u16) filter[5] << 8));
3077 gma_write16(hw, port, GM_MC_ADDR_H4,
3078 (u16) filter[6] | ((u16) filter[7] << 8));
3079
3080 gma_write16(hw, port, GM_RX_CTRL, reg);
3081 }
3082
3083 /* Can have one global because blinking is controlled by
3084 * ethtool and that is always under RTNL mutex
3085 */
3086 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3087 {
3088 u16 pg;
3089
3090 switch (hw->chip_id) {
3091 case CHIP_ID_YUKON_XL:
3092 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3093 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3094 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3095 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3096 PHY_M_LEDC_INIT_CTRL(7) |
3097 PHY_M_LEDC_STA1_CTRL(7) |
3098 PHY_M_LEDC_STA0_CTRL(7))
3099 : 0);
3100
3101 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3102 break;
3103
3104 default:
3105 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3106 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3107 on ? PHY_M_LED_ALL : 0);
3108 }
3109 }
3110
3111 /* blink LED's for finding board */
3112 static int sky2_phys_id(struct net_device *dev, u32 data)
3113 {
3114 struct sky2_port *sky2 = netdev_priv(dev);
3115 struct sky2_hw *hw = sky2->hw;
3116 unsigned port = sky2->port;
3117 u16 ledctrl, ledover = 0;
3118 long ms;
3119 int interrupted;
3120 int onoff = 1;
3121
3122 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3123 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3124 else
3125 ms = data * 1000;
3126
3127 /* save initial values */
3128 spin_lock_bh(&sky2->phy_lock);
3129 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3130 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3131 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3132 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3133 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3134 } else {
3135 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3136 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3137 }
3138
3139 interrupted = 0;
3140 while (!interrupted && ms > 0) {
3141 sky2_led(hw, port, onoff);
3142 onoff = !onoff;
3143
3144 spin_unlock_bh(&sky2->phy_lock);
3145 interrupted = msleep_interruptible(250);
3146 spin_lock_bh(&sky2->phy_lock);
3147
3148 ms -= 250;
3149 }
3150
3151 /* resume regularly scheduled programming */
3152 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3153 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3154 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3155 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3156 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3157 } else {
3158 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3159 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3160 }
3161 spin_unlock_bh(&sky2->phy_lock);
3162
3163 return 0;
3164 }
3165
3166 static void sky2_get_pauseparam(struct net_device *dev,
3167 struct ethtool_pauseparam *ecmd)
3168 {
3169 struct sky2_port *sky2 = netdev_priv(dev);
3170
3171 switch (sky2->flow_mode) {
3172 case FC_NONE:
3173 ecmd->tx_pause = ecmd->rx_pause = 0;
3174 break;
3175 case FC_TX:
3176 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3177 break;
3178 case FC_RX:
3179 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3180 break;
3181 case FC_BOTH:
3182 ecmd->tx_pause = ecmd->rx_pause = 1;
3183 }
3184
3185 ecmd->autoneg = sky2->autoneg;
3186 }
3187
3188 static int sky2_set_pauseparam(struct net_device *dev,
3189 struct ethtool_pauseparam *ecmd)
3190 {
3191 struct sky2_port *sky2 = netdev_priv(dev);
3192
3193 sky2->autoneg = ecmd->autoneg;
3194 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3195
3196 if (netif_running(dev))
3197 sky2_phy_reinit(sky2);
3198
3199 return 0;
3200 }
3201
3202 static int sky2_get_coalesce(struct net_device *dev,
3203 struct ethtool_coalesce *ecmd)
3204 {
3205 struct sky2_port *sky2 = netdev_priv(dev);
3206 struct sky2_hw *hw = sky2->hw;
3207
3208 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3209 ecmd->tx_coalesce_usecs = 0;
3210 else {
3211 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3212 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3213 }
3214 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3215
3216 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3217 ecmd->rx_coalesce_usecs = 0;
3218 else {
3219 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3220 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3221 }
3222 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3223
3224 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3225 ecmd->rx_coalesce_usecs_irq = 0;
3226 else {
3227 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3228 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3229 }
3230
3231 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3232
3233 return 0;
3234 }
3235
3236 /* Note: this affect both ports */
3237 static int sky2_set_coalesce(struct net_device *dev,
3238 struct ethtool_coalesce *ecmd)
3239 {
3240 struct sky2_port *sky2 = netdev_priv(dev);
3241 struct sky2_hw *hw = sky2->hw;
3242 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3243
3244 if (ecmd->tx_coalesce_usecs > tmax ||
3245 ecmd->rx_coalesce_usecs > tmax ||
3246 ecmd->rx_coalesce_usecs_irq > tmax)
3247 return -EINVAL;
3248
3249 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3250 return -EINVAL;
3251 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3252 return -EINVAL;
3253 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3254 return -EINVAL;
3255
3256 if (ecmd->tx_coalesce_usecs == 0)
3257 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3258 else {
3259 sky2_write32(hw, STAT_TX_TIMER_INI,
3260 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3261 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3262 }
3263 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3264
3265 if (ecmd->rx_coalesce_usecs == 0)
3266 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3267 else {
3268 sky2_write32(hw, STAT_LEV_TIMER_INI,
3269 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3270 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3271 }
3272 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3273
3274 if (ecmd->rx_coalesce_usecs_irq == 0)
3275 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3276 else {
3277 sky2_write32(hw, STAT_ISR_TIMER_INI,
3278 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3279 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3280 }
3281 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3282 return 0;
3283 }
3284
3285 static void sky2_get_ringparam(struct net_device *dev,
3286 struct ethtool_ringparam *ering)
3287 {
3288 struct sky2_port *sky2 = netdev_priv(dev);
3289
3290 ering->rx_max_pending = RX_MAX_PENDING;
3291 ering->rx_mini_max_pending = 0;
3292 ering->rx_jumbo_max_pending = 0;
3293 ering->tx_max_pending = TX_RING_SIZE - 1;
3294
3295 ering->rx_pending = sky2->rx_pending;
3296 ering->rx_mini_pending = 0;
3297 ering->rx_jumbo_pending = 0;
3298 ering->tx_pending = sky2->tx_pending;
3299 }
3300
3301 static int sky2_set_ringparam(struct net_device *dev,
3302 struct ethtool_ringparam *ering)
3303 {
3304 struct sky2_port *sky2 = netdev_priv(dev);
3305 int err = 0;
3306
3307 if (ering->rx_pending > RX_MAX_PENDING ||
3308 ering->rx_pending < 8 ||
3309 ering->tx_pending < MAX_SKB_TX_LE ||
3310 ering->tx_pending > TX_RING_SIZE - 1)
3311 return -EINVAL;
3312
3313 if (netif_running(dev))
3314 sky2_down(dev);
3315
3316 sky2->rx_pending = ering->rx_pending;
3317 sky2->tx_pending = ering->tx_pending;
3318
3319 if (netif_running(dev)) {
3320 err = sky2_up(dev);
3321 if (err)
3322 dev_close(dev);
3323 else
3324 sky2_set_multicast(dev);
3325 }
3326
3327 return err;
3328 }
3329
3330 static int sky2_get_regs_len(struct net_device *dev)
3331 {
3332 return 0x4000;
3333 }
3334
3335 /*
3336 * Returns copy of control register region
3337 * Note: access to the RAM address register set will cause timeouts.
3338 */
3339 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3340 void *p)
3341 {
3342 const struct sky2_port *sky2 = netdev_priv(dev);
3343 const void __iomem *io = sky2->hw->regs;
3344
3345 BUG_ON(regs->len < B3_RI_WTO_R1);
3346 regs->version = 1;
3347 memset(p, 0, regs->len);
3348
3349 memcpy_fromio(p, io, B3_RAM_ADDR);
3350
3351 memcpy_fromio(p + B3_RI_WTO_R1,
3352 io + B3_RI_WTO_R1,
3353 regs->len - B3_RI_WTO_R1);
3354 }
3355
3356 /* In order to do Jumbo packets on these chips, need to turn off the
3357 * transmit store/forward. Therefore checksum offload won't work.
3358 */
3359 static int no_tx_offload(struct net_device *dev)
3360 {
3361 const struct sky2_port *sky2 = netdev_priv(dev);
3362 const struct sky2_hw *hw = sky2->hw;
3363
3364 return dev->mtu > ETH_DATA_LEN &&
3365 (hw->chip_id == CHIP_ID_YUKON_EX
3366 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3367 }
3368
3369 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3370 {
3371 if (data && no_tx_offload(dev))
3372 return -EINVAL;
3373
3374 return ethtool_op_set_tx_csum(dev, data);
3375 }
3376
3377
3378 static int sky2_set_tso(struct net_device *dev, u32 data)
3379 {
3380 if (data && no_tx_offload(dev))
3381 return -EINVAL;
3382
3383 return ethtool_op_set_tso(dev, data);
3384 }
3385
3386 static const struct ethtool_ops sky2_ethtool_ops = {
3387 .get_settings = sky2_get_settings,
3388 .set_settings = sky2_set_settings,
3389 .get_drvinfo = sky2_get_drvinfo,
3390 .get_wol = sky2_get_wol,
3391 .set_wol = sky2_set_wol,
3392 .get_msglevel = sky2_get_msglevel,
3393 .set_msglevel = sky2_set_msglevel,
3394 .nway_reset = sky2_nway_reset,
3395 .get_regs_len = sky2_get_regs_len,
3396 .get_regs = sky2_get_regs,
3397 .get_link = ethtool_op_get_link,
3398 .get_sg = ethtool_op_get_sg,
3399 .set_sg = ethtool_op_set_sg,
3400 .get_tx_csum = ethtool_op_get_tx_csum,
3401 .set_tx_csum = sky2_set_tx_csum,
3402 .get_tso = ethtool_op_get_tso,
3403 .set_tso = sky2_set_tso,
3404 .get_rx_csum = sky2_get_rx_csum,
3405 .set_rx_csum = sky2_set_rx_csum,
3406 .get_strings = sky2_get_strings,
3407 .get_coalesce = sky2_get_coalesce,
3408 .set_coalesce = sky2_set_coalesce,
3409 .get_ringparam = sky2_get_ringparam,
3410 .set_ringparam = sky2_set_ringparam,
3411 .get_pauseparam = sky2_get_pauseparam,
3412 .set_pauseparam = sky2_set_pauseparam,
3413 .phys_id = sky2_phys_id,
3414 .get_stats_count = sky2_get_stats_count,
3415 .get_ethtool_stats = sky2_get_ethtool_stats,
3416 .get_perm_addr = ethtool_op_get_perm_addr,
3417 };
3418
3419 /* Initialize network device */
3420 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3421 unsigned port,
3422 int highmem, int wol)
3423 {
3424 struct sky2_port *sky2;
3425 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3426
3427 if (!dev) {
3428 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3429 return NULL;
3430 }
3431
3432 SET_MODULE_OWNER(dev);
3433 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3434 dev->irq = hw->pdev->irq;
3435 dev->open = sky2_up;
3436 dev->stop = sky2_down;
3437 dev->do_ioctl = sky2_ioctl;
3438 dev->hard_start_xmit = sky2_xmit_frame;
3439 dev->get_stats = sky2_get_stats;
3440 dev->set_multicast_list = sky2_set_multicast;
3441 dev->set_mac_address = sky2_set_mac_address;
3442 dev->change_mtu = sky2_change_mtu;
3443 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3444 dev->tx_timeout = sky2_tx_timeout;
3445 dev->watchdog_timeo = TX_WATCHDOG;
3446 if (port == 0)
3447 dev->poll = sky2_poll;
3448 dev->weight = NAPI_WEIGHT;
3449 #ifdef CONFIG_NET_POLL_CONTROLLER
3450 /* Network console (only works on port 0)
3451 * because netpoll makes assumptions about NAPI
3452 */
3453 if (port == 0)
3454 dev->poll_controller = sky2_netpoll;
3455 #endif
3456
3457 sky2 = netdev_priv(dev);
3458 sky2->netdev = dev;
3459 sky2->hw = hw;
3460 sky2->msg_enable = netif_msg_init(debug, default_msg);
3461
3462 /* Auto speed and flow control */
3463 sky2->autoneg = AUTONEG_ENABLE;
3464 sky2->flow_mode = FC_BOTH;
3465
3466 sky2->duplex = -1;
3467 sky2->speed = -1;
3468 sky2->advertising = sky2_supported_modes(hw);
3469 sky2->rx_csum = 1;
3470 sky2->wol = wol;
3471
3472 spin_lock_init(&sky2->phy_lock);
3473 sky2->tx_pending = TX_DEF_PENDING;
3474 sky2->rx_pending = RX_DEF_PENDING;
3475
3476 hw->dev[port] = dev;
3477
3478 sky2->port = port;
3479
3480 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3481 if (highmem)
3482 dev->features |= NETIF_F_HIGHDMA;
3483
3484 #ifdef SKY2_VLAN_TAG_USED
3485 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3486 dev->vlan_rx_register = sky2_vlan_rx_register;
3487 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3488 #endif
3489
3490 /* read the mac address */
3491 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3492 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3493
3494 /* device is off until link detection */
3495 netif_carrier_off(dev);
3496 netif_stop_queue(dev);
3497
3498 return dev;
3499 }
3500
3501 static void __devinit sky2_show_addr(struct net_device *dev)
3502 {
3503 const struct sky2_port *sky2 = netdev_priv(dev);
3504
3505 if (netif_msg_probe(sky2))
3506 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3507 dev->name,
3508 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3509 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3510 }
3511
3512 /* Handle software interrupt used during MSI test */
3513 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3514 {
3515 struct sky2_hw *hw = dev_id;
3516 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3517
3518 if (status == 0)
3519 return IRQ_NONE;
3520
3521 if (status & Y2_IS_IRQ_SW) {
3522 hw->msi = 1;
3523 wake_up(&hw->msi_wait);
3524 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3525 }
3526 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3527
3528 return IRQ_HANDLED;
3529 }
3530
3531 /* Test interrupt path by forcing a a software IRQ */
3532 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3533 {
3534 struct pci_dev *pdev = hw->pdev;
3535 int err;
3536
3537 init_waitqueue_head (&hw->msi_wait);
3538
3539 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3540
3541 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3542 if (err) {
3543 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3544 return err;
3545 }
3546
3547 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3548 sky2_read8(hw, B0_CTST);
3549
3550 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3551
3552 if (!hw->msi) {
3553 /* MSI test failed, go back to INTx mode */
3554 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3555 "switching to INTx mode.\n");
3556
3557 err = -EOPNOTSUPP;
3558 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3559 }
3560
3561 sky2_write32(hw, B0_IMSK, 0);
3562 sky2_read32(hw, B0_IMSK);
3563
3564 free_irq(pdev->irq, hw);
3565
3566 return err;
3567 }
3568
3569 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3570 {
3571 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3572 u16 value;
3573
3574 if (!pm)
3575 return 0;
3576 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3577 return 0;
3578 return value & PCI_PM_CTRL_PME_ENABLE;
3579 }
3580
3581 static int __devinit sky2_probe(struct pci_dev *pdev,
3582 const struct pci_device_id *ent)
3583 {
3584 struct net_device *dev;
3585 struct sky2_hw *hw;
3586 int err, using_dac = 0, wol_default;
3587
3588 err = pci_enable_device(pdev);
3589 if (err) {
3590 dev_err(&pdev->dev, "cannot enable PCI device\n");
3591 goto err_out;
3592 }
3593
3594 err = pci_request_regions(pdev, DRV_NAME);
3595 if (err) {
3596 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3597 goto err_out_disable;
3598 }
3599
3600 pci_set_master(pdev);
3601
3602 if (sizeof(dma_addr_t) > sizeof(u32) &&
3603 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3604 using_dac = 1;
3605 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3606 if (err < 0) {
3607 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3608 "for consistent allocations\n");
3609 goto err_out_free_regions;
3610 }
3611 } else {
3612 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3613 if (err) {
3614 dev_err(&pdev->dev, "no usable DMA configuration\n");
3615 goto err_out_free_regions;
3616 }
3617 }
3618
3619 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3620
3621 err = -ENOMEM;
3622 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3623 if (!hw) {
3624 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3625 goto err_out_free_regions;
3626 }
3627
3628 hw->pdev = pdev;
3629
3630 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3631 if (!hw->regs) {
3632 dev_err(&pdev->dev, "cannot map device registers\n");
3633 goto err_out_free_hw;
3634 }
3635
3636 #ifdef __BIG_ENDIAN
3637 /* The sk98lin vendor driver uses hardware byte swapping but
3638 * this driver uses software swapping.
3639 */
3640 {
3641 u32 reg;
3642 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3643 reg &= ~PCI_REV_DESC;
3644 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3645 }
3646 #endif
3647
3648 /* ring for status responses */
3649 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3650 &hw->st_dma);
3651 if (!hw->st_le)
3652 goto err_out_iounmap;
3653
3654 err = sky2_init(hw);
3655 if (err)
3656 goto err_out_iounmap;
3657
3658 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3659 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3660 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3661 hw->chip_id, hw->chip_rev);
3662
3663 sky2_reset(hw);
3664
3665 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3666 if (!dev) {
3667 err = -ENOMEM;
3668 goto err_out_free_pci;
3669 }
3670
3671 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3672 err = sky2_test_msi(hw);
3673 if (err == -EOPNOTSUPP)
3674 pci_disable_msi(pdev);
3675 else if (err)
3676 goto err_out_free_netdev;
3677 }
3678
3679 err = register_netdev(dev);
3680 if (err) {
3681 dev_err(&pdev->dev, "cannot register net device\n");
3682 goto err_out_free_netdev;
3683 }
3684
3685 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3686 dev->name, hw);
3687 if (err) {
3688 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3689 goto err_out_unregister;
3690 }
3691 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3692
3693 sky2_show_addr(dev);
3694
3695 if (hw->ports > 1) {
3696 struct net_device *dev1;
3697
3698 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3699 if (!dev1)
3700 dev_warn(&pdev->dev, "allocation for second device failed\n");
3701 else if ((err = register_netdev(dev1))) {
3702 dev_warn(&pdev->dev,
3703 "register of second port failed (%d)\n", err);
3704 hw->dev[1] = NULL;
3705 free_netdev(dev1);
3706 } else
3707 sky2_show_addr(dev1);
3708 }
3709
3710 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3711 INIT_WORK(&hw->restart_work, sky2_restart);
3712
3713 sky2_idle_start(hw);
3714
3715 pci_set_drvdata(pdev, hw);
3716
3717 return 0;
3718
3719 err_out_unregister:
3720 if (hw->msi)
3721 pci_disable_msi(pdev);
3722 unregister_netdev(dev);
3723 err_out_free_netdev:
3724 free_netdev(dev);
3725 err_out_free_pci:
3726 sky2_write8(hw, B0_CTST, CS_RST_SET);
3727 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3728 err_out_iounmap:
3729 iounmap(hw->regs);
3730 err_out_free_hw:
3731 kfree(hw);
3732 err_out_free_regions:
3733 pci_release_regions(pdev);
3734 err_out_disable:
3735 pci_disable_device(pdev);
3736 err_out:
3737 pci_set_drvdata(pdev, NULL);
3738 return err;
3739 }
3740
3741 static void __devexit sky2_remove(struct pci_dev *pdev)
3742 {
3743 struct sky2_hw *hw = pci_get_drvdata(pdev);
3744 struct net_device *dev0, *dev1;
3745
3746 if (!hw)
3747 return;
3748
3749 del_timer_sync(&hw->idle_timer);
3750
3751 flush_scheduled_work();
3752
3753 sky2_write32(hw, B0_IMSK, 0);
3754 synchronize_irq(hw->pdev->irq);
3755
3756 dev0 = hw->dev[0];
3757 dev1 = hw->dev[1];
3758 if (dev1)
3759 unregister_netdev(dev1);
3760 unregister_netdev(dev0);
3761
3762 sky2_power_aux(hw);
3763
3764 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3765 sky2_write8(hw, B0_CTST, CS_RST_SET);
3766 sky2_read8(hw, B0_CTST);
3767
3768 free_irq(pdev->irq, hw);
3769 if (hw->msi)
3770 pci_disable_msi(pdev);
3771 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3772 pci_release_regions(pdev);
3773 pci_disable_device(pdev);
3774
3775 if (dev1)
3776 free_netdev(dev1);
3777 free_netdev(dev0);
3778 iounmap(hw->regs);
3779 kfree(hw);
3780
3781 pci_set_drvdata(pdev, NULL);
3782 }
3783
3784 #ifdef CONFIG_PM
3785 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3786 {
3787 struct sky2_hw *hw = pci_get_drvdata(pdev);
3788 int i, wol = 0;
3789
3790 if (!hw)
3791 return 0;
3792
3793 del_timer_sync(&hw->idle_timer);
3794 netif_poll_disable(hw->dev[0]);
3795
3796 for (i = 0; i < hw->ports; i++) {
3797 struct net_device *dev = hw->dev[i];
3798 struct sky2_port *sky2 = netdev_priv(dev);
3799
3800 if (netif_running(dev))
3801 sky2_down(dev);
3802
3803 if (sky2->wol)
3804 sky2_wol_init(sky2);
3805
3806 wol |= sky2->wol;
3807 }
3808
3809 sky2_write32(hw, B0_IMSK, 0);
3810 sky2_power_aux(hw);
3811
3812 pci_save_state(pdev);
3813 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3814 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3815
3816 return 0;
3817 }
3818
3819 static int sky2_resume(struct pci_dev *pdev)
3820 {
3821 struct sky2_hw *hw = pci_get_drvdata(pdev);
3822 int i, err;
3823
3824 if (!hw)
3825 return 0;
3826
3827 err = pci_set_power_state(pdev, PCI_D0);
3828 if (err)
3829 goto out;
3830
3831 err = pci_restore_state(pdev);
3832 if (err)
3833 goto out;
3834
3835 pci_enable_wake(pdev, PCI_D0, 0);
3836
3837 /* Re-enable all clocks */
3838 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3839 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3840
3841 sky2_reset(hw);
3842
3843 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3844
3845 for (i = 0; i < hw->ports; i++) {
3846 struct net_device *dev = hw->dev[i];
3847 if (netif_running(dev)) {
3848 err = sky2_up(dev);
3849 if (err) {
3850 printk(KERN_ERR PFX "%s: could not up: %d\n",
3851 dev->name, err);
3852 dev_close(dev);
3853 goto out;
3854 }
3855 }
3856 }
3857
3858 netif_poll_enable(hw->dev[0]);
3859 sky2_idle_start(hw);
3860 return 0;
3861 out:
3862 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3863 pci_disable_device(pdev);
3864 return err;
3865 }
3866 #endif
3867
3868 static void sky2_shutdown(struct pci_dev *pdev)
3869 {
3870 struct sky2_hw *hw = pci_get_drvdata(pdev);
3871 int i, wol = 0;
3872
3873 if (!hw)
3874 return;
3875
3876 del_timer_sync(&hw->idle_timer);
3877 netif_poll_disable(hw->dev[0]);
3878
3879 for (i = 0; i < hw->ports; i++) {
3880 struct net_device *dev = hw->dev[i];
3881 struct sky2_port *sky2 = netdev_priv(dev);
3882
3883 if (sky2->wol) {
3884 wol = 1;
3885 sky2_wol_init(sky2);
3886 }
3887 }
3888
3889 if (wol)
3890 sky2_power_aux(hw);
3891
3892 pci_enable_wake(pdev, PCI_D3hot, wol);
3893 pci_enable_wake(pdev, PCI_D3cold, wol);
3894
3895 pci_disable_device(pdev);
3896 pci_set_power_state(pdev, PCI_D3hot);
3897
3898 }
3899
3900 static struct pci_driver sky2_driver = {
3901 .name = DRV_NAME,
3902 .id_table = sky2_id_table,
3903 .probe = sky2_probe,
3904 .remove = __devexit_p(sky2_remove),
3905 #ifdef CONFIG_PM
3906 .suspend = sky2_suspend,
3907 .resume = sky2_resume,
3908 #endif
3909 .shutdown = sky2_shutdown,
3910 };
3911
3912 static int __init sky2_init_module(void)
3913 {
3914 return pci_register_driver(&sky2_driver);
3915 }
3916
3917 static void __exit sky2_cleanup_module(void)
3918 {
3919 pci_unregister_driver(&sky2_driver);
3920 }
3921
3922 module_init(sky2_init_module);
3923 module_exit(sky2_cleanup_module);
3924
3925 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3926 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3927 MODULE_LICENSE("GPL");
3928 MODULE_VERSION(DRV_VERSION);
WRT350N Kernel Patches