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CRIS: Move common Kconfig variable ETRAX_RTC to arch independet Kconfig.
[wrt350n-kernel.git] / drivers / net / wireless / b43 / main.c
blobef65c41af00fc022e4841baa843571f1ae107fda
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/io.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
44
45 #include "b43.h"
46 #include "main.h"
47 #include "debugfs.h"
48 #include "phy.h"
49 #include "dma.h"
50 #include "sysfs.h"
51 #include "xmit.h"
52 #include "lo.h"
53 #include "pcmcia.h"
54
55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
56 MODULE_AUTHOR("Martin Langer");
57 MODULE_AUTHOR("Stefano Brivio");
58 MODULE_AUTHOR("Michael Buesch");
59 MODULE_LICENSE("GPL");
60
61
62 static int modparam_bad_frames_preempt;
63 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
64 MODULE_PARM_DESC(bad_frames_preempt,
65 "enable(1) / disable(0) Bad Frames Preemption");
66
67 static char modparam_fwpostfix[16];
68 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
69 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
70
71 static int modparam_hwpctl;
72 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
73 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
74
75 static int modparam_nohwcrypt;
76 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
77 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78
79 static const struct ssb_device_id b43_ssb_tbl[] = {
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
87 SSB_DEVTABLE_END
88 };
89
90 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
91
92 /* Channel and ratetables are shared for all devices.
93 * They can't be const, because ieee80211 puts some precalculated
94 * data in there. This data is the same for all devices, so we don't
95 * get concurrency issues */
96 #define RATETAB_ENT(_rateid, _flags) \
97 { \
98 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
99 .val = (_rateid), \
100 .val2 = (_rateid), \
101 .flags = (_flags), \
102 }
103 static struct ieee80211_rate __b43_ratetable[] = {
104 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
105 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
108 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
115 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
116 };
117
118 #define b43_a_ratetable (__b43_ratetable + 4)
119 #define b43_a_ratetable_size 8
120 #define b43_b_ratetable (__b43_ratetable + 0)
121 #define b43_b_ratetable_size 4
122 #define b43_g_ratetable (__b43_ratetable + 0)
123 #define b43_g_ratetable_size 12
124
125 #define CHANTAB_ENT(_chanid, _freq) \
126 { \
127 .chan = (_chanid), \
128 .freq = (_freq), \
129 .val = (_chanid), \
130 .flag = IEEE80211_CHAN_W_SCAN | \
131 IEEE80211_CHAN_W_ACTIVE_SCAN | \
132 IEEE80211_CHAN_W_IBSS, \
133 .power_level = 0xFF, \
134 .antenna_max = 0xFF, \
135 }
136 static struct ieee80211_channel b43_2ghz_chantable[] = {
137 CHANTAB_ENT(1, 2412),
138 CHANTAB_ENT(2, 2417),
139 CHANTAB_ENT(3, 2422),
140 CHANTAB_ENT(4, 2427),
141 CHANTAB_ENT(5, 2432),
142 CHANTAB_ENT(6, 2437),
143 CHANTAB_ENT(7, 2442),
144 CHANTAB_ENT(8, 2447),
145 CHANTAB_ENT(9, 2452),
146 CHANTAB_ENT(10, 2457),
147 CHANTAB_ENT(11, 2462),
148 CHANTAB_ENT(12, 2467),
149 CHANTAB_ENT(13, 2472),
150 CHANTAB_ENT(14, 2484),
151 };
152 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
153
154 #if 0
155 static struct ieee80211_channel b43_5ghz_chantable[] = {
156 CHANTAB_ENT(36, 5180),
157 CHANTAB_ENT(40, 5200),
158 CHANTAB_ENT(44, 5220),
159 CHANTAB_ENT(48, 5240),
160 CHANTAB_ENT(52, 5260),
161 CHANTAB_ENT(56, 5280),
162 CHANTAB_ENT(60, 5300),
163 CHANTAB_ENT(64, 5320),
164 CHANTAB_ENT(149, 5745),
165 CHANTAB_ENT(153, 5765),
166 CHANTAB_ENT(157, 5785),
167 CHANTAB_ENT(161, 5805),
168 CHANTAB_ENT(165, 5825),
169 };
170 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
171 #endif
172
173 static void b43_wireless_core_exit(struct b43_wldev *dev);
174 static int b43_wireless_core_init(struct b43_wldev *dev);
175 static void b43_wireless_core_stop(struct b43_wldev *dev);
176 static int b43_wireless_core_start(struct b43_wldev *dev);
177
178 static int b43_ratelimit(struct b43_wl *wl)
179 {
180 if (!wl || !wl->current_dev)
181 return 1;
182 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
183 return 1;
184 /* We are up and running.
185 * Ratelimit the messages to avoid DoS over the net. */
186 return net_ratelimit();
187 }
188
189 void b43info(struct b43_wl *wl, const char *fmt, ...)
190 {
191 va_list args;
192
193 if (!b43_ratelimit(wl))
194 return;
195 va_start(args, fmt);
196 printk(KERN_INFO "b43-%s: ",
197 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
198 vprintk(fmt, args);
199 va_end(args);
200 }
201
202 void b43err(struct b43_wl *wl, const char *fmt, ...)
203 {
204 va_list args;
205
206 if (!b43_ratelimit(wl))
207 return;
208 va_start(args, fmt);
209 printk(KERN_ERR "b43-%s ERROR: ",
210 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
211 vprintk(fmt, args);
212 va_end(args);
213 }
214
215 void b43warn(struct b43_wl *wl, const char *fmt, ...)
216 {
217 va_list args;
218
219 if (!b43_ratelimit(wl))
220 return;
221 va_start(args, fmt);
222 printk(KERN_WARNING "b43-%s warning: ",
223 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
224 vprintk(fmt, args);
225 va_end(args);
226 }
227
228 #if B43_DEBUG
229 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
230 {
231 va_list args;
232
233 va_start(args, fmt);
234 printk(KERN_DEBUG "b43-%s debug: ",
235 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
236 vprintk(fmt, args);
237 va_end(args);
238 }
239 #endif /* DEBUG */
240
241 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
242 {
243 u32 macctl;
244
245 B43_WARN_ON(offset % 4 != 0);
246
247 macctl = b43_read32(dev, B43_MMIO_MACCTL);
248 if (macctl & B43_MACCTL_BE)
249 val = swab32(val);
250
251 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
252 mmiowb();
253 b43_write32(dev, B43_MMIO_RAM_DATA, val);
254 }
255
256 static inline void b43_shm_control_word(struct b43_wldev *dev,
257 u16 routing, u16 offset)
258 {
259 u32 control;
260
261 /* "offset" is the WORD offset. */
262 control = routing;
263 control <<= 16;
264 control |= offset;
265 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
266 }
267
268 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
269 {
270 struct b43_wl *wl = dev->wl;
271 unsigned long flags;
272 u32 ret;
273
274 spin_lock_irqsave(&wl->shm_lock, flags);
275 if (routing == B43_SHM_SHARED) {
276 B43_WARN_ON(offset & 0x0001);
277 if (offset & 0x0003) {
278 /* Unaligned access */
279 b43_shm_control_word(dev, routing, offset >> 2);
280 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
281 ret <<= 16;
282 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
283 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
284
285 goto out;
286 }
287 offset >>= 2;
288 }
289 b43_shm_control_word(dev, routing, offset);
290 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
291 out:
292 spin_unlock_irqrestore(&wl->shm_lock, flags);
293
294 return ret;
295 }
296
297 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
298 {
299 struct b43_wl *wl = dev->wl;
300 unsigned long flags;
301 u16 ret;
302
303 spin_lock_irqsave(&wl->shm_lock, flags);
304 if (routing == B43_SHM_SHARED) {
305 B43_WARN_ON(offset & 0x0001);
306 if (offset & 0x0003) {
307 /* Unaligned access */
308 b43_shm_control_word(dev, routing, offset >> 2);
309 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
310
311 goto out;
312 }
313 offset >>= 2;
314 }
315 b43_shm_control_word(dev, routing, offset);
316 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
317 out:
318 spin_unlock_irqrestore(&wl->shm_lock, flags);
319
320 return ret;
321 }
322
323 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
324 {
325 struct b43_wl *wl = dev->wl;
326 unsigned long flags;
327
328 spin_lock_irqsave(&wl->shm_lock, flags);
329 if (routing == B43_SHM_SHARED) {
330 B43_WARN_ON(offset & 0x0001);
331 if (offset & 0x0003) {
332 /* Unaligned access */
333 b43_shm_control_word(dev, routing, offset >> 2);
334 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
335 (value >> 16) & 0xffff);
336 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
337 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
338 goto out;
339 }
340 offset >>= 2;
341 }
342 b43_shm_control_word(dev, routing, offset);
343 b43_write32(dev, B43_MMIO_SHM_DATA, value);
344 out:
345 spin_unlock_irqrestore(&wl->shm_lock, flags);
346 }
347
348 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
349 {
350 struct b43_wl *wl = dev->wl;
351 unsigned long flags;
352
353 spin_lock_irqsave(&wl->shm_lock, flags);
354 if (routing == B43_SHM_SHARED) {
355 B43_WARN_ON(offset & 0x0001);
356 if (offset & 0x0003) {
357 /* Unaligned access */
358 b43_shm_control_word(dev, routing, offset >> 2);
359 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
360 goto out;
361 }
362 offset >>= 2;
363 }
364 b43_shm_control_word(dev, routing, offset);
365 b43_write16(dev, B43_MMIO_SHM_DATA, value);
366 out:
367 spin_unlock_irqrestore(&wl->shm_lock, flags);
368 }
369
370 /* Read HostFlags */
371 u32 b43_hf_read(struct b43_wldev * dev)
372 {
373 u32 ret;
374
375 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
376 ret <<= 16;
377 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
378
379 return ret;
380 }
381
382 /* Write HostFlags */
383 void b43_hf_write(struct b43_wldev *dev, u32 value)
384 {
385 b43_shm_write16(dev, B43_SHM_SHARED,
386 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
387 b43_shm_write16(dev, B43_SHM_SHARED,
388 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
389 }
390
391 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
392 {
393 /* We need to be careful. As we read the TSF from multiple
394 * registers, we should take care of register overflows.
395 * In theory, the whole tsf read process should be atomic.
396 * We try to be atomic here, by restaring the read process,
397 * if any of the high registers changed (overflew).
398 */
399 if (dev->dev->id.revision >= 3) {
400 u32 low, high, high2;
401
402 do {
403 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
404 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
405 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
406 } while (unlikely(high != high2));
407
408 *tsf = high;
409 *tsf <<= 32;
410 *tsf |= low;
411 } else {
412 u64 tmp;
413 u16 v0, v1, v2, v3;
414 u16 test1, test2, test3;
415
416 do {
417 v3 = b43_read16(dev, B43_MMIO_TSF_3);
418 v2 = b43_read16(dev, B43_MMIO_TSF_2);
419 v1 = b43_read16(dev, B43_MMIO_TSF_1);
420 v0 = b43_read16(dev, B43_MMIO_TSF_0);
421
422 test3 = b43_read16(dev, B43_MMIO_TSF_3);
423 test2 = b43_read16(dev, B43_MMIO_TSF_2);
424 test1 = b43_read16(dev, B43_MMIO_TSF_1);
425 } while (v3 != test3 || v2 != test2 || v1 != test1);
426
427 *tsf = v3;
428 *tsf <<= 48;
429 tmp = v2;
430 tmp <<= 32;
431 *tsf |= tmp;
432 tmp = v1;
433 tmp <<= 16;
434 *tsf |= tmp;
435 *tsf |= v0;
436 }
437 }
438
439 static void b43_time_lock(struct b43_wldev *dev)
440 {
441 u32 macctl;
442
443 macctl = b43_read32(dev, B43_MMIO_MACCTL);
444 macctl |= B43_MACCTL_TBTTHOLD;
445 b43_write32(dev, B43_MMIO_MACCTL, macctl);
446 /* Commit the write */
447 b43_read32(dev, B43_MMIO_MACCTL);
448 }
449
450 static void b43_time_unlock(struct b43_wldev *dev)
451 {
452 u32 macctl;
453
454 macctl = b43_read32(dev, B43_MMIO_MACCTL);
455 macctl &= ~B43_MACCTL_TBTTHOLD;
456 b43_write32(dev, B43_MMIO_MACCTL, macctl);
457 /* Commit the write */
458 b43_read32(dev, B43_MMIO_MACCTL);
459 }
460
461 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
462 {
463 /* Be careful with the in-progress timer.
464 * First zero out the low register, so we have a full
465 * register-overflow duration to complete the operation.
466 */
467 if (dev->dev->id.revision >= 3) {
468 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
469 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
470
471 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
472 mmiowb();
473 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
474 mmiowb();
475 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
476 } else {
477 u16 v0 = (tsf & 0x000000000000FFFFULL);
478 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
479 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
480 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
481
482 b43_write16(dev, B43_MMIO_TSF_0, 0);
483 mmiowb();
484 b43_write16(dev, B43_MMIO_TSF_3, v3);
485 mmiowb();
486 b43_write16(dev, B43_MMIO_TSF_2, v2);
487 mmiowb();
488 b43_write16(dev, B43_MMIO_TSF_1, v1);
489 mmiowb();
490 b43_write16(dev, B43_MMIO_TSF_0, v0);
491 }
492 }
493
494 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
495 {
496 b43_time_lock(dev);
497 b43_tsf_write_locked(dev, tsf);
498 b43_time_unlock(dev);
499 }
500
501 static
502 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
503 {
504 static const u8 zero_addr[ETH_ALEN] = { 0 };
505 u16 data;
506
507 if (!mac)
508 mac = zero_addr;
509
510 offset |= 0x0020;
511 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
512
513 data = mac[0];
514 data |= mac[1] << 8;
515 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
516 data = mac[2];
517 data |= mac[3] << 8;
518 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
519 data = mac[4];
520 data |= mac[5] << 8;
521 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
522 }
523
524 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
525 {
526 const u8 *mac;
527 const u8 *bssid;
528 u8 mac_bssid[ETH_ALEN * 2];
529 int i;
530 u32 tmp;
531
532 bssid = dev->wl->bssid;
533 mac = dev->wl->mac_addr;
534
535 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
536
537 memcpy(mac_bssid, mac, ETH_ALEN);
538 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
539
540 /* Write our MAC address and BSSID to template ram */
541 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
542 tmp = (u32) (mac_bssid[i + 0]);
543 tmp |= (u32) (mac_bssid[i + 1]) << 8;
544 tmp |= (u32) (mac_bssid[i + 2]) << 16;
545 tmp |= (u32) (mac_bssid[i + 3]) << 24;
546 b43_ram_write(dev, 0x20 + i, tmp);
547 }
548 }
549
550 static void b43_upload_card_macaddress(struct b43_wldev *dev)
551 {
552 b43_write_mac_bssid_templates(dev);
553 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
554 }
555
556 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
557 {
558 /* slot_time is in usec. */
559 if (dev->phy.type != B43_PHYTYPE_G)
560 return;
561 b43_write16(dev, 0x684, 510 + slot_time);
562 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
563 }
564
565 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
566 {
567 b43_set_slot_time(dev, 9);
568 dev->short_slot = 1;
569 }
570
571 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
572 {
573 b43_set_slot_time(dev, 20);
574 dev->short_slot = 0;
575 }
576
577 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
578 * Returns the _previously_ enabled IRQ mask.
579 */
580 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
581 {
582 u32 old_mask;
583
584 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
585 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
586
587 return old_mask;
588 }
589
590 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
591 * Returns the _previously_ enabled IRQ mask.
592 */
593 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
594 {
595 u32 old_mask;
596
597 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
598 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
599
600 return old_mask;
601 }
602
603 /* Synchronize IRQ top- and bottom-half.
604 * IRQs must be masked before calling this.
605 * This must not be called with the irq_lock held.
606 */
607 static void b43_synchronize_irq(struct b43_wldev *dev)
608 {
609 synchronize_irq(dev->dev->irq);
610 tasklet_kill(&dev->isr_tasklet);
611 }
612
613 /* DummyTransmission function, as documented on
614 * http://bcm-specs.sipsolutions.net/DummyTransmission
615 */
616 void b43_dummy_transmission(struct b43_wldev *dev)
617 {
618 struct b43_phy *phy = &dev->phy;
619 unsigned int i, max_loop;
620 u16 value;
621 u32 buffer[5] = {
622 0x00000000,
623 0x00D40000,
624 0x00000000,
625 0x01000000,
626 0x00000000,
627 };
628
629 switch (phy->type) {
630 case B43_PHYTYPE_A:
631 max_loop = 0x1E;
632 buffer[0] = 0x000201CC;
633 break;
634 case B43_PHYTYPE_B:
635 case B43_PHYTYPE_G:
636 max_loop = 0xFA;
637 buffer[0] = 0x000B846E;
638 break;
639 default:
640 B43_WARN_ON(1);
641 return;
642 }
643
644 for (i = 0; i < 5; i++)
645 b43_ram_write(dev, i * 4, buffer[i]);
646
647 /* Commit writes */
648 b43_read32(dev, B43_MMIO_MACCTL);
649
650 b43_write16(dev, 0x0568, 0x0000);
651 b43_write16(dev, 0x07C0, 0x0000);
652 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
653 b43_write16(dev, 0x050C, value);
654 b43_write16(dev, 0x0508, 0x0000);
655 b43_write16(dev, 0x050A, 0x0000);
656 b43_write16(dev, 0x054C, 0x0000);
657 b43_write16(dev, 0x056A, 0x0014);
658 b43_write16(dev, 0x0568, 0x0826);
659 b43_write16(dev, 0x0500, 0x0000);
660 b43_write16(dev, 0x0502, 0x0030);
661
662 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
663 b43_radio_write16(dev, 0x0051, 0x0017);
664 for (i = 0x00; i < max_loop; i++) {
665 value = b43_read16(dev, 0x050E);
666 if (value & 0x0080)
667 break;
668 udelay(10);
669 }
670 for (i = 0x00; i < 0x0A; i++) {
671 value = b43_read16(dev, 0x050E);
672 if (value & 0x0400)
673 break;
674 udelay(10);
675 }
676 for (i = 0x00; i < 0x0A; i++) {
677 value = b43_read16(dev, 0x0690);
678 if (!(value & 0x0100))
679 break;
680 udelay(10);
681 }
682 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
683 b43_radio_write16(dev, 0x0051, 0x0037);
684 }
685
686 static void key_write(struct b43_wldev *dev,
687 u8 index, u8 algorithm, const u8 * key)
688 {
689 unsigned int i;
690 u32 offset;
691 u16 value;
692 u16 kidx;
693
694 /* Key index/algo block */
695 kidx = b43_kidx_to_fw(dev, index);
696 value = ((kidx << 4) | algorithm);
697 b43_shm_write16(dev, B43_SHM_SHARED,
698 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
699
700 /* Write the key to the Key Table Pointer offset */
701 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
702 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
703 value = key[i];
704 value |= (u16) (key[i + 1]) << 8;
705 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
706 }
707 }
708
709 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
710 {
711 u32 addrtmp[2] = { 0, 0, };
712 u8 per_sta_keys_start = 8;
713
714 if (b43_new_kidx_api(dev))
715 per_sta_keys_start = 4;
716
717 B43_WARN_ON(index < per_sta_keys_start);
718 /* We have two default TX keys and possibly two default RX keys.
719 * Physical mac 0 is mapped to physical key 4 or 8, depending
720 * on the firmware version.
721 * So we must adjust the index here.
722 */
723 index -= per_sta_keys_start;
724
725 if (addr) {
726 addrtmp[0] = addr[0];
727 addrtmp[0] |= ((u32) (addr[1]) << 8);
728 addrtmp[0] |= ((u32) (addr[2]) << 16);
729 addrtmp[0] |= ((u32) (addr[3]) << 24);
730 addrtmp[1] = addr[4];
731 addrtmp[1] |= ((u32) (addr[5]) << 8);
732 }
733
734 if (dev->dev->id.revision >= 5) {
735 /* Receive match transmitter address mechanism */
736 b43_shm_write32(dev, B43_SHM_RCMTA,
737 (index * 2) + 0, addrtmp[0]);
738 b43_shm_write16(dev, B43_SHM_RCMTA,
739 (index * 2) + 1, addrtmp[1]);
740 } else {
741 /* RXE (Receive Engine) and
742 * PSM (Programmable State Machine) mechanism
743 */
744 if (index < 8) {
745 /* TODO write to RCM 16, 19, 22 and 25 */
746 } else {
747 b43_shm_write32(dev, B43_SHM_SHARED,
748 B43_SHM_SH_PSM + (index * 6) + 0,
749 addrtmp[0]);
750 b43_shm_write16(dev, B43_SHM_SHARED,
751 B43_SHM_SH_PSM + (index * 6) + 4,
752 addrtmp[1]);
753 }
754 }
755 }
756
757 static void do_key_write(struct b43_wldev *dev,
758 u8 index, u8 algorithm,
759 const u8 * key, size_t key_len, const u8 * mac_addr)
760 {
761 u8 buf[B43_SEC_KEYSIZE] = { 0, };
762 u8 per_sta_keys_start = 8;
763
764 if (b43_new_kidx_api(dev))
765 per_sta_keys_start = 4;
766
767 B43_WARN_ON(index >= dev->max_nr_keys);
768 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
769
770 if (index >= per_sta_keys_start)
771 keymac_write(dev, index, NULL); /* First zero out mac. */
772 if (key)
773 memcpy(buf, key, key_len);
774 key_write(dev, index, algorithm, buf);
775 if (index >= per_sta_keys_start)
776 keymac_write(dev, index, mac_addr);
777
778 dev->key[index].algorithm = algorithm;
779 }
780
781 static int b43_key_write(struct b43_wldev *dev,
782 int index, u8 algorithm,
783 const u8 * key, size_t key_len,
784 const u8 * mac_addr,
785 struct ieee80211_key_conf *keyconf)
786 {
787 int i;
788 int sta_keys_start;
789
790 if (key_len > B43_SEC_KEYSIZE)
791 return -EINVAL;
792 for (i = 0; i < dev->max_nr_keys; i++) {
793 /* Check that we don't already have this key. */
794 B43_WARN_ON(dev->key[i].keyconf == keyconf);
795 }
796 if (index < 0) {
797 /* Either pairwise key or address is 00:00:00:00:00:00
798 * for transmit-only keys. Search the index. */
799 if (b43_new_kidx_api(dev))
800 sta_keys_start = 4;
801 else
802 sta_keys_start = 8;
803 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
804 if (!dev->key[i].keyconf) {
805 /* found empty */
806 index = i;
807 break;
808 }
809 }
810 if (index < 0) {
811 b43err(dev->wl, "Out of hardware key memory\n");
812 return -ENOSPC;
813 }
814 } else
815 B43_WARN_ON(index > 3);
816
817 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
818 if ((index <= 3) && !b43_new_kidx_api(dev)) {
819 /* Default RX key */
820 B43_WARN_ON(mac_addr);
821 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
822 }
823 keyconf->hw_key_idx = index;
824 dev->key[index].keyconf = keyconf;
825
826 return 0;
827 }
828
829 static int b43_key_clear(struct b43_wldev *dev, int index)
830 {
831 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
832 return -EINVAL;
833 do_key_write(dev, index, B43_SEC_ALGO_NONE,
834 NULL, B43_SEC_KEYSIZE, NULL);
835 if ((index <= 3) && !b43_new_kidx_api(dev)) {
836 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
837 NULL, B43_SEC_KEYSIZE, NULL);
838 }
839 dev->key[index].keyconf = NULL;
840
841 return 0;
842 }
843
844 static void b43_clear_keys(struct b43_wldev *dev)
845 {
846 int i;
847
848 for (i = 0; i < dev->max_nr_keys; i++)
849 b43_key_clear(dev, i);
850 }
851
852 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
853 {
854 u32 macctl;
855 u16 ucstat;
856 bool hwps;
857 bool awake;
858 int i;
859
860 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
861 (ps_flags & B43_PS_DISABLED));
862 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
863
864 if (ps_flags & B43_PS_ENABLED) {
865 hwps = 1;
866 } else if (ps_flags & B43_PS_DISABLED) {
867 hwps = 0;
868 } else {
869 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
870 // and thus is not an AP and we are associated, set bit 25
871 }
872 if (ps_flags & B43_PS_AWAKE) {
873 awake = 1;
874 } else if (ps_flags & B43_PS_ASLEEP) {
875 awake = 0;
876 } else {
877 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
878 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
879 // successful, set bit26
880 }
881
882 /* FIXME: For now we force awake-on and hwps-off */
883 hwps = 0;
884 awake = 1;
885
886 macctl = b43_read32(dev, B43_MMIO_MACCTL);
887 if (hwps)
888 macctl |= B43_MACCTL_HWPS;
889 else
890 macctl &= ~B43_MACCTL_HWPS;
891 if (awake)
892 macctl |= B43_MACCTL_AWAKE;
893 else
894 macctl &= ~B43_MACCTL_AWAKE;
895 b43_write32(dev, B43_MMIO_MACCTL, macctl);
896 /* Commit write */
897 b43_read32(dev, B43_MMIO_MACCTL);
898 if (awake && dev->dev->id.revision >= 5) {
899 /* Wait for the microcode to wake up. */
900 for (i = 0; i < 100; i++) {
901 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
902 B43_SHM_SH_UCODESTAT);
903 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
904 break;
905 udelay(10);
906 }
907 }
908 }
909
910 /* Turn the Analog ON/OFF */
911 static void b43_switch_analog(struct b43_wldev *dev, int on)
912 {
913 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
914 }
915
916 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
917 {
918 u32 tmslow;
919 u32 macctl;
920
921 flags |= B43_TMSLOW_PHYCLKEN;
922 flags |= B43_TMSLOW_PHYRESET;
923 ssb_device_enable(dev->dev, flags);
924 msleep(2); /* Wait for the PLL to turn on. */
925
926 /* Now take the PHY out of Reset again */
927 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
928 tmslow |= SSB_TMSLOW_FGC;
929 tmslow &= ~B43_TMSLOW_PHYRESET;
930 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
931 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
932 msleep(1);
933 tmslow &= ~SSB_TMSLOW_FGC;
934 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
935 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
936 msleep(1);
937
938 /* Turn Analog ON */
939 b43_switch_analog(dev, 1);
940
941 macctl = b43_read32(dev, B43_MMIO_MACCTL);
942 macctl &= ~B43_MACCTL_GMODE;
943 if (flags & B43_TMSLOW_GMODE)
944 macctl |= B43_MACCTL_GMODE;
945 macctl |= B43_MACCTL_IHR_ENABLED;
946 b43_write32(dev, B43_MMIO_MACCTL, macctl);
947 }
948
949 static void handle_irq_transmit_status(struct b43_wldev *dev)
950 {
951 u32 v0, v1;
952 u16 tmp;
953 struct b43_txstatus stat;
954
955 while (1) {
956 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
957 if (!(v0 & 0x00000001))
958 break;
959 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
960
961 stat.cookie = (v0 >> 16);
962 stat.seq = (v1 & 0x0000FFFF);
963 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
964 tmp = (v0 & 0x0000FFFF);
965 stat.frame_count = ((tmp & 0xF000) >> 12);
966 stat.rts_count = ((tmp & 0x0F00) >> 8);
967 stat.supp_reason = ((tmp & 0x001C) >> 2);
968 stat.pm_indicated = !!(tmp & 0x0080);
969 stat.intermediate = !!(tmp & 0x0040);
970 stat.for_ampdu = !!(tmp & 0x0020);
971 stat.acked = !!(tmp & 0x0002);
972
973 b43_handle_txstatus(dev, &stat);
974 }
975 }
976
977 static void drain_txstatus_queue(struct b43_wldev *dev)
978 {
979 u32 dummy;
980
981 if (dev->dev->id.revision < 5)
982 return;
983 /* Read all entries from the microcode TXstatus FIFO
984 * and throw them away.
985 */
986 while (1) {
987 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
988 if (!(dummy & 0x00000001))
989 break;
990 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
991 }
992 }
993
994 static u32 b43_jssi_read(struct b43_wldev *dev)
995 {
996 u32 val = 0;
997
998 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
999 val <<= 16;
1000 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1001
1002 return val;
1003 }
1004
1005 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1006 {
1007 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1008 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1009 }
1010
1011 static void b43_generate_noise_sample(struct b43_wldev *dev)
1012 {
1013 b43_jssi_write(dev, 0x7F7F7F7F);
1014 b43_write32(dev, B43_MMIO_MACCMD,
1015 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1016 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1017 }
1018
1019 static void b43_calculate_link_quality(struct b43_wldev *dev)
1020 {
1021 /* Top half of Link Quality calculation. */
1022
1023 if (dev->noisecalc.calculation_running)
1024 return;
1025 dev->noisecalc.channel_at_start = dev->phy.channel;
1026 dev->noisecalc.calculation_running = 1;
1027 dev->noisecalc.nr_samples = 0;
1028
1029 b43_generate_noise_sample(dev);
1030 }
1031
1032 static void handle_irq_noise(struct b43_wldev *dev)
1033 {
1034 struct b43_phy *phy = &dev->phy;
1035 u16 tmp;
1036 u8 noise[4];
1037 u8 i, j;
1038 s32 average;
1039
1040 /* Bottom half of Link Quality calculation. */
1041
1042 B43_WARN_ON(!dev->noisecalc.calculation_running);
1043 if (dev->noisecalc.channel_at_start != phy->channel)
1044 goto drop_calculation;
1045 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1046 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1047 noise[2] == 0x7F || noise[3] == 0x7F)
1048 goto generate_new;
1049
1050 /* Get the noise samples. */
1051 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1052 i = dev->noisecalc.nr_samples;
1053 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1054 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1055 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1056 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1057 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1058 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1059 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1060 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1061 dev->noisecalc.nr_samples++;
1062 if (dev->noisecalc.nr_samples == 8) {
1063 /* Calculate the Link Quality by the noise samples. */
1064 average = 0;
1065 for (i = 0; i < 8; i++) {
1066 for (j = 0; j < 4; j++)
1067 average += dev->noisecalc.samples[i][j];
1068 }
1069 average /= (8 * 4);
1070 average *= 125;
1071 average += 64;
1072 average /= 128;
1073 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1074 tmp = (tmp / 128) & 0x1F;
1075 if (tmp >= 8)
1076 average += 2;
1077 else
1078 average -= 25;
1079 if (tmp == 8)
1080 average -= 72;
1081 else
1082 average -= 48;
1083
1084 dev->stats.link_noise = average;
1085 drop_calculation:
1086 dev->noisecalc.calculation_running = 0;
1087 return;
1088 }
1089 generate_new:
1090 b43_generate_noise_sample(dev);
1091 }
1092
1093 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1094 {
1095 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1096 ///TODO: PS TBTT
1097 } else {
1098 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1099 b43_power_saving_ctl_bits(dev, 0);
1100 }
1101 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1102 dev->dfq_valid = 1;
1103 }
1104
1105 static void handle_irq_atim_end(struct b43_wldev *dev)
1106 {
1107 if (dev->dfq_valid) {
1108 b43_write32(dev, B43_MMIO_MACCMD,
1109 b43_read32(dev, B43_MMIO_MACCMD)
1110 | B43_MACCMD_DFQ_VALID);
1111 dev->dfq_valid = 0;
1112 }
1113 }
1114
1115 static void handle_irq_pmq(struct b43_wldev *dev)
1116 {
1117 u32 tmp;
1118
1119 //TODO: AP mode.
1120
1121 while (1) {
1122 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1123 if (!(tmp & 0x00000008))
1124 break;
1125 }
1126 /* 16bit write is odd, but correct. */
1127 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1128 }
1129
1130 static void b43_write_template_common(struct b43_wldev *dev,
1131 const u8 * data, u16 size,
1132 u16 ram_offset,
1133 u16 shm_size_offset, u8 rate)
1134 {
1135 u32 i, tmp;
1136 struct b43_plcp_hdr4 plcp;
1137
1138 plcp.data = 0;
1139 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1140 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1141 ram_offset += sizeof(u32);
1142 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1143 * So leave the first two bytes of the next write blank.
1144 */
1145 tmp = (u32) (data[0]) << 16;
1146 tmp |= (u32) (data[1]) << 24;
1147 b43_ram_write(dev, ram_offset, tmp);
1148 ram_offset += sizeof(u32);
1149 for (i = 2; i < size; i += sizeof(u32)) {
1150 tmp = (u32) (data[i + 0]);
1151 if (i + 1 < size)
1152 tmp |= (u32) (data[i + 1]) << 8;
1153 if (i + 2 < size)
1154 tmp |= (u32) (data[i + 2]) << 16;
1155 if (i + 3 < size)
1156 tmp |= (u32) (data[i + 3]) << 24;
1157 b43_ram_write(dev, ram_offset + i - 2, tmp);
1158 }
1159 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1160 size + sizeof(struct b43_plcp_hdr6));
1161 }
1162
1163 static void b43_write_beacon_template(struct b43_wldev *dev,
1164 u16 ram_offset,
1165 u16 shm_size_offset, u8 rate)
1166 {
1167 unsigned int i, len, variable_len;
1168 const struct ieee80211_mgmt *bcn;
1169 const u8 *ie;
1170 bool tim_found = 0;
1171
1172 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1173 len = min((size_t) dev->wl->current_beacon->len,
1174 0x200 - sizeof(struct b43_plcp_hdr6));
1175
1176 b43_write_template_common(dev, (const u8 *)bcn,
1177 len, ram_offset, shm_size_offset, rate);
1178
1179 /* Find the position of the TIM and the DTIM_period value
1180 * and write them to SHM. */
1181 ie = bcn->u.beacon.variable;
1182 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1183 for (i = 0; i < variable_len - 2; ) {
1184 uint8_t ie_id, ie_len;
1185
1186 ie_id = ie[i];
1187 ie_len = ie[i + 1];
1188 if (ie_id == 5) {
1189 u16 tim_position;
1190 u16 dtim_period;
1191 /* This is the TIM Information Element */
1192
1193 /* Check whether the ie_len is in the beacon data range. */
1194 if (variable_len < ie_len + 2 + i)
1195 break;
1196 /* A valid TIM is at least 4 bytes long. */
1197 if (ie_len < 4)
1198 break;
1199 tim_found = 1;
1200
1201 tim_position = sizeof(struct b43_plcp_hdr6);
1202 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1203 tim_position += i;
1204
1205 dtim_period = ie[i + 3];
1206
1207 b43_shm_write16(dev, B43_SHM_SHARED,
1208 B43_SHM_SH_TIMBPOS, tim_position);
1209 b43_shm_write16(dev, B43_SHM_SHARED,
1210 B43_SHM_SH_DTIMPER, dtim_period);
1211 break;
1212 }
1213 i += ie_len + 2;
1214 }
1215 if (!tim_found) {
1216 b43warn(dev->wl, "Did not find a valid TIM IE in "
1217 "the beacon template packet. AP or IBSS operation "
1218 "may be broken.\n");
1219 }
1220 }
1221
1222 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1223 u16 shm_offset, u16 size, u8 rate)
1224 {
1225 struct b43_plcp_hdr4 plcp;
1226 u32 tmp;
1227 __le16 dur;
1228
1229 plcp.data = 0;
1230 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1231 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1232 dev->wl->vif, size,
1233 B43_RATE_TO_BASE100KBPS(rate));
1234 /* Write PLCP in two parts and timing for packet transfer */
1235 tmp = le32_to_cpu(plcp.data);
1236 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1237 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1238 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1239 }
1240
1241 /* Instead of using custom probe response template, this function
1242 * just patches custom beacon template by:
1243 * 1) Changing packet type
1244 * 2) Patching duration field
1245 * 3) Stripping TIM
1246 */
1247 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1248 u16 *dest_size, u8 rate)
1249 {
1250 const u8 *src_data;
1251 u8 *dest_data;
1252 u16 src_size, elem_size, src_pos, dest_pos;
1253 __le16 dur;
1254 struct ieee80211_hdr *hdr;
1255 size_t ie_start;
1256
1257 src_size = dev->wl->current_beacon->len;
1258 src_data = (const u8 *)dev->wl->current_beacon->data;
1259
1260 /* Get the start offset of the variable IEs in the packet. */
1261 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1262 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1263
1264 if (B43_WARN_ON(src_size < ie_start))
1265 return NULL;
1266
1267 dest_data = kmalloc(src_size, GFP_ATOMIC);
1268 if (unlikely(!dest_data))
1269 return NULL;
1270
1271 /* Copy the static data and all Information Elements, except the TIM. */
1272 memcpy(dest_data, src_data, ie_start);
1273 src_pos = ie_start;
1274 dest_pos = ie_start;
1275 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1276 elem_size = src_data[src_pos + 1] + 2;
1277 if (src_data[src_pos] == 5) {
1278 /* This is the TIM. */
1279 continue;
1280 }
1281 memcpy(dest_data + dest_pos, src_data + src_pos,
1282 elem_size);
1283 dest_pos += elem_size;
1284 }
1285 *dest_size = dest_pos;
1286 hdr = (struct ieee80211_hdr *)dest_data;
1287
1288 /* Set the frame control. */
1289 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1290 IEEE80211_STYPE_PROBE_RESP);
1291 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1292 dev->wl->vif, *dest_size,
1293 B43_RATE_TO_BASE100KBPS(rate));
1294 hdr->duration_id = dur;
1295
1296 return dest_data;
1297 }
1298
1299 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1300 u16 ram_offset,
1301 u16 shm_size_offset, u8 rate)
1302 {
1303 const u8 *probe_resp_data;
1304 u16 size;
1305
1306 size = dev->wl->current_beacon->len;
1307 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1308 if (unlikely(!probe_resp_data))
1309 return;
1310
1311 /* Looks like PLCP headers plus packet timings are stored for
1312 * all possible basic rates
1313 */
1314 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1315 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1316 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1317 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1318
1319 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1320 b43_write_template_common(dev, probe_resp_data,
1321 size, ram_offset, shm_size_offset, rate);
1322 kfree(probe_resp_data);
1323 }
1324
1325 /* Asynchronously update the packet templates in template RAM.
1326 * Locking: Requires wl->irq_lock to be locked. */
1327 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1328 {
1329 /* This is the top half of the ansynchronous beacon update.
1330 * The bottom half is the beacon IRQ.
1331 * Beacon update must be asynchronous to avoid sending an
1332 * invalid beacon. This can happen for example, if the firmware
1333 * transmits a beacon while we are updating it. */
1334
1335 if (wl->current_beacon)
1336 dev_kfree_skb_any(wl->current_beacon);
1337 wl->current_beacon = beacon;
1338 wl->beacon0_uploaded = 0;
1339 wl->beacon1_uploaded = 0;
1340 }
1341
1342 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1343 {
1344 u32 tmp;
1345 u16 i, len;
1346
1347 len = min((u16) ssid_len, (u16) 0x100);
1348 for (i = 0; i < len; i += sizeof(u32)) {
1349 tmp = (u32) (ssid[i + 0]);
1350 if (i + 1 < len)
1351 tmp |= (u32) (ssid[i + 1]) << 8;
1352 if (i + 2 < len)
1353 tmp |= (u32) (ssid[i + 2]) << 16;
1354 if (i + 3 < len)
1355 tmp |= (u32) (ssid[i + 3]) << 24;
1356 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1357 }
1358 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1359 }
1360
1361 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1362 {
1363 b43_time_lock(dev);
1364 if (dev->dev->id.revision >= 3) {
1365 b43_write32(dev, 0x188, (beacon_int << 16));
1366 } else {
1367 b43_write16(dev, 0x606, (beacon_int >> 6));
1368 b43_write16(dev, 0x610, beacon_int);
1369 }
1370 b43_time_unlock(dev);
1371 }
1372
1373 static void handle_irq_beacon(struct b43_wldev *dev)
1374 {
1375 struct b43_wl *wl = dev->wl;
1376 u32 cmd;
1377
1378 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1379 return;
1380
1381 /* This is the bottom half of the asynchronous beacon update. */
1382
1383 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1384 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1385 if (!wl->beacon0_uploaded) {
1386 b43_write_beacon_template(dev, 0x68, 0x18,
1387 B43_CCK_RATE_1MB);
1388 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1389 B43_CCK_RATE_11MB);
1390 wl->beacon0_uploaded = 1;
1391 }
1392 cmd |= B43_MACCMD_BEACON0_VALID;
1393 }
1394 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1395 if (!wl->beacon1_uploaded) {
1396 b43_write_beacon_template(dev, 0x468, 0x1A,
1397 B43_CCK_RATE_1MB);
1398 wl->beacon1_uploaded = 1;
1399 }
1400 cmd |= B43_MACCMD_BEACON1_VALID;
1401 }
1402 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1403 }
1404
1405 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1406 {
1407 //TODO
1408 }
1409
1410 /* Interrupt handler bottom-half */
1411 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1412 {
1413 u32 reason;
1414 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1415 u32 merged_dma_reason = 0;
1416 int i;
1417 unsigned long flags;
1418
1419 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1420
1421 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1422
1423 reason = dev->irq_reason;
1424 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1425 dma_reason[i] = dev->dma_reason[i];
1426 merged_dma_reason |= dma_reason[i];
1427 }
1428
1429 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1430 b43err(dev->wl, "MAC transmission error\n");
1431
1432 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1433 b43err(dev->wl, "PHY transmission error\n");
1434 rmb();
1435 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1436 atomic_set(&dev->phy.txerr_cnt,
1437 B43_PHY_TX_BADNESS_LIMIT);
1438 b43err(dev->wl, "Too many PHY TX errors, "
1439 "restarting the controller\n");
1440 b43_controller_restart(dev, "PHY TX errors");
1441 }
1442 }
1443
1444 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1445 B43_DMAIRQ_NONFATALMASK))) {
1446 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1447 b43err(dev->wl, "Fatal DMA error: "
1448 "0x%08X, 0x%08X, 0x%08X, "
1449 "0x%08X, 0x%08X, 0x%08X\n",
1450 dma_reason[0], dma_reason[1],
1451 dma_reason[2], dma_reason[3],
1452 dma_reason[4], dma_reason[5]);
1453 b43_controller_restart(dev, "DMA error");
1454 mmiowb();
1455 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1456 return;
1457 }
1458 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1459 b43err(dev->wl, "DMA error: "
1460 "0x%08X, 0x%08X, 0x%08X, "
1461 "0x%08X, 0x%08X, 0x%08X\n",
1462 dma_reason[0], dma_reason[1],
1463 dma_reason[2], dma_reason[3],
1464 dma_reason[4], dma_reason[5]);
1465 }
1466 }
1467
1468 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1469 handle_irq_ucode_debug(dev);
1470 if (reason & B43_IRQ_TBTT_INDI)
1471 handle_irq_tbtt_indication(dev);
1472 if (reason & B43_IRQ_ATIM_END)
1473 handle_irq_atim_end(dev);
1474 if (reason & B43_IRQ_BEACON)
1475 handle_irq_beacon(dev);
1476 if (reason & B43_IRQ_PMQ)
1477 handle_irq_pmq(dev);
1478 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1479 ;/* TODO */
1480 if (reason & B43_IRQ_NOISESAMPLE_OK)
1481 handle_irq_noise(dev);
1482
1483 /* Check the DMA reason registers for received data. */
1484 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1485 b43_dma_rx(dev->dma.rx_ring0);
1486 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1487 b43_dma_rx(dev->dma.rx_ring3);
1488 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1489 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1490 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1491 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1492
1493 if (reason & B43_IRQ_TX_OK)
1494 handle_irq_transmit_status(dev);
1495
1496 b43_interrupt_enable(dev, dev->irq_savedstate);
1497 mmiowb();
1498 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1499 }
1500
1501 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1502 {
1503 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1504
1505 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1506 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1507 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1508 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1509 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1510 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1511 }
1512
1513 /* Interrupt handler top-half */
1514 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1515 {
1516 irqreturn_t ret = IRQ_NONE;
1517 struct b43_wldev *dev = dev_id;
1518 u32 reason;
1519
1520 if (!dev)
1521 return IRQ_NONE;
1522
1523 spin_lock(&dev->wl->irq_lock);
1524
1525 if (b43_status(dev) < B43_STAT_STARTED)
1526 goto out;
1527 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1528 if (reason == 0xffffffff) /* shared IRQ */
1529 goto out;
1530 ret = IRQ_HANDLED;
1531 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1532 if (!reason)
1533 goto out;
1534
1535 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1536 & 0x0001DC00;
1537 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1538 & 0x0000DC00;
1539 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1540 & 0x0000DC00;
1541 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1542 & 0x0001DC00;
1543 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1544 & 0x0000DC00;
1545 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1546 & 0x0000DC00;
1547
1548 b43_interrupt_ack(dev, reason);
1549 /* disable all IRQs. They are enabled again in the bottom half. */
1550 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1551 /* save the reason code and call our bottom half. */
1552 dev->irq_reason = reason;
1553 tasklet_schedule(&dev->isr_tasklet);
1554 out:
1555 mmiowb();
1556 spin_unlock(&dev->wl->irq_lock);
1557
1558 return ret;
1559 }
1560
1561 static void do_release_fw(struct b43_firmware_file *fw)
1562 {
1563 release_firmware(fw->data);
1564 fw->data = NULL;
1565 fw->filename = NULL;
1566 }
1567
1568 static void b43_release_firmware(struct b43_wldev *dev)
1569 {
1570 do_release_fw(&dev->fw.ucode);
1571 do_release_fw(&dev->fw.pcm);
1572 do_release_fw(&dev->fw.initvals);
1573 do_release_fw(&dev->fw.initvals_band);
1574 }
1575
1576 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1577 {
1578 const char *text;
1579
1580 text = "You must go to "
1581 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1582 "and download the latest firmware (version 4).\n";
1583 if (error)
1584 b43err(wl, text);
1585 else
1586 b43warn(wl, text);
1587 }
1588
1589 static int do_request_fw(struct b43_wldev *dev,
1590 const char *name,
1591 struct b43_firmware_file *fw)
1592 {
1593 char path[sizeof(modparam_fwpostfix) + 32];
1594 const struct firmware *blob;
1595 struct b43_fw_header *hdr;
1596 u32 size;
1597 int err;
1598
1599 if (!name) {
1600 /* Don't fetch anything. Free possibly cached firmware. */
1601 do_release_fw(fw);
1602 return 0;
1603 }
1604 if (fw->filename) {
1605 if (strcmp(fw->filename, name) == 0)
1606 return 0; /* Already have this fw. */
1607 /* Free the cached firmware first. */
1608 do_release_fw(fw);
1609 }
1610
1611 snprintf(path, ARRAY_SIZE(path),
1612 "b43%s/%s.fw",
1613 modparam_fwpostfix, name);
1614 err = request_firmware(&blob, path, dev->dev->dev);
1615 if (err) {
1616 b43err(dev->wl, "Firmware file \"%s\" not found "
1617 "or load failed.\n", path);
1618 return err;
1619 }
1620 if (blob->size < sizeof(struct b43_fw_header))
1621 goto err_format;
1622 hdr = (struct b43_fw_header *)(blob->data);
1623 switch (hdr->type) {
1624 case B43_FW_TYPE_UCODE:
1625 case B43_FW_TYPE_PCM:
1626 size = be32_to_cpu(hdr->size);
1627 if (size != blob->size - sizeof(struct b43_fw_header))
1628 goto err_format;
1629 /* fallthrough */
1630 case B43_FW_TYPE_IV:
1631 if (hdr->ver != 1)
1632 goto err_format;
1633 break;
1634 default:
1635 goto err_format;
1636 }
1637
1638 fw->data = blob;
1639 fw->filename = name;
1640
1641 return 0;
1642
1643 err_format:
1644 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1645 release_firmware(blob);
1646
1647 return -EPROTO;
1648 }
1649
1650 static int b43_request_firmware(struct b43_wldev *dev)
1651 {
1652 struct b43_firmware *fw = &dev->fw;
1653 const u8 rev = dev->dev->id.revision;
1654 const char *filename;
1655 u32 tmshigh;
1656 int err;
1657
1658 /* Get microcode */
1659 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1660 if ((rev >= 5) && (rev <= 10))
1661 filename = "ucode5";
1662 else if ((rev >= 11) && (rev <= 12))
1663 filename = "ucode11";
1664 else if (rev >= 13)
1665 filename = "ucode13";
1666 else
1667 goto err_no_ucode;
1668 err = do_request_fw(dev, filename, &fw->ucode);
1669 if (err)
1670 goto err_load;
1671
1672 /* Get PCM code */
1673 if ((rev >= 5) && (rev <= 10))
1674 filename = "pcm5";
1675 else if (rev >= 11)
1676 filename = NULL;
1677 else
1678 goto err_no_pcm;
1679 err = do_request_fw(dev, filename, &fw->pcm);
1680 if (err)
1681 goto err_load;
1682
1683 /* Get initvals */
1684 switch (dev->phy.type) {
1685 case B43_PHYTYPE_A:
1686 if ((rev >= 5) && (rev <= 10)) {
1687 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1688 filename = "a0g1initvals5";
1689 else
1690 filename = "a0g0initvals5";
1691 } else
1692 goto err_no_initvals;
1693 break;
1694 case B43_PHYTYPE_G:
1695 if ((rev >= 5) && (rev <= 10))
1696 filename = "b0g0initvals5";
1697 else if (rev >= 13)
1698 filename = "lp0initvals13";
1699 else
1700 goto err_no_initvals;
1701 break;
1702 case B43_PHYTYPE_N:
1703 if ((rev >= 11) && (rev <= 12))
1704 filename = "n0initvals11";
1705 else
1706 goto err_no_initvals;
1707 break;
1708 default:
1709 goto err_no_initvals;
1710 }
1711 err = do_request_fw(dev, filename, &fw->initvals);
1712 if (err)
1713 goto err_load;
1714
1715 /* Get bandswitch initvals */
1716 switch (dev->phy.type) {
1717 case B43_PHYTYPE_A:
1718 if ((rev >= 5) && (rev <= 10)) {
1719 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1720 filename = "a0g1bsinitvals5";
1721 else
1722 filename = "a0g0bsinitvals5";
1723 } else if (rev >= 11)
1724 filename = NULL;
1725 else
1726 goto err_no_initvals;
1727 break;
1728 case B43_PHYTYPE_G:
1729 if ((rev >= 5) && (rev <= 10))
1730 filename = "b0g0bsinitvals5";
1731 else if (rev >= 11)
1732 filename = NULL;
1733 else
1734 goto err_no_initvals;
1735 break;
1736 case B43_PHYTYPE_N:
1737 if ((rev >= 11) && (rev <= 12))
1738 filename = "n0bsinitvals11";
1739 else
1740 goto err_no_initvals;
1741 break;
1742 default:
1743 goto err_no_initvals;
1744 }
1745 err = do_request_fw(dev, filename, &fw->initvals_band);
1746 if (err)
1747 goto err_load;
1748
1749 return 0;
1750
1751 err_load:
1752 b43_print_fw_helptext(dev->wl, 1);
1753 goto error;
1754
1755 err_no_ucode:
1756 err = -ENODEV;
1757 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1758 goto error;
1759
1760 err_no_pcm:
1761 err = -ENODEV;
1762 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1763 goto error;
1764
1765 err_no_initvals:
1766 err = -ENODEV;
1767 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1768 "core rev %u\n", dev->phy.type, rev);
1769 goto error;
1770
1771 error:
1772 b43_release_firmware(dev);
1773 return err;
1774 }
1775
1776 static int b43_upload_microcode(struct b43_wldev *dev)
1777 {
1778 const size_t hdr_len = sizeof(struct b43_fw_header);
1779 const __be32 *data;
1780 unsigned int i, len;
1781 u16 fwrev, fwpatch, fwdate, fwtime;
1782 u32 tmp, macctl;
1783 int err = 0;
1784
1785 /* Jump the microcode PSM to offset 0 */
1786 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1787 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
1788 macctl |= B43_MACCTL_PSM_JMP0;
1789 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1790 /* Zero out all microcode PSM registers and shared memory. */
1791 for (i = 0; i < 64; i++)
1792 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
1793 for (i = 0; i < 4096; i += 2)
1794 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
1795
1796 /* Upload Microcode. */
1797 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
1798 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
1799 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1800 for (i = 0; i < len; i++) {
1801 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1802 udelay(10);
1803 }
1804
1805 if (dev->fw.pcm.data) {
1806 /* Upload PCM data. */
1807 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
1808 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
1809 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1810 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1811 /* No need for autoinc bit in SHM_HW */
1812 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1813 for (i = 0; i < len; i++) {
1814 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1815 udelay(10);
1816 }
1817 }
1818
1819 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1820
1821 /* Start the microcode PSM */
1822 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1823 macctl &= ~B43_MACCTL_PSM_JMP0;
1824 macctl |= B43_MACCTL_PSM_RUN;
1825 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1826
1827 /* Wait for the microcode to load and respond */
1828 i = 0;
1829 while (1) {
1830 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1831 if (tmp == B43_IRQ_MAC_SUSPENDED)
1832 break;
1833 i++;
1834 if (i >= 20) {
1835 b43err(dev->wl, "Microcode not responding\n");
1836 b43_print_fw_helptext(dev->wl, 1);
1837 err = -ENODEV;
1838 goto error;
1839 }
1840 msleep_interruptible(50);
1841 if (signal_pending(current)) {
1842 err = -EINTR;
1843 goto error;
1844 }
1845 }
1846 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1847
1848 /* Get and check the revisions. */
1849 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1850 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1851 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1852 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1853
1854 if (fwrev <= 0x128) {
1855 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1856 "binary drivers older than version 4.x is unsupported. "
1857 "You must upgrade your firmware files.\n");
1858 b43_print_fw_helptext(dev->wl, 1);
1859 err = -EOPNOTSUPP;
1860 goto error;
1861 }
1862 b43dbg(dev->wl, "Loading firmware version %u.%u "
1863 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1864 fwrev, fwpatch,
1865 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1866 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1867
1868 dev->fw.rev = fwrev;
1869 dev->fw.patch = fwpatch;
1870
1871 if (b43_is_old_txhdr_format(dev)) {
1872 b43warn(dev->wl, "You are using an old firmware image. "
1873 "Support for old firmware will be removed in July 2008.\n");
1874 b43_print_fw_helptext(dev->wl, 0);
1875 }
1876
1877 return 0;
1878
1879 error:
1880 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1881 macctl &= ~B43_MACCTL_PSM_RUN;
1882 macctl |= B43_MACCTL_PSM_JMP0;
1883 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1884
1885 return err;
1886 }
1887
1888 static int b43_write_initvals(struct b43_wldev *dev,
1889 const struct b43_iv *ivals,
1890 size_t count,
1891 size_t array_size)
1892 {
1893 const struct b43_iv *iv;
1894 u16 offset;
1895 size_t i;
1896 bool bit32;
1897
1898 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1899 iv = ivals;
1900 for (i = 0; i < count; i++) {
1901 if (array_size < sizeof(iv->offset_size))
1902 goto err_format;
1903 array_size -= sizeof(iv->offset_size);
1904 offset = be16_to_cpu(iv->offset_size);
1905 bit32 = !!(offset & B43_IV_32BIT);
1906 offset &= B43_IV_OFFSET_MASK;
1907 if (offset >= 0x1000)
1908 goto err_format;
1909 if (bit32) {
1910 u32 value;
1911
1912 if (array_size < sizeof(iv->data.d32))
1913 goto err_format;
1914 array_size -= sizeof(iv->data.d32);
1915
1916 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1917 b43_write32(dev, offset, value);
1918
1919 iv = (const struct b43_iv *)((const uint8_t *)iv +
1920 sizeof(__be16) +
1921 sizeof(__be32));
1922 } else {
1923 u16 value;
1924
1925 if (array_size < sizeof(iv->data.d16))
1926 goto err_format;
1927 array_size -= sizeof(iv->data.d16);
1928
1929 value = be16_to_cpu(iv->data.d16);
1930 b43_write16(dev, offset, value);
1931
1932 iv = (const struct b43_iv *)((const uint8_t *)iv +
1933 sizeof(__be16) +
1934 sizeof(__be16));
1935 }
1936 }
1937 if (array_size)
1938 goto err_format;
1939
1940 return 0;
1941
1942 err_format:
1943 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1944 b43_print_fw_helptext(dev->wl, 1);
1945
1946 return -EPROTO;
1947 }
1948
1949 static int b43_upload_initvals(struct b43_wldev *dev)
1950 {
1951 const size_t hdr_len = sizeof(struct b43_fw_header);
1952 const struct b43_fw_header *hdr;
1953 struct b43_firmware *fw = &dev->fw;
1954 const struct b43_iv *ivals;
1955 size_t count;
1956 int err;
1957
1958 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
1959 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
1960 count = be32_to_cpu(hdr->size);
1961 err = b43_write_initvals(dev, ivals, count,
1962 fw->initvals.data->size - hdr_len);
1963 if (err)
1964 goto out;
1965 if (fw->initvals_band.data) {
1966 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
1967 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
1968 count = be32_to_cpu(hdr->size);
1969 err = b43_write_initvals(dev, ivals, count,
1970 fw->initvals_band.data->size - hdr_len);
1971 if (err)
1972 goto out;
1973 }
1974 out:
1975
1976 return err;
1977 }
1978
1979 /* Initialize the GPIOs
1980 * http://bcm-specs.sipsolutions.net/GPIO
1981 */
1982 static int b43_gpio_init(struct b43_wldev *dev)
1983 {
1984 struct ssb_bus *bus = dev->dev->bus;
1985 struct ssb_device *gpiodev, *pcidev = NULL;
1986 u32 mask, set;
1987
1988 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1989 & ~B43_MACCTL_GPOUTSMSK);
1990
1991 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1992 | 0x000F);
1993
1994 mask = 0x0000001F;
1995 set = 0x0000000F;
1996 if (dev->dev->bus->chip_id == 0x4301) {
1997 mask |= 0x0060;
1998 set |= 0x0060;
1999 }
2000 if (0 /* FIXME: conditional unknown */ ) {
2001 b43_write16(dev, B43_MMIO_GPIO_MASK,
2002 b43_read16(dev, B43_MMIO_GPIO_MASK)
2003 | 0x0100);
2004 mask |= 0x0180;
2005 set |= 0x0180;
2006 }
2007 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2008 b43_write16(dev, B43_MMIO_GPIO_MASK,
2009 b43_read16(dev, B43_MMIO_GPIO_MASK)
2010 | 0x0200);
2011 mask |= 0x0200;
2012 set |= 0x0200;
2013 }
2014 if (dev->dev->id.revision >= 2)
2015 mask |= 0x0010; /* FIXME: This is redundant. */
2016
2017 #ifdef CONFIG_SSB_DRIVER_PCICORE
2018 pcidev = bus->pcicore.dev;
2019 #endif
2020 gpiodev = bus->chipco.dev ? : pcidev;
2021 if (!gpiodev)
2022 return 0;
2023 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2024 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2025 & mask) | set);
2026
2027 return 0;
2028 }
2029
2030 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2031 static void b43_gpio_cleanup(struct b43_wldev *dev)
2032 {
2033 struct ssb_bus *bus = dev->dev->bus;
2034 struct ssb_device *gpiodev, *pcidev = NULL;
2035
2036 #ifdef CONFIG_SSB_DRIVER_PCICORE
2037 pcidev = bus->pcicore.dev;
2038 #endif
2039 gpiodev = bus->chipco.dev ? : pcidev;
2040 if (!gpiodev)
2041 return;
2042 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2043 }
2044
2045 /* http://bcm-specs.sipsolutions.net/EnableMac */
2046 void b43_mac_enable(struct b43_wldev *dev)
2047 {
2048 dev->mac_suspended--;
2049 B43_WARN_ON(dev->mac_suspended < 0);
2050 B43_WARN_ON(irqs_disabled());
2051 if (dev->mac_suspended == 0) {
2052 b43_write32(dev, B43_MMIO_MACCTL,
2053 b43_read32(dev, B43_MMIO_MACCTL)
2054 | B43_MACCTL_ENABLED);
2055 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2056 B43_IRQ_MAC_SUSPENDED);
2057 /* Commit writes */
2058 b43_read32(dev, B43_MMIO_MACCTL);
2059 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2060 b43_power_saving_ctl_bits(dev, 0);
2061
2062 /* Re-enable IRQs. */
2063 spin_lock_irq(&dev->wl->irq_lock);
2064 b43_interrupt_enable(dev, dev->irq_savedstate);
2065 spin_unlock_irq(&dev->wl->irq_lock);
2066 }
2067 }
2068
2069 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2070 void b43_mac_suspend(struct b43_wldev *dev)
2071 {
2072 int i;
2073 u32 tmp;
2074
2075 might_sleep();
2076 B43_WARN_ON(irqs_disabled());
2077 B43_WARN_ON(dev->mac_suspended < 0);
2078
2079 if (dev->mac_suspended == 0) {
2080 /* Mask IRQs before suspending MAC. Otherwise
2081 * the MAC stays busy and won't suspend. */
2082 spin_lock_irq(&dev->wl->irq_lock);
2083 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2084 spin_unlock_irq(&dev->wl->irq_lock);
2085 b43_synchronize_irq(dev);
2086 dev->irq_savedstate = tmp;
2087
2088 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2089 b43_write32(dev, B43_MMIO_MACCTL,
2090 b43_read32(dev, B43_MMIO_MACCTL)
2091 & ~B43_MACCTL_ENABLED);
2092 /* force pci to flush the write */
2093 b43_read32(dev, B43_MMIO_MACCTL);
2094 for (i = 40; i; i--) {
2095 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2096 if (tmp & B43_IRQ_MAC_SUSPENDED)
2097 goto out;
2098 msleep(1);
2099 }
2100 b43err(dev->wl, "MAC suspend failed\n");
2101 }
2102 out:
2103 dev->mac_suspended++;
2104 }
2105
2106 static void b43_adjust_opmode(struct b43_wldev *dev)
2107 {
2108 struct b43_wl *wl = dev->wl;
2109 u32 ctl;
2110 u16 cfp_pretbtt;
2111
2112 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2113 /* Reset status to STA infrastructure mode. */
2114 ctl &= ~B43_MACCTL_AP;
2115 ctl &= ~B43_MACCTL_KEEP_CTL;
2116 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2117 ctl &= ~B43_MACCTL_KEEP_BAD;
2118 ctl &= ~B43_MACCTL_PROMISC;
2119 ctl &= ~B43_MACCTL_BEACPROMISC;
2120 ctl |= B43_MACCTL_INFRA;
2121
2122 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2123 ctl |= B43_MACCTL_AP;
2124 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2125 ctl &= ~B43_MACCTL_INFRA;
2126
2127 if (wl->filter_flags & FIF_CONTROL)
2128 ctl |= B43_MACCTL_KEEP_CTL;
2129 if (wl->filter_flags & FIF_FCSFAIL)
2130 ctl |= B43_MACCTL_KEEP_BAD;
2131 if (wl->filter_flags & FIF_PLCPFAIL)
2132 ctl |= B43_MACCTL_KEEP_BADPLCP;
2133 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2134 ctl |= B43_MACCTL_PROMISC;
2135 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2136 ctl |= B43_MACCTL_BEACPROMISC;
2137
2138 /* Workaround: On old hardware the HW-MAC-address-filter
2139 * doesn't work properly, so always run promisc in filter
2140 * it in software. */
2141 if (dev->dev->id.revision <= 4)
2142 ctl |= B43_MACCTL_PROMISC;
2143
2144 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2145
2146 cfp_pretbtt = 2;
2147 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2148 if (dev->dev->bus->chip_id == 0x4306 &&
2149 dev->dev->bus->chip_rev == 3)
2150 cfp_pretbtt = 100;
2151 else
2152 cfp_pretbtt = 50;
2153 }
2154 b43_write16(dev, 0x612, cfp_pretbtt);
2155 }
2156
2157 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2158 {
2159 u16 offset;
2160
2161 if (is_ofdm) {
2162 offset = 0x480;
2163 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2164 } else {
2165 offset = 0x4C0;
2166 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2167 }
2168 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2169 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2170 }
2171
2172 static void b43_rate_memory_init(struct b43_wldev *dev)
2173 {
2174 switch (dev->phy.type) {
2175 case B43_PHYTYPE_A:
2176 case B43_PHYTYPE_G:
2177 case B43_PHYTYPE_N:
2178 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2179 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2180 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2181 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2182 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2183 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2184 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2185 if (dev->phy.type == B43_PHYTYPE_A)
2186 break;
2187 /* fallthrough */
2188 case B43_PHYTYPE_B:
2189 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2190 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2191 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2192 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2193 break;
2194 default:
2195 B43_WARN_ON(1);
2196 }
2197 }
2198
2199 /* Set the TX-Antenna for management frames sent by firmware. */
2200 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2201 {
2202 u16 ant = 0;
2203 u16 tmp;
2204
2205 switch (antenna) {
2206 case B43_ANTENNA0:
2207 ant |= B43_TXH_PHY_ANT0;
2208 break;
2209 case B43_ANTENNA1:
2210 ant |= B43_TXH_PHY_ANT1;
2211 break;
2212 case B43_ANTENNA2:
2213 ant |= B43_TXH_PHY_ANT2;
2214 break;
2215 case B43_ANTENNA3:
2216 ant |= B43_TXH_PHY_ANT3;
2217 break;
2218 case B43_ANTENNA_AUTO:
2219 ant |= B43_TXH_PHY_ANT01AUTO;
2220 break;
2221 default:
2222 B43_WARN_ON(1);
2223 }
2224
2225 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2226
2227 /* For Beacons */
2228 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2229 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2230 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2231 /* For ACK/CTS */
2232 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2233 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2234 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2235 /* For Probe Resposes */
2236 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2237 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2238 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2239 }
2240
2241 /* This is the opposite of b43_chip_init() */
2242 static void b43_chip_exit(struct b43_wldev *dev)
2243 {
2244 b43_radio_turn_off(dev, 1);
2245 b43_gpio_cleanup(dev);
2246 /* firmware is released later */
2247 }
2248
2249 /* Initialize the chip
2250 * http://bcm-specs.sipsolutions.net/ChipInit
2251 */
2252 static int b43_chip_init(struct b43_wldev *dev)
2253 {
2254 struct b43_phy *phy = &dev->phy;
2255 int err, tmp;
2256 u32 value32, macctl;
2257 u16 value16;
2258
2259 /* Initialize the MAC control */
2260 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2261 if (dev->phy.gmode)
2262 macctl |= B43_MACCTL_GMODE;
2263 macctl |= B43_MACCTL_INFRA;
2264 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2265
2266 err = b43_request_firmware(dev);
2267 if (err)
2268 goto out;
2269 err = b43_upload_microcode(dev);
2270 if (err)
2271 goto out; /* firmware is released later */
2272
2273 err = b43_gpio_init(dev);
2274 if (err)
2275 goto out; /* firmware is released later */
2276
2277 err = b43_upload_initvals(dev);
2278 if (err)
2279 goto err_gpio_clean;
2280 b43_radio_turn_on(dev);
2281
2282 b43_write16(dev, 0x03E6, 0x0000);
2283 err = b43_phy_init(dev);
2284 if (err)
2285 goto err_radio_off;
2286
2287 /* Select initial Interference Mitigation. */
2288 tmp = phy->interfmode;
2289 phy->interfmode = B43_INTERFMODE_NONE;
2290 b43_radio_set_interference_mitigation(dev, tmp);
2291
2292 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2293 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2294
2295 if (phy->type == B43_PHYTYPE_B) {
2296 value16 = b43_read16(dev, 0x005E);
2297 value16 |= 0x0004;
2298 b43_write16(dev, 0x005E, value16);
2299 }
2300 b43_write32(dev, 0x0100, 0x01000000);
2301 if (dev->dev->id.revision < 5)
2302 b43_write32(dev, 0x010C, 0x01000000);
2303
2304 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2305 & ~B43_MACCTL_INFRA);
2306 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2307 | B43_MACCTL_INFRA);
2308
2309 /* Probe Response Timeout value */
2310 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2311 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2312
2313 /* Initially set the wireless operation mode. */
2314 b43_adjust_opmode(dev);
2315
2316 if (dev->dev->id.revision < 3) {
2317 b43_write16(dev, 0x060E, 0x0000);
2318 b43_write16(dev, 0x0610, 0x8000);
2319 b43_write16(dev, 0x0604, 0x0000);
2320 b43_write16(dev, 0x0606, 0x0200);
2321 } else {
2322 b43_write32(dev, 0x0188, 0x80000000);
2323 b43_write32(dev, 0x018C, 0x02000000);
2324 }
2325 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2326 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2327 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2328 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2329 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2330 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2331 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2332
2333 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2334 value32 |= 0x00100000;
2335 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2336
2337 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2338 dev->dev->bus->chipco.fast_pwrup_delay);
2339
2340 err = 0;
2341 b43dbg(dev->wl, "Chip initialized\n");
2342 out:
2343 return err;
2344
2345 err_radio_off:
2346 b43_radio_turn_off(dev, 1);
2347 err_gpio_clean:
2348 b43_gpio_cleanup(dev);
2349 return err;
2350 }
2351
2352 static void b43_periodic_every120sec(struct b43_wldev *dev)
2353 {
2354 struct b43_phy *phy = &dev->phy;
2355
2356 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2357 return;
2358
2359 b43_mac_suspend(dev);
2360 b43_lo_g_measure(dev);
2361 b43_mac_enable(dev);
2362 if (b43_has_hardware_pctl(phy))
2363 b43_lo_g_ctl_mark_all_unused(dev);
2364 }
2365
2366 static void b43_periodic_every60sec(struct b43_wldev *dev)
2367 {
2368 struct b43_phy *phy = &dev->phy;
2369
2370 if (phy->type != B43_PHYTYPE_G)
2371 return;
2372 if (!b43_has_hardware_pctl(phy))
2373 b43_lo_g_ctl_mark_all_unused(dev);
2374 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2375 b43_mac_suspend(dev);
2376 b43_calc_nrssi_slope(dev);
2377 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2378 u8 old_chan = phy->channel;
2379
2380 /* VCO Calibration */
2381 if (old_chan >= 8)
2382 b43_radio_selectchannel(dev, 1, 0);
2383 else
2384 b43_radio_selectchannel(dev, 13, 0);
2385 b43_radio_selectchannel(dev, old_chan, 0);
2386 }
2387 b43_mac_enable(dev);
2388 }
2389 }
2390
2391 static void b43_periodic_every30sec(struct b43_wldev *dev)
2392 {
2393 /* Update device statistics. */
2394 b43_calculate_link_quality(dev);
2395 }
2396
2397 static void b43_periodic_every15sec(struct b43_wldev *dev)
2398 {
2399 struct b43_phy *phy = &dev->phy;
2400
2401 if (phy->type == B43_PHYTYPE_G) {
2402 //TODO: update_aci_moving_average
2403 if (phy->aci_enable && phy->aci_wlan_automatic) {
2404 b43_mac_suspend(dev);
2405 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2406 if (0 /*TODO: bunch of conditions */ ) {
2407 b43_radio_set_interference_mitigation
2408 (dev, B43_INTERFMODE_MANUALWLAN);
2409 }
2410 } else if (1 /*TODO*/) {
2411 /*
2412 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2413 b43_radio_set_interference_mitigation(dev,
2414 B43_INTERFMODE_NONE);
2415 }
2416 */
2417 }
2418 b43_mac_enable(dev);
2419 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2420 phy->rev == 1) {
2421 //TODO: implement rev1 workaround
2422 }
2423 }
2424 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2425 //TODO for APHY (temperature?)
2426
2427 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2428 wmb();
2429 }
2430
2431 static void do_periodic_work(struct b43_wldev *dev)
2432 {
2433 unsigned int state;
2434
2435 state = dev->periodic_state;
2436 if (state % 8 == 0)
2437 b43_periodic_every120sec(dev);
2438 if (state % 4 == 0)
2439 b43_periodic_every60sec(dev);
2440 if (state % 2 == 0)
2441 b43_periodic_every30sec(dev);
2442 b43_periodic_every15sec(dev);
2443 }
2444
2445 /* Periodic work locking policy:
2446 * The whole periodic work handler is protected by
2447 * wl->mutex. If another lock is needed somewhere in the
2448 * pwork callchain, it's aquired in-place, where it's needed.
2449 */
2450 static void b43_periodic_work_handler(struct work_struct *work)
2451 {
2452 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2453 periodic_work.work);
2454 struct b43_wl *wl = dev->wl;
2455 unsigned long delay;
2456
2457 mutex_lock(&wl->mutex);
2458
2459 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2460 goto out;
2461 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2462 goto out_requeue;
2463
2464 do_periodic_work(dev);
2465
2466 dev->periodic_state++;
2467 out_requeue:
2468 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2469 delay = msecs_to_jiffies(50);
2470 else
2471 delay = round_jiffies_relative(HZ * 15);
2472 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2473 out:
2474 mutex_unlock(&wl->mutex);
2475 }
2476
2477 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2478 {
2479 struct delayed_work *work = &dev->periodic_work;
2480
2481 dev->periodic_state = 0;
2482 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2483 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2484 }
2485
2486 /* Check if communication with the device works correctly. */
2487 static int b43_validate_chipaccess(struct b43_wldev *dev)
2488 {
2489 u32 v, backup;
2490
2491 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2492
2493 /* Check for read/write and endianness problems. */
2494 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2495 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2496 goto error;
2497 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2498 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2499 goto error;
2500
2501 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2502
2503 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2504 /* The 32bit register shadows the two 16bit registers
2505 * with update sideeffects. Validate this. */
2506 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2507 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2508 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2509 goto error;
2510 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2511 goto error;
2512 }
2513 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2514
2515 v = b43_read32(dev, B43_MMIO_MACCTL);
2516 v |= B43_MACCTL_GMODE;
2517 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2518 goto error;
2519
2520 return 0;
2521 error:
2522 b43err(dev->wl, "Failed to validate the chipaccess\n");
2523 return -ENODEV;
2524 }
2525
2526 static void b43_security_init(struct b43_wldev *dev)
2527 {
2528 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2529 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2530 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2531 /* KTP is a word address, but we address SHM bytewise.
2532 * So multiply by two.
2533 */
2534 dev->ktp *= 2;
2535 if (dev->dev->id.revision >= 5) {
2536 /* Number of RCMTA address slots */
2537 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2538 }
2539 b43_clear_keys(dev);
2540 }
2541
2542 static int b43_rng_read(struct hwrng *rng, u32 * data)
2543 {
2544 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2545 unsigned long flags;
2546
2547 /* Don't take wl->mutex here, as it could deadlock with
2548 * hwrng internal locking. It's not needed to take
2549 * wl->mutex here, anyway. */
2550
2551 spin_lock_irqsave(&wl->irq_lock, flags);
2552 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2553 spin_unlock_irqrestore(&wl->irq_lock, flags);
2554
2555 return (sizeof(u16));
2556 }
2557
2558 static void b43_rng_exit(struct b43_wl *wl, bool suspended)
2559 {
2560 if (wl->rng_initialized)
2561 __hwrng_unregister(&wl->rng, suspended);
2562 }
2563
2564 static int b43_rng_init(struct b43_wl *wl)
2565 {
2566 int err;
2567
2568 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2569 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2570 wl->rng.name = wl->rng_name;
2571 wl->rng.data_read = b43_rng_read;
2572 wl->rng.priv = (unsigned long)wl;
2573 wl->rng_initialized = 1;
2574 err = hwrng_register(&wl->rng);
2575 if (err) {
2576 wl->rng_initialized = 0;
2577 b43err(wl, "Failed to register the random "
2578 "number generator (%d)\n", err);
2579 }
2580
2581 return err;
2582 }
2583
2584 static int b43_op_tx(struct ieee80211_hw *hw,
2585 struct sk_buff *skb,
2586 struct ieee80211_tx_control *ctl)
2587 {
2588 struct b43_wl *wl = hw_to_b43_wl(hw);
2589 struct b43_wldev *dev = wl->current_dev;
2590 int err = -ENODEV;
2591
2592 if (unlikely(!dev))
2593 goto out;
2594 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2595 goto out;
2596 /* DMA-TX is done without a global lock. */
2597 err = b43_dma_tx(dev, skb, ctl);
2598 out:
2599 if (unlikely(err))
2600 return NETDEV_TX_BUSY;
2601 return NETDEV_TX_OK;
2602 }
2603
2604 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2605 int queue,
2606 const struct ieee80211_tx_queue_params *params)
2607 {
2608 return 0;
2609 }
2610
2611 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2612 struct ieee80211_tx_queue_stats *stats)
2613 {
2614 struct b43_wl *wl = hw_to_b43_wl(hw);
2615 struct b43_wldev *dev = wl->current_dev;
2616 unsigned long flags;
2617 int err = -ENODEV;
2618
2619 if (!dev)
2620 goto out;
2621 spin_lock_irqsave(&wl->irq_lock, flags);
2622 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2623 b43_dma_get_tx_stats(dev, stats);
2624 err = 0;
2625 }
2626 spin_unlock_irqrestore(&wl->irq_lock, flags);
2627 out:
2628 return err;
2629 }
2630
2631 static int b43_op_get_stats(struct ieee80211_hw *hw,
2632 struct ieee80211_low_level_stats *stats)
2633 {
2634 struct b43_wl *wl = hw_to_b43_wl(hw);
2635 unsigned long flags;
2636
2637 spin_lock_irqsave(&wl->irq_lock, flags);
2638 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2639 spin_unlock_irqrestore(&wl->irq_lock, flags);
2640
2641 return 0;
2642 }
2643
2644 static const char *phymode_to_string(unsigned int phymode)
2645 {
2646 switch (phymode) {
2647 case B43_PHYMODE_A:
2648 return "A";
2649 case B43_PHYMODE_B:
2650 return "B";
2651 case B43_PHYMODE_G:
2652 return "G";
2653 default:
2654 B43_WARN_ON(1);
2655 }
2656 return "";
2657 }
2658
2659 static int find_wldev_for_phymode(struct b43_wl *wl,
2660 unsigned int phymode,
2661 struct b43_wldev **dev, bool * gmode)
2662 {
2663 struct b43_wldev *d;
2664
2665 list_for_each_entry(d, &wl->devlist, list) {
2666 if (d->phy.possible_phymodes & phymode) {
2667 /* Ok, this device supports the PHY-mode.
2668 * Now figure out how the gmode bit has to be
2669 * set to support it. */
2670 if (phymode == B43_PHYMODE_A)
2671 *gmode = 0;
2672 else
2673 *gmode = 1;
2674 *dev = d;
2675
2676 return 0;
2677 }
2678 }
2679
2680 return -ESRCH;
2681 }
2682
2683 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2684 {
2685 struct ssb_device *sdev = dev->dev;
2686 u32 tmslow;
2687
2688 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2689 tmslow &= ~B43_TMSLOW_GMODE;
2690 tmslow |= B43_TMSLOW_PHYRESET;
2691 tmslow |= SSB_TMSLOW_FGC;
2692 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2693 msleep(1);
2694
2695 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2696 tmslow &= ~SSB_TMSLOW_FGC;
2697 tmslow |= B43_TMSLOW_PHYRESET;
2698 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2699 msleep(1);
2700 }
2701
2702 /* Expects wl->mutex locked */
2703 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2704 {
2705 struct b43_wldev *up_dev;
2706 struct b43_wldev *down_dev;
2707 int err;
2708 bool gmode = 0;
2709 int prev_status;
2710
2711 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2712 if (err) {
2713 b43err(wl, "Could not find a device for %s-PHY mode\n",
2714 phymode_to_string(new_mode));
2715 return err;
2716 }
2717 if ((up_dev == wl->current_dev) &&
2718 (!!wl->current_dev->phy.gmode == !!gmode)) {
2719 /* This device is already running. */
2720 return 0;
2721 }
2722 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2723 phymode_to_string(new_mode));
2724 down_dev = wl->current_dev;
2725
2726 prev_status = b43_status(down_dev);
2727 /* Shutdown the currently running core. */
2728 if (prev_status >= B43_STAT_STARTED)
2729 b43_wireless_core_stop(down_dev);
2730 if (prev_status >= B43_STAT_INITIALIZED)
2731 b43_wireless_core_exit(down_dev);
2732
2733 if (down_dev != up_dev) {
2734 /* We switch to a different core, so we put PHY into
2735 * RESET on the old core. */
2736 b43_put_phy_into_reset(down_dev);
2737 }
2738
2739 /* Now start the new core. */
2740 up_dev->phy.gmode = gmode;
2741 if (prev_status >= B43_STAT_INITIALIZED) {
2742 err = b43_wireless_core_init(up_dev);
2743 if (err) {
2744 b43err(wl, "Fatal: Could not initialize device for "
2745 "newly selected %s-PHY mode\n",
2746 phymode_to_string(new_mode));
2747 goto init_failure;
2748 }
2749 }
2750 if (prev_status >= B43_STAT_STARTED) {
2751 err = b43_wireless_core_start(up_dev);
2752 if (err) {
2753 b43err(wl, "Fatal: Coult not start device for "
2754 "newly selected %s-PHY mode\n",
2755 phymode_to_string(new_mode));
2756 b43_wireless_core_exit(up_dev);
2757 goto init_failure;
2758 }
2759 }
2760 B43_WARN_ON(b43_status(up_dev) != prev_status);
2761
2762 wl->current_dev = up_dev;
2763
2764 return 0;
2765 init_failure:
2766 /* Whoops, failed to init the new core. No core is operating now. */
2767 wl->current_dev = NULL;
2768 return err;
2769 }
2770
2771 /* Check if the use of the antenna that ieee80211 told us to
2772 * use is possible. This will fall back to DEFAULT.
2773 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2774 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2775 u8 antenna_nr)
2776 {
2777 u8 antenna_mask;
2778
2779 if (antenna_nr == 0) {
2780 /* Zero means "use default antenna". That's always OK. */
2781 return 0;
2782 }
2783
2784 /* Get the mask of available antennas. */
2785 if (dev->phy.gmode)
2786 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2787 else
2788 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2789
2790 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2791 /* This antenna is not available. Fall back to default. */
2792 return 0;
2793 }
2794
2795 return antenna_nr;
2796 }
2797
2798 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2799 {
2800 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2801 switch (antenna) {
2802 case 0: /* default/diversity */
2803 return B43_ANTENNA_DEFAULT;
2804 case 1: /* Antenna 0 */
2805 return B43_ANTENNA0;
2806 case 2: /* Antenna 1 */
2807 return B43_ANTENNA1;
2808 case 3: /* Antenna 2 */
2809 return B43_ANTENNA2;
2810 case 4: /* Antenna 3 */
2811 return B43_ANTENNA3;
2812 default:
2813 return B43_ANTENNA_DEFAULT;
2814 }
2815 }
2816
2817 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2818 {
2819 struct b43_wl *wl = hw_to_b43_wl(hw);
2820 struct b43_wldev *dev;
2821 struct b43_phy *phy;
2822 unsigned long flags;
2823 unsigned int new_phymode = 0xFFFF;
2824 int antenna;
2825 int err = 0;
2826 u32 savedirqs;
2827
2828 mutex_lock(&wl->mutex);
2829
2830 /* Switch the PHY mode (if necessary). */
2831 switch (conf->phymode) {
2832 case MODE_IEEE80211A:
2833 new_phymode = B43_PHYMODE_A;
2834 break;
2835 case MODE_IEEE80211B:
2836 new_phymode = B43_PHYMODE_B;
2837 break;
2838 case MODE_IEEE80211G:
2839 new_phymode = B43_PHYMODE_G;
2840 break;
2841 default:
2842 B43_WARN_ON(1);
2843 }
2844 err = b43_switch_phymode(wl, new_phymode);
2845 if (err)
2846 goto out_unlock_mutex;
2847 dev = wl->current_dev;
2848 phy = &dev->phy;
2849
2850 /* Disable IRQs while reconfiguring the device.
2851 * This makes it possible to drop the spinlock throughout
2852 * the reconfiguration process. */
2853 spin_lock_irqsave(&wl->irq_lock, flags);
2854 if (b43_status(dev) < B43_STAT_STARTED) {
2855 spin_unlock_irqrestore(&wl->irq_lock, flags);
2856 goto out_unlock_mutex;
2857 }
2858 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2859 spin_unlock_irqrestore(&wl->irq_lock, flags);
2860 b43_synchronize_irq(dev);
2861
2862 /* Switch to the requested channel.
2863 * The firmware takes care of races with the TX handler. */
2864 if (conf->channel_val != phy->channel)
2865 b43_radio_selectchannel(dev, conf->channel_val, 0);
2866
2867 /* Enable/Disable ShortSlot timing. */
2868 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2869 dev->short_slot) {
2870 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2871 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2872 b43_short_slot_timing_enable(dev);
2873 else
2874 b43_short_slot_timing_disable(dev);
2875 }
2876
2877 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2878
2879 /* Adjust the desired TX power level. */
2880 if (conf->power_level != 0) {
2881 if (conf->power_level != phy->power_level) {
2882 phy->power_level = conf->power_level;
2883 b43_phy_xmitpower(dev);
2884 }
2885 }
2886
2887 /* Antennas for RX and management frame TX. */
2888 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2889 b43_mgmtframe_txantenna(dev, antenna);
2890 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2891 b43_set_rx_antenna(dev, antenna);
2892
2893 /* Update templates for AP mode. */
2894 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2895 b43_set_beacon_int(dev, conf->beacon_int);
2896
2897 if (!!conf->radio_enabled != phy->radio_on) {
2898 if (conf->radio_enabled) {
2899 b43_radio_turn_on(dev);
2900 b43info(dev->wl, "Radio turned on by software\n");
2901 if (!dev->radio_hw_enable) {
2902 b43info(dev->wl, "The hardware RF-kill button "
2903 "still turns the radio physically off. "
2904 "Press the button to turn it on.\n");
2905 }
2906 } else {
2907 b43_radio_turn_off(dev, 0);
2908 b43info(dev->wl, "Radio turned off by software\n");
2909 }
2910 }
2911
2912 spin_lock_irqsave(&wl->irq_lock, flags);
2913 b43_interrupt_enable(dev, savedirqs);
2914 mmiowb();
2915 spin_unlock_irqrestore(&wl->irq_lock, flags);
2916 out_unlock_mutex:
2917 mutex_unlock(&wl->mutex);
2918
2919 return err;
2920 }
2921
2922 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2923 const u8 *local_addr, const u8 *addr,
2924 struct ieee80211_key_conf *key)
2925 {
2926 struct b43_wl *wl = hw_to_b43_wl(hw);
2927 struct b43_wldev *dev;
2928 unsigned long flags;
2929 u8 algorithm;
2930 u8 index;
2931 int err;
2932 DECLARE_MAC_BUF(mac);
2933
2934 if (modparam_nohwcrypt)
2935 return -ENOSPC; /* User disabled HW-crypto */
2936
2937 mutex_lock(&wl->mutex);
2938 spin_lock_irqsave(&wl->irq_lock, flags);
2939
2940 dev = wl->current_dev;
2941 err = -ENODEV;
2942 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2943 goto out_unlock;
2944
2945 err = -EINVAL;
2946 switch (key->alg) {
2947 case ALG_WEP:
2948 if (key->keylen == 5)
2949 algorithm = B43_SEC_ALGO_WEP40;
2950 else
2951 algorithm = B43_SEC_ALGO_WEP104;
2952 break;
2953 case ALG_TKIP:
2954 algorithm = B43_SEC_ALGO_TKIP;
2955 break;
2956 case ALG_CCMP:
2957 algorithm = B43_SEC_ALGO_AES;
2958 break;
2959 default:
2960 B43_WARN_ON(1);
2961 goto out_unlock;
2962 }
2963 index = (u8) (key->keyidx);
2964 if (index > 3)
2965 goto out_unlock;
2966
2967 switch (cmd) {
2968 case SET_KEY:
2969 if (algorithm == B43_SEC_ALGO_TKIP) {
2970 /* FIXME: No TKIP hardware encryption for now. */
2971 err = -EOPNOTSUPP;
2972 goto out_unlock;
2973 }
2974
2975 if (is_broadcast_ether_addr(addr)) {
2976 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2977 err = b43_key_write(dev, index, algorithm,
2978 key->key, key->keylen, NULL, key);
2979 } else {
2980 /*
2981 * either pairwise key or address is 00:00:00:00:00:00
2982 * for transmit-only keys
2983 */
2984 err = b43_key_write(dev, -1, algorithm,
2985 key->key, key->keylen, addr, key);
2986 }
2987 if (err)
2988 goto out_unlock;
2989
2990 if (algorithm == B43_SEC_ALGO_WEP40 ||
2991 algorithm == B43_SEC_ALGO_WEP104) {
2992 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2993 } else {
2994 b43_hf_write(dev,
2995 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2996 }
2997 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2998 break;
2999 case DISABLE_KEY: {
3000 err = b43_key_clear(dev, key->hw_key_idx);
3001 if (err)
3002 goto out_unlock;
3003 break;
3004 }
3005 default:
3006 B43_WARN_ON(1);
3007 }
3008 out_unlock:
3009 spin_unlock_irqrestore(&wl->irq_lock, flags);
3010 mutex_unlock(&wl->mutex);
3011 if (!err) {
3012 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3013 "mac: %s\n",
3014 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3015 print_mac(mac, addr));
3016 }
3017 return err;
3018 }
3019
3020 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3021 unsigned int changed, unsigned int *fflags,
3022 int mc_count, struct dev_addr_list *mc_list)
3023 {
3024 struct b43_wl *wl = hw_to_b43_wl(hw);
3025 struct b43_wldev *dev = wl->current_dev;
3026 unsigned long flags;
3027
3028 if (!dev) {
3029 *fflags = 0;
3030 return;
3031 }
3032
3033 spin_lock_irqsave(&wl->irq_lock, flags);
3034 *fflags &= FIF_PROMISC_IN_BSS |
3035 FIF_ALLMULTI |
3036 FIF_FCSFAIL |
3037 FIF_PLCPFAIL |
3038 FIF_CONTROL |
3039 FIF_OTHER_BSS |
3040 FIF_BCN_PRBRESP_PROMISC;
3041
3042 changed &= FIF_PROMISC_IN_BSS |
3043 FIF_ALLMULTI |
3044 FIF_FCSFAIL |
3045 FIF_PLCPFAIL |
3046 FIF_CONTROL |
3047 FIF_OTHER_BSS |
3048 FIF_BCN_PRBRESP_PROMISC;
3049
3050 wl->filter_flags = *fflags;
3051
3052 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3053 b43_adjust_opmode(dev);
3054 spin_unlock_irqrestore(&wl->irq_lock, flags);
3055 }
3056
3057 static int b43_op_config_interface(struct ieee80211_hw *hw,
3058 struct ieee80211_vif *vif,
3059 struct ieee80211_if_conf *conf)
3060 {
3061 struct b43_wl *wl = hw_to_b43_wl(hw);
3062 struct b43_wldev *dev = wl->current_dev;
3063 unsigned long flags;
3064
3065 if (!dev)
3066 return -ENODEV;
3067 mutex_lock(&wl->mutex);
3068 spin_lock_irqsave(&wl->irq_lock, flags);
3069 B43_WARN_ON(wl->vif != vif);
3070 if (conf->bssid)
3071 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3072 else
3073 memset(wl->bssid, 0, ETH_ALEN);
3074 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3075 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
3076 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
3077 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
3078 if (conf->beacon)
3079 b43_update_templates(wl, conf->beacon);
3080 }
3081 b43_write_mac_bssid_templates(dev);
3082 }
3083 spin_unlock_irqrestore(&wl->irq_lock, flags);
3084 mutex_unlock(&wl->mutex);
3085
3086 return 0;
3087 }
3088
3089 /* Locking: wl->mutex */
3090 static void b43_wireless_core_stop(struct b43_wldev *dev)
3091 {
3092 struct b43_wl *wl = dev->wl;
3093 unsigned long flags;
3094
3095 if (b43_status(dev) < B43_STAT_STARTED)
3096 return;
3097
3098 /* Disable and sync interrupts. We must do this before than
3099 * setting the status to INITIALIZED, as the interrupt handler
3100 * won't care about IRQs then. */
3101 spin_lock_irqsave(&wl->irq_lock, flags);
3102 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3103 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3104 spin_unlock_irqrestore(&wl->irq_lock, flags);
3105 b43_synchronize_irq(dev);
3106
3107 b43_set_status(dev, B43_STAT_INITIALIZED);
3108
3109 mutex_unlock(&wl->mutex);
3110 /* Must unlock as it would otherwise deadlock. No races here.
3111 * Cancel the possibly running self-rearming periodic work. */
3112 cancel_delayed_work_sync(&dev->periodic_work);
3113 mutex_lock(&wl->mutex);
3114
3115 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3116
3117 b43_mac_suspend(dev);
3118 free_irq(dev->dev->irq, dev);
3119 b43dbg(wl, "Wireless interface stopped\n");
3120 }
3121
3122 /* Locking: wl->mutex */
3123 static int b43_wireless_core_start(struct b43_wldev *dev)
3124 {
3125 int err;
3126
3127 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3128
3129 drain_txstatus_queue(dev);
3130 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3131 IRQF_SHARED, KBUILD_MODNAME, dev);
3132 if (err) {
3133 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3134 goto out;
3135 }
3136
3137 /* We are ready to run. */
3138 b43_set_status(dev, B43_STAT_STARTED);
3139
3140 /* Start data flow (TX/RX). */
3141 b43_mac_enable(dev);
3142 b43_interrupt_enable(dev, dev->irq_savedstate);
3143 ieee80211_start_queues(dev->wl->hw);
3144
3145 /* Start maintainance work */
3146 b43_periodic_tasks_setup(dev);
3147
3148 b43dbg(dev->wl, "Wireless interface started\n");
3149 out:
3150 return err;
3151 }
3152
3153 /* Get PHY and RADIO versioning numbers */
3154 static int b43_phy_versioning(struct b43_wldev *dev)
3155 {
3156 struct b43_phy *phy = &dev->phy;
3157 u32 tmp;
3158 u8 analog_type;
3159 u8 phy_type;
3160 u8 phy_rev;
3161 u16 radio_manuf;
3162 u16 radio_ver;
3163 u16 radio_rev;
3164 int unsupported = 0;
3165
3166 /* Get PHY versioning */
3167 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3168 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3169 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3170 phy_rev = (tmp & B43_PHYVER_VERSION);
3171 switch (phy_type) {
3172 case B43_PHYTYPE_A:
3173 if (phy_rev >= 4)
3174 unsupported = 1;
3175 break;
3176 case B43_PHYTYPE_B:
3177 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3178 && phy_rev != 7)
3179 unsupported = 1;
3180 break;
3181 case B43_PHYTYPE_G:
3182 if (phy_rev > 9)
3183 unsupported = 1;
3184 break;
3185 #ifdef CONFIG_B43_NPHY
3186 case B43_PHYTYPE_N:
3187 if (phy_rev > 1)
3188 unsupported = 1;
3189 break;
3190 #endif
3191 default:
3192 unsupported = 1;
3193 };
3194 if (unsupported) {
3195 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3196 "(Analog %u, Type %u, Revision %u)\n",
3197 analog_type, phy_type, phy_rev);
3198 return -EOPNOTSUPP;
3199 }
3200 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3201 analog_type, phy_type, phy_rev);
3202
3203 /* Get RADIO versioning */
3204 if (dev->dev->bus->chip_id == 0x4317) {
3205 if (dev->dev->bus->chip_rev == 0)
3206 tmp = 0x3205017F;
3207 else if (dev->dev->bus->chip_rev == 1)
3208 tmp = 0x4205017F;
3209 else
3210 tmp = 0x5205017F;
3211 } else {
3212 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3213 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3214 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3215 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3216 }
3217 radio_manuf = (tmp & 0x00000FFF);
3218 radio_ver = (tmp & 0x0FFFF000) >> 12;
3219 radio_rev = (tmp & 0xF0000000) >> 28;
3220 if (radio_manuf != 0x17F /* Broadcom */)
3221 unsupported = 1;
3222 switch (phy_type) {
3223 case B43_PHYTYPE_A:
3224 if (radio_ver != 0x2060)
3225 unsupported = 1;
3226 if (radio_rev != 1)
3227 unsupported = 1;
3228 if (radio_manuf != 0x17F)
3229 unsupported = 1;
3230 break;
3231 case B43_PHYTYPE_B:
3232 if ((radio_ver & 0xFFF0) != 0x2050)
3233 unsupported = 1;
3234 break;
3235 case B43_PHYTYPE_G:
3236 if (radio_ver != 0x2050)
3237 unsupported = 1;
3238 break;
3239 case B43_PHYTYPE_N:
3240 if (radio_ver != 0x2055)
3241 unsupported = 1;
3242 break;
3243 default:
3244 B43_WARN_ON(1);
3245 }
3246 if (unsupported) {
3247 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3248 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3249 radio_manuf, radio_ver, radio_rev);
3250 return -EOPNOTSUPP;
3251 }
3252 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3253 radio_manuf, radio_ver, radio_rev);
3254
3255 phy->radio_manuf = radio_manuf;
3256 phy->radio_ver = radio_ver;
3257 phy->radio_rev = radio_rev;
3258
3259 phy->analog = analog_type;
3260 phy->type = phy_type;
3261 phy->rev = phy_rev;
3262
3263 return 0;
3264 }
3265
3266 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3267 struct b43_phy *phy)
3268 {
3269 struct b43_txpower_lo_control *lo;
3270 int i;
3271
3272 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3273 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3274
3275 phy->aci_enable = 0;
3276 phy->aci_wlan_automatic = 0;
3277 phy->aci_hw_rssi = 0;
3278
3279 phy->radio_off_context.valid = 0;
3280
3281 lo = phy->lo_control;
3282 if (lo) {
3283 memset(lo, 0, sizeof(*(phy->lo_control)));
3284 lo->rebuild = 1;
3285 lo->tx_bias = 0xFF;
3286 }
3287 phy->max_lb_gain = 0;
3288 phy->trsw_rx_gain = 0;
3289 phy->txpwr_offset = 0;
3290
3291 /* NRSSI */
3292 phy->nrssislope = 0;
3293 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3294 phy->nrssi[i] = -1000;
3295 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3296 phy->nrssi_lt[i] = i;
3297
3298 phy->lofcal = 0xFFFF;
3299 phy->initval = 0xFFFF;
3300
3301 phy->interfmode = B43_INTERFMODE_NONE;
3302 phy->channel = 0xFF;
3303
3304 phy->hardware_power_control = !!modparam_hwpctl;
3305
3306 /* PHY TX errors counter. */
3307 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3308
3309 /* OFDM-table address caching. */
3310 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3311 }
3312
3313 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3314 {
3315 dev->dfq_valid = 0;
3316
3317 /* Assume the radio is enabled. If it's not enabled, the state will
3318 * immediately get fixed on the first periodic work run. */
3319 dev->radio_hw_enable = 1;
3320
3321 /* Stats */
3322 memset(&dev->stats, 0, sizeof(dev->stats));
3323
3324 setup_struct_phy_for_init(dev, &dev->phy);
3325
3326 /* IRQ related flags */
3327 dev->irq_reason = 0;
3328 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3329 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3330
3331 dev->mac_suspended = 1;
3332
3333 /* Noise calculation context */
3334 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3335 }
3336
3337 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3338 {
3339 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3340 u32 hf;
3341
3342 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3343 return;
3344 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3345 return;
3346
3347 hf = b43_hf_read(dev);
3348 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3349 hf |= B43_HF_BTCOEXALT;
3350 else
3351 hf |= B43_HF_BTCOEX;
3352 b43_hf_write(dev, hf);
3353 //TODO
3354 }
3355
3356 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3357 { //TODO
3358 }
3359
3360 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3361 {
3362 #ifdef CONFIG_SSB_DRIVER_PCICORE
3363 struct ssb_bus *bus = dev->dev->bus;
3364 u32 tmp;
3365
3366 if (bus->pcicore.dev &&
3367 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3368 bus->pcicore.dev->id.revision <= 5) {
3369 /* IMCFGLO timeouts workaround. */
3370 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3371 tmp &= ~SSB_IMCFGLO_REQTO;
3372 tmp &= ~SSB_IMCFGLO_SERTO;
3373 switch (bus->bustype) {
3374 case SSB_BUSTYPE_PCI:
3375 case SSB_BUSTYPE_PCMCIA:
3376 tmp |= 0x32;
3377 break;
3378 case SSB_BUSTYPE_SSB:
3379 tmp |= 0x53;
3380 break;
3381 }
3382 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3383 }
3384 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3385 }
3386
3387 /* Write the short and long frame retry limit values. */
3388 static void b43_set_retry_limits(struct b43_wldev *dev,
3389 unsigned int short_retry,
3390 unsigned int long_retry)
3391 {
3392 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3393 * the chip-internal counter. */
3394 short_retry = min(short_retry, (unsigned int)0xF);
3395 long_retry = min(long_retry, (unsigned int)0xF);
3396
3397 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3398 short_retry);
3399 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3400 long_retry);
3401 }
3402
3403 /* Shutdown a wireless core */
3404 /* Locking: wl->mutex */
3405 static void b43_wireless_core_exit(struct b43_wldev *dev)
3406 {
3407 struct b43_phy *phy = &dev->phy;
3408 u32 macctl;
3409
3410 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3411 if (b43_status(dev) != B43_STAT_INITIALIZED)
3412 return;
3413 b43_set_status(dev, B43_STAT_UNINIT);
3414
3415 /* Stop the microcode PSM. */
3416 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3417 macctl &= ~B43_MACCTL_PSM_RUN;
3418 macctl |= B43_MACCTL_PSM_JMP0;
3419 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3420
3421 if (!dev->suspend_in_progress) {
3422 b43_leds_exit(dev);
3423 b43_rng_exit(dev->wl, false);
3424 }
3425 b43_dma_free(dev);
3426 b43_chip_exit(dev);
3427 b43_radio_turn_off(dev, 1);
3428 b43_switch_analog(dev, 0);
3429 if (phy->dyn_tssi_tbl)
3430 kfree(phy->tssi2dbm);
3431 kfree(phy->lo_control);
3432 phy->lo_control = NULL;
3433 if (dev->wl->current_beacon) {
3434 dev_kfree_skb_any(dev->wl->current_beacon);
3435 dev->wl->current_beacon = NULL;
3436 }
3437
3438 ssb_device_disable(dev->dev, 0);
3439 ssb_bus_may_powerdown(dev->dev->bus);
3440 }
3441
3442 /* Initialize a wireless core */
3443 static int b43_wireless_core_init(struct b43_wldev *dev)
3444 {
3445 struct b43_wl *wl = dev->wl;
3446 struct ssb_bus *bus = dev->dev->bus;
3447 struct ssb_sprom *sprom = &bus->sprom;
3448 struct b43_phy *phy = &dev->phy;
3449 int err;
3450 u32 hf, tmp;
3451
3452 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3453
3454 err = ssb_bus_powerup(bus, 0);
3455 if (err)
3456 goto out;
3457 if (!ssb_device_is_enabled(dev->dev)) {
3458 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3459 b43_wireless_core_reset(dev, tmp);
3460 }
3461
3462 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3463 phy->lo_control =
3464 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3465 if (!phy->lo_control) {
3466 err = -ENOMEM;
3467 goto err_busdown;
3468 }
3469 }
3470 setup_struct_wldev_for_init(dev);
3471
3472 err = b43_phy_init_tssi2dbm_table(dev);
3473 if (err)
3474 goto err_kfree_lo_control;
3475
3476 /* Enable IRQ routing to this device. */
3477 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3478
3479 b43_imcfglo_timeouts_workaround(dev);
3480 b43_bluetooth_coext_disable(dev);
3481 b43_phy_early_init(dev);
3482 err = b43_chip_init(dev);
3483 if (err)
3484 goto err_kfree_tssitbl;
3485 b43_shm_write16(dev, B43_SHM_SHARED,
3486 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3487 hf = b43_hf_read(dev);
3488 if (phy->type == B43_PHYTYPE_G) {
3489 hf |= B43_HF_SYMW;
3490 if (phy->rev == 1)
3491 hf |= B43_HF_GDCW;
3492 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3493 hf |= B43_HF_OFDMPABOOST;
3494 } else if (phy->type == B43_PHYTYPE_B) {
3495 hf |= B43_HF_SYMW;
3496 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3497 hf &= ~B43_HF_GDCW;
3498 }
3499 b43_hf_write(dev, hf);
3500
3501 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3502 B43_DEFAULT_LONG_RETRY_LIMIT);
3503 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3504 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3505
3506 /* Disable sending probe responses from firmware.
3507 * Setting the MaxTime to one usec will always trigger
3508 * a timeout, so we never send any probe resp.
3509 * A timeout of zero is infinite. */
3510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3511
3512 b43_rate_memory_init(dev);
3513
3514 /* Minimum Contention Window */
3515 if (phy->type == B43_PHYTYPE_B) {
3516 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3517 } else {
3518 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3519 }
3520 /* Maximum Contention Window */
3521 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3522
3523 err = b43_dma_init(dev);
3524 if (err)
3525 goto err_chip_exit;
3526 b43_qos_init(dev);
3527
3528 //FIXME
3529 #if 1
3530 b43_write16(dev, 0x0612, 0x0050);
3531 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3532 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3533 #endif
3534
3535 b43_bluetooth_coext_enable(dev);
3536
3537 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3538 b43_upload_card_macaddress(dev);
3539 b43_security_init(dev);
3540 if (!dev->suspend_in_progress)
3541 b43_rng_init(wl);
3542
3543 b43_set_status(dev, B43_STAT_INITIALIZED);
3544
3545 if (!dev->suspend_in_progress)
3546 b43_leds_init(dev);
3547 out:
3548 return err;
3549
3550 err_chip_exit:
3551 b43_chip_exit(dev);
3552 err_kfree_tssitbl:
3553 if (phy->dyn_tssi_tbl)
3554 kfree(phy->tssi2dbm);
3555 err_kfree_lo_control:
3556 kfree(phy->lo_control);
3557 phy->lo_control = NULL;
3558 err_busdown:
3559 ssb_bus_may_powerdown(bus);
3560 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3561 return err;
3562 }
3563
3564 static int b43_op_add_interface(struct ieee80211_hw *hw,
3565 struct ieee80211_if_init_conf *conf)
3566 {
3567 struct b43_wl *wl = hw_to_b43_wl(hw);
3568 struct b43_wldev *dev;
3569 unsigned long flags;
3570 int err = -EOPNOTSUPP;
3571
3572 /* TODO: allow WDS/AP devices to coexist */
3573
3574 if (conf->type != IEEE80211_IF_TYPE_AP &&
3575 conf->type != IEEE80211_IF_TYPE_STA &&
3576 conf->type != IEEE80211_IF_TYPE_WDS &&
3577 conf->type != IEEE80211_IF_TYPE_IBSS)
3578 return -EOPNOTSUPP;
3579
3580 mutex_lock(&wl->mutex);
3581 if (wl->operating)
3582 goto out_mutex_unlock;
3583
3584 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3585
3586 dev = wl->current_dev;
3587 wl->operating = 1;
3588 wl->vif = conf->vif;
3589 wl->if_type = conf->type;
3590 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3591
3592 spin_lock_irqsave(&wl->irq_lock, flags);
3593 b43_adjust_opmode(dev);
3594 b43_upload_card_macaddress(dev);
3595 spin_unlock_irqrestore(&wl->irq_lock, flags);
3596
3597 err = 0;
3598 out_mutex_unlock:
3599 mutex_unlock(&wl->mutex);
3600
3601 return err;
3602 }
3603
3604 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3605 struct ieee80211_if_init_conf *conf)
3606 {
3607 struct b43_wl *wl = hw_to_b43_wl(hw);
3608 struct b43_wldev *dev = wl->current_dev;
3609 unsigned long flags;
3610
3611 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3612
3613 mutex_lock(&wl->mutex);
3614
3615 B43_WARN_ON(!wl->operating);
3616 B43_WARN_ON(wl->vif != conf->vif);
3617 wl->vif = NULL;
3618
3619 wl->operating = 0;
3620
3621 spin_lock_irqsave(&wl->irq_lock, flags);
3622 b43_adjust_opmode(dev);
3623 memset(wl->mac_addr, 0, ETH_ALEN);
3624 b43_upload_card_macaddress(dev);
3625 spin_unlock_irqrestore(&wl->irq_lock, flags);
3626
3627 mutex_unlock(&wl->mutex);
3628 }
3629
3630 static int b43_op_start(struct ieee80211_hw *hw)
3631 {
3632 struct b43_wl *wl = hw_to_b43_wl(hw);
3633 struct b43_wldev *dev = wl->current_dev;
3634 int did_init = 0;
3635 int err = 0;
3636 bool do_rfkill_exit = 0;
3637
3638 /* Kill all old instance specific information to make sure
3639 * the card won't use it in the short timeframe between start
3640 * and mac80211 reconfiguring it. */
3641 memset(wl->bssid, 0, ETH_ALEN);
3642 memset(wl->mac_addr, 0, ETH_ALEN);
3643 wl->filter_flags = 0;
3644 wl->radiotap_enabled = 0;
3645
3646 /* First register RFkill.
3647 * LEDs that are registered later depend on it. */
3648 b43_rfkill_init(dev);
3649
3650 mutex_lock(&wl->mutex);
3651
3652 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3653 err = b43_wireless_core_init(dev);
3654 if (err) {
3655 do_rfkill_exit = 1;
3656 goto out_mutex_unlock;
3657 }
3658 did_init = 1;
3659 }
3660
3661 if (b43_status(dev) < B43_STAT_STARTED) {
3662 err = b43_wireless_core_start(dev);
3663 if (err) {
3664 if (did_init)
3665 b43_wireless_core_exit(dev);
3666 do_rfkill_exit = 1;
3667 goto out_mutex_unlock;
3668 }
3669 }
3670
3671 out_mutex_unlock:
3672 mutex_unlock(&wl->mutex);
3673
3674 if (do_rfkill_exit)
3675 b43_rfkill_exit(dev);
3676
3677 return err;
3678 }
3679
3680 static void b43_op_stop(struct ieee80211_hw *hw)
3681 {
3682 struct b43_wl *wl = hw_to_b43_wl(hw);
3683 struct b43_wldev *dev = wl->current_dev;
3684
3685 b43_rfkill_exit(dev);
3686
3687 mutex_lock(&wl->mutex);
3688 if (b43_status(dev) >= B43_STAT_STARTED)
3689 b43_wireless_core_stop(dev);
3690 b43_wireless_core_exit(dev);
3691 mutex_unlock(&wl->mutex);
3692 }
3693
3694 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3695 u32 short_retry_limit, u32 long_retry_limit)
3696 {
3697 struct b43_wl *wl = hw_to_b43_wl(hw);
3698 struct b43_wldev *dev;
3699 int err = 0;
3700
3701 mutex_lock(&wl->mutex);
3702 dev = wl->current_dev;
3703 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3704 err = -ENODEV;
3705 goto out_unlock;
3706 }
3707 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3708 out_unlock:
3709 mutex_unlock(&wl->mutex);
3710
3711 return err;
3712 }
3713
3714 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3715 {
3716 struct b43_wl *wl = hw_to_b43_wl(hw);
3717 struct sk_buff *beacon;
3718 unsigned long flags;
3719
3720 /* We could modify the existing beacon and set the aid bit in
3721 * the TIM field, but that would probably require resizing and
3722 * moving of data within the beacon template.
3723 * Simply request a new beacon and let mac80211 do the hard work. */
3724 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3725 if (unlikely(!beacon))
3726 return -ENOMEM;
3727 spin_lock_irqsave(&wl->irq_lock, flags);
3728 b43_update_templates(wl, beacon);
3729 spin_unlock_irqrestore(&wl->irq_lock, flags);
3730
3731 return 0;
3732 }
3733
3734 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3735 struct sk_buff *beacon,
3736 struct ieee80211_tx_control *ctl)
3737 {
3738 struct b43_wl *wl = hw_to_b43_wl(hw);
3739 unsigned long flags;
3740
3741 spin_lock_irqsave(&wl->irq_lock, flags);
3742 b43_update_templates(wl, beacon);
3743 spin_unlock_irqrestore(&wl->irq_lock, flags);
3744
3745 return 0;
3746 }
3747
3748 static const struct ieee80211_ops b43_hw_ops = {
3749 .tx = b43_op_tx,
3750 .conf_tx = b43_op_conf_tx,
3751 .add_interface = b43_op_add_interface,
3752 .remove_interface = b43_op_remove_interface,
3753 .config = b43_op_config,
3754 .config_interface = b43_op_config_interface,
3755 .configure_filter = b43_op_configure_filter,
3756 .set_key = b43_op_set_key,
3757 .get_stats = b43_op_get_stats,
3758 .get_tx_stats = b43_op_get_tx_stats,
3759 .start = b43_op_start,
3760 .stop = b43_op_stop,
3761 .set_retry_limit = b43_op_set_retry_limit,
3762 .set_tim = b43_op_beacon_set_tim,
3763 .beacon_update = b43_op_ibss_beacon_update,
3764 };
3765
3766 /* Hard-reset the chip. Do not call this directly.
3767 * Use b43_controller_restart()
3768 */
3769 static void b43_chip_reset(struct work_struct *work)
3770 {
3771 struct b43_wldev *dev =
3772 container_of(work, struct b43_wldev, restart_work);
3773 struct b43_wl *wl = dev->wl;
3774 int err = 0;
3775 int prev_status;
3776
3777 mutex_lock(&wl->mutex);
3778
3779 prev_status = b43_status(dev);
3780 /* Bring the device down... */
3781 if (prev_status >= B43_STAT_STARTED)
3782 b43_wireless_core_stop(dev);
3783 if (prev_status >= B43_STAT_INITIALIZED)
3784 b43_wireless_core_exit(dev);
3785
3786 /* ...and up again. */
3787 if (prev_status >= B43_STAT_INITIALIZED) {
3788 err = b43_wireless_core_init(dev);
3789 if (err)
3790 goto out;
3791 }
3792 if (prev_status >= B43_STAT_STARTED) {
3793 err = b43_wireless_core_start(dev);
3794 if (err) {
3795 b43_wireless_core_exit(dev);
3796 goto out;
3797 }
3798 }
3799 out:
3800 mutex_unlock(&wl->mutex);
3801 if (err)
3802 b43err(wl, "Controller restart FAILED\n");
3803 else
3804 b43info(wl, "Controller restarted\n");
3805 }
3806
3807 static int b43_setup_modes(struct b43_wldev *dev,
3808 bool have_2ghz_phy, bool have_5ghz_phy)
3809 {
3810 struct ieee80211_hw *hw = dev->wl->hw;
3811 struct ieee80211_hw_mode *mode;
3812 struct b43_phy *phy = &dev->phy;
3813 int err;
3814
3815 /* XXX: This function will go away soon, when mac80211
3816 * band stuff is rewritten. So this is just a hack.
3817 * For now we always claim GPHY mode, as there is no
3818 * support for NPHY and APHY in the device, yet.
3819 * This assumption is OK, as any B, N or A PHY will already
3820 * have died a horrible sanity check death earlier. */
3821
3822 mode = &phy->hwmodes[0];
3823 mode->mode = MODE_IEEE80211G;
3824 mode->num_channels = b43_2ghz_chantable_size;
3825 mode->channels = b43_2ghz_chantable;
3826 mode->num_rates = b43_g_ratetable_size;
3827 mode->rates = b43_g_ratetable;
3828 err = ieee80211_register_hwmode(hw, mode);
3829 if (err)
3830 return err;
3831 phy->possible_phymodes |= B43_PHYMODE_G;
3832
3833 return 0;
3834 }
3835
3836 static void b43_wireless_core_detach(struct b43_wldev *dev)
3837 {
3838 /* We release firmware that late to not be required to re-request
3839 * is all the time when we reinit the core. */
3840 b43_release_firmware(dev);
3841 }
3842
3843 static int b43_wireless_core_attach(struct b43_wldev *dev)
3844 {
3845 struct b43_wl *wl = dev->wl;
3846 struct ssb_bus *bus = dev->dev->bus;
3847 struct pci_dev *pdev = bus->host_pci;
3848 int err;
3849 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3850 u32 tmp;
3851
3852 /* Do NOT do any device initialization here.
3853 * Do it in wireless_core_init() instead.
3854 * This function is for gathering basic information about the HW, only.
3855 * Also some structs may be set up here. But most likely you want to have
3856 * that in core_init(), too.
3857 */
3858
3859 err = ssb_bus_powerup(bus, 0);
3860 if (err) {
3861 b43err(wl, "Bus powerup failed\n");
3862 goto out;
3863 }
3864 /* Get the PHY type. */
3865 if (dev->dev->id.revision >= 5) {
3866 u32 tmshigh;
3867
3868 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3869 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3870 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3871 } else
3872 B43_WARN_ON(1);
3873
3874 dev->phy.gmode = have_2ghz_phy;
3875 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3876 b43_wireless_core_reset(dev, tmp);
3877
3878 err = b43_phy_versioning(dev);
3879 if (err)
3880 goto err_powerdown;
3881 /* Check if this device supports multiband. */
3882 if (!pdev ||
3883 (pdev->device != 0x4312 &&
3884 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3885 /* No multiband support. */
3886 have_2ghz_phy = 0;
3887 have_5ghz_phy = 0;
3888 switch (dev->phy.type) {
3889 case B43_PHYTYPE_A:
3890 have_5ghz_phy = 1;
3891 break;
3892 case B43_PHYTYPE_G:
3893 case B43_PHYTYPE_N:
3894 have_2ghz_phy = 1;
3895 break;
3896 default:
3897 B43_WARN_ON(1);
3898 }
3899 }
3900 if (dev->phy.type == B43_PHYTYPE_A) {
3901 /* FIXME */
3902 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3903 err = -EOPNOTSUPP;
3904 goto err_powerdown;
3905 }
3906 dev->phy.gmode = have_2ghz_phy;
3907 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3908 b43_wireless_core_reset(dev, tmp);
3909
3910 err = b43_validate_chipaccess(dev);
3911 if (err)
3912 goto err_powerdown;
3913 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3914 if (err)
3915 goto err_powerdown;
3916
3917 /* Now set some default "current_dev" */
3918 if (!wl->current_dev)
3919 wl->current_dev = dev;
3920 INIT_WORK(&dev->restart_work, b43_chip_reset);
3921
3922 b43_radio_turn_off(dev, 1);
3923 b43_switch_analog(dev, 0);
3924 ssb_device_disable(dev->dev, 0);
3925 ssb_bus_may_powerdown(bus);
3926
3927 out:
3928 return err;
3929
3930 err_powerdown:
3931 ssb_bus_may_powerdown(bus);
3932 return err;
3933 }
3934
3935 static void b43_one_core_detach(struct ssb_device *dev)
3936 {
3937 struct b43_wldev *wldev;
3938 struct b43_wl *wl;
3939
3940 wldev = ssb_get_drvdata(dev);
3941 wl = wldev->wl;
3942 cancel_work_sync(&wldev->restart_work);
3943 b43_debugfs_remove_device(wldev);
3944 b43_wireless_core_detach(wldev);
3945 list_del(&wldev->list);
3946 wl->nr_devs--;
3947 ssb_set_drvdata(dev, NULL);
3948 kfree(wldev);
3949 }
3950
3951 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3952 {
3953 struct b43_wldev *wldev;
3954 struct pci_dev *pdev;
3955 int err = -ENOMEM;
3956
3957 if (!list_empty(&wl->devlist)) {
3958 /* We are not the first core on this chip. */
3959 pdev = dev->bus->host_pci;
3960 /* Only special chips support more than one wireless
3961 * core, although some of the other chips have more than
3962 * one wireless core as well. Check for this and
3963 * bail out early.
3964 */
3965 if (!pdev ||
3966 ((pdev->device != 0x4321) &&
3967 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3968 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3969 return -ENODEV;
3970 }
3971 }
3972
3973 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3974 if (!wldev)
3975 goto out;
3976
3977 wldev->dev = dev;
3978 wldev->wl = wl;
3979 b43_set_status(wldev, B43_STAT_UNINIT);
3980 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3981 tasklet_init(&wldev->isr_tasklet,
3982 (void (*)(unsigned long))b43_interrupt_tasklet,
3983 (unsigned long)wldev);
3984 INIT_LIST_HEAD(&wldev->list);
3985
3986 err = b43_wireless_core_attach(wldev);
3987 if (err)
3988 goto err_kfree_wldev;
3989
3990 list_add(&wldev->list, &wl->devlist);
3991 wl->nr_devs++;
3992 ssb_set_drvdata(dev, wldev);
3993 b43_debugfs_add_device(wldev);
3994
3995 out:
3996 return err;
3997
3998 err_kfree_wldev:
3999 kfree(wldev);
4000 return err;
4001 }
4002
4003 static void b43_sprom_fixup(struct ssb_bus *bus)
4004 {
4005 /* boardflags workarounds */
4006 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4007 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4008 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4009 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4010 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4011 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4012 }
4013
4014 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4015 {
4016 struct ieee80211_hw *hw = wl->hw;
4017
4018 ssb_set_devtypedata(dev, NULL);
4019 ieee80211_free_hw(hw);
4020 }
4021
4022 static int b43_wireless_init(struct ssb_device *dev)
4023 {
4024 struct ssb_sprom *sprom = &dev->bus->sprom;
4025 struct ieee80211_hw *hw;
4026 struct b43_wl *wl;
4027 int err = -ENOMEM;
4028
4029 b43_sprom_fixup(dev->bus);
4030
4031 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4032 if (!hw) {
4033 b43err(NULL, "Could not allocate ieee80211 device\n");
4034 goto out;
4035 }
4036
4037 /* fill hw info */
4038 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
4039 IEEE80211_HW_RX_INCLUDES_FCS;
4040 hw->max_signal = 100;
4041 hw->max_rssi = -110;
4042 hw->max_noise = -110;
4043 hw->queues = 1; /* FIXME: hardware has more queues */
4044 SET_IEEE80211_DEV(hw, dev->dev);
4045 if (is_valid_ether_addr(sprom->et1mac))
4046 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4047 else
4048 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4049
4050 /* Get and initialize struct b43_wl */
4051 wl = hw_to_b43_wl(hw);
4052 memset(wl, 0, sizeof(*wl));
4053 wl->hw = hw;
4054 spin_lock_init(&wl->irq_lock);
4055 spin_lock_init(&wl->leds_lock);
4056 spin_lock_init(&wl->shm_lock);
4057 mutex_init(&wl->mutex);
4058 INIT_LIST_HEAD(&wl->devlist);
4059
4060 ssb_set_devtypedata(dev, wl);
4061 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4062 err = 0;
4063 out:
4064 return err;
4065 }
4066
4067 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4068 {
4069 struct b43_wl *wl;
4070 int err;
4071 int first = 0;
4072
4073 wl = ssb_get_devtypedata(dev);
4074 if (!wl) {
4075 /* Probing the first core. Must setup common struct b43_wl */
4076 first = 1;
4077 err = b43_wireless_init(dev);
4078 if (err)
4079 goto out;
4080 wl = ssb_get_devtypedata(dev);
4081 B43_WARN_ON(!wl);
4082 }
4083 err = b43_one_core_attach(dev, wl);
4084 if (err)
4085 goto err_wireless_exit;
4086
4087 if (first) {
4088 err = ieee80211_register_hw(wl->hw);
4089 if (err)
4090 goto err_one_core_detach;
4091 }
4092
4093 out:
4094 return err;
4095
4096 err_one_core_detach:
4097 b43_one_core_detach(dev);
4098 err_wireless_exit:
4099 if (first)
4100 b43_wireless_exit(dev, wl);
4101 return err;
4102 }
4103
4104 static void b43_remove(struct ssb_device *dev)
4105 {
4106 struct b43_wl *wl = ssb_get_devtypedata(dev);
4107 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4108
4109 B43_WARN_ON(!wl);
4110 if (wl->current_dev == wldev)
4111 ieee80211_unregister_hw(wl->hw);
4112
4113 b43_one_core_detach(dev);
4114
4115 if (list_empty(&wl->devlist)) {
4116 /* Last core on the chip unregistered.
4117 * We can destroy common struct b43_wl.
4118 */
4119 b43_wireless_exit(dev, wl);
4120 }
4121 }
4122
4123 /* Perform a hardware reset. This can be called from any context. */
4124 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4125 {
4126 /* Must avoid requeueing, if we are in shutdown. */
4127 if (b43_status(dev) < B43_STAT_INITIALIZED)
4128 return;
4129 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4130 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4131 }
4132
4133 #ifdef CONFIG_PM
4134
4135 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4136 {
4137 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4138 struct b43_wl *wl = wldev->wl;
4139
4140 b43dbg(wl, "Suspending...\n");
4141
4142 mutex_lock(&wl->mutex);
4143 wldev->suspend_in_progress = true;
4144 wldev->suspend_init_status = b43_status(wldev);
4145 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4146 b43_wireless_core_stop(wldev);
4147 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4148 b43_wireless_core_exit(wldev);
4149 mutex_unlock(&wl->mutex);
4150
4151 b43dbg(wl, "Device suspended.\n");
4152
4153 return 0;
4154 }
4155
4156 static int b43_resume(struct ssb_device *dev)
4157 {
4158 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4159 struct b43_wl *wl = wldev->wl;
4160 int err = 0;
4161
4162 b43dbg(wl, "Resuming...\n");
4163
4164 mutex_lock(&wl->mutex);
4165 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4166 err = b43_wireless_core_init(wldev);
4167 if (err) {
4168 b43err(wl, "Resume failed at core init\n");
4169 goto out;
4170 }
4171 }
4172 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4173 err = b43_wireless_core_start(wldev);
4174 if (err) {
4175 b43_leds_exit(wldev);
4176 b43_rng_exit(wldev->wl, true);
4177 b43_wireless_core_exit(wldev);
4178 b43err(wl, "Resume failed at core start\n");
4179 goto out;
4180 }
4181 }
4182 b43dbg(wl, "Device resumed.\n");
4183 out:
4184 wldev->suspend_in_progress = false;
4185 mutex_unlock(&wl->mutex);
4186 return err;
4187 }
4188
4189 #else /* CONFIG_PM */
4190 # define b43_suspend NULL
4191 # define b43_resume NULL
4192 #endif /* CONFIG_PM */
4193
4194 static struct ssb_driver b43_ssb_driver = {
4195 .name = KBUILD_MODNAME,
4196 .id_table = b43_ssb_tbl,
4197 .probe = b43_probe,
4198 .remove = b43_remove,
4199 .suspend = b43_suspend,
4200 .resume = b43_resume,
4201 };
4202
4203 static int __init b43_init(void)
4204 {
4205 int err;
4206
4207 b43_debugfs_init();
4208 err = b43_pcmcia_init();
4209 if (err)
4210 goto err_dfs_exit;
4211 err = ssb_driver_register(&b43_ssb_driver);
4212 if (err)
4213 goto err_pcmcia_exit;
4214
4215 return err;
4216
4217 err_pcmcia_exit:
4218 b43_pcmcia_exit();
4219 err_dfs_exit:
4220 b43_debugfs_exit();
4221 return err;
4222 }
4223
4224 static void __exit b43_exit(void)
4225 {
4226 ssb_driver_unregister(&b43_ssb_driver);
4227 b43_pcmcia_exit();
4228 b43_debugfs_exit();
4229 }
4230
4231 module_init(b43_init)
4232 module_exit(b43_exit)
WRT350N Kernel Patches