arch/arm/mach-pxa/irq.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/irq.c
   3  *
   4  *  Generic PXA IRQ handling, GPIO IRQ demultiplexing, etc.
   5  *
   6  *  Author:     Nicolas Pitre
   7  *  Created:    Jun 15, 2001
   8  *  Copyright:  MontaVista Software Inc.
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/module.h>
  17 #include <linux/interrupt.h>
  18
  19 #include <asm/hardware.h>
  20 #include <asm/irq.h>
  21 #include <asm/mach/irq.h>
  22 #include <asm/arch/pxa-regs.h>
  23
  24 #include "generic.h"
  25
  26
  27 /*
  28  * This is for peripheral IRQs internal to the PXA chip.
  29  */
  30
  31 static void pxa_mask_low_irq(unsigned int irq)
  32 {
  33         ICMR &= ~(1 << (irq + PXA_IRQ_SKIP));
  34 }
  35
  36 static void pxa_unmask_low_irq(unsigned int irq)
  37 {
  38         ICMR |= (1 << (irq + PXA_IRQ_SKIP));
  39 }
  40
  41 static int pxa_set_wake(unsigned int irq, unsigned int on)
  42 {
  43         u32     mask;
  44
  45         switch (irq) {
  46         case IRQ_RTCAlrm:
  47                 mask = PWER_RTC;
  48                 break;
  49 #ifdef CONFIG_PXA27x
  50         /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
  51 #endif
  52         default:
  53                 return -EINVAL;
  54         }
  55         if (on)
  56                 PWER |= mask;
  57         else
  58                 PWER &= ~mask;
  59         return 0;
  60 }
  61
  62 static struct irq_chip pxa_internal_chip_low = {
  63         .name           = "SC",
  64         .ack            = pxa_mask_low_irq,
  65         .mask           = pxa_mask_low_irq,
  66         .unmask         = pxa_unmask_low_irq,
  67         .set_wake       = pxa_set_wake,
  68 };
  69
  70 #if PXA_INTERNAL_IRQS > 32
  71
  72 /*
  73  * This is for the second set of internal IRQs as found on the PXA27x.
  74  */
  75
  76 static void pxa_mask_high_irq(unsigned int irq)
  77 {
  78         ICMR2 &= ~(1 << (irq - 32 + PXA_IRQ_SKIP));
  79 }
  80
  81 static void pxa_unmask_high_irq(unsigned int irq)
  82 {
  83         ICMR2 |= (1 << (irq - 32 + PXA_IRQ_SKIP));
  84 }
  85
  86 static struct irq_chip pxa_internal_chip_high = {
  87         .name           = "SC-hi",
  88         .ack            = pxa_mask_high_irq,
  89         .mask           = pxa_mask_high_irq,
  90         .unmask         = pxa_unmask_high_irq,
  91 };
  92
  93 #endif
  94
  95 /* Note that if an input/irq line ever gets changed to an output during
  96  * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
  97  */
  98 #ifdef CONFIG_PXA27x
  99
 100 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 101  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 102  */
 103 #define PXA27x_GPIO_NOWAKE_MASK \
 104         ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
 105 #define WAKEMASK(gpio) \
 106         (((gpio) <= 15) \
 107                 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
 108                 : ((gpio == 35) ? (1 << 24) : 0))
 109 #else
 110
 111 /* pxa 210, 250, 255, 26x:  gpios 0..15 can issue wakeups */
 112 #define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
 113 #endif
 114
 115 /*
 116  * PXA GPIO edge detection for IRQs:
 117  * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 118  * Use this instead of directly setting GRER/GFER.
 119  */
 120
 121 static long GPIO_IRQ_rising_edge[4];
 122 static long GPIO_IRQ_falling_edge[4];
 123 static long GPIO_IRQ_mask[4];
 124
 125 static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
 126 {
 127         int gpio, idx;
 128         u32 mask;
 129
 130         gpio = IRQ_TO_GPIO(irq);
 131         idx = gpio >> 5;
 132         mask = WAKEMASK(gpio);
 133
 134         if (type == IRQT_PROBE) {
 135             /* Don't mess with enabled GPIOs using preconfigured edges or
 136                GPIOs set to alternate function or to output during probe */
 137                 if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx] | GPDR(gpio)) &
 138                     GPIO_bit(gpio))
 139                         return 0;
 140                 if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
 141                         return 0;
 142                 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
 143         }
 144
 145         /* printk(KERN_DEBUG "IRQ%d (GPIO%d): ", irq, gpio); */
 146
 147         pxa_gpio_mode(gpio | GPIO_IN);
 148
 149         if (type & __IRQT_RISEDGE) {
 150                 /* printk("rising "); */
 151                 __set_bit (gpio, GPIO_IRQ_rising_edge);
 152                 PRER |= mask;
 153         } else {
 154                 __clear_bit (gpio, GPIO_IRQ_rising_edge);
 155                 PRER &= ~mask;
 156         }
 157
 158         if (type & __IRQT_FALEDGE) {
 159                 /* printk("falling "); */
 160                 __set_bit (gpio, GPIO_IRQ_falling_edge);
 161                 PFER |= mask;
 162         } else {
 163                 __clear_bit (gpio, GPIO_IRQ_falling_edge);
 164                 PFER &= ~mask;
 165         }
 166
 167         /* printk("edges\n"); */
 168
 169         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 170         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 171         return 0;
 172 }
 173
 174 /*
 175  * GPIO IRQs must be acknowledged.  This is for GPIO 0 and 1.
 176  */
 177
 178 static void pxa_ack_low_gpio(unsigned int irq)
 179 {
 180         GEDR0 = (1 << (irq - IRQ_GPIO0));
 181 }
 182
 183 static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
 184 {
 185         int     gpio = IRQ_TO_GPIO(irq);
 186         u32     mask = WAKEMASK(gpio);
 187
 188         if (!mask)
 189                 return -EINVAL;
 190
 191         if (on)
 192                 PWER |= mask;
 193         else
 194                 PWER &= ~mask;
 195         return 0;
 196 }
 197
 198
 199 static struct irq_chip pxa_low_gpio_chip = {
 200         .name           = "GPIO-l",
 201         .ack            = pxa_ack_low_gpio,
 202         .mask           = pxa_mask_low_irq,
 203         .unmask         = pxa_unmask_low_irq,
 204         .set_type       = pxa_gpio_irq_type,
 205         .set_wake       = pxa_set_gpio_wake,
 206 };
 207
 208 /*
 209  * Demux handler for GPIO>=2 edge detect interrupts
 210  */
 211
 212 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
 213 {
 214         unsigned int mask;
 215         int loop;
 216
 217         do {
 218                 loop = 0;
 219
 220                 mask = GEDR0 & ~3;
 221                 if (mask) {
 222                         GEDR0 = mask;
 223                         irq = IRQ_GPIO(2);
 224                         desc = irq_desc + irq;
 225                         mask >>= 2;
 226                         do {
 227                                 if (mask & 1)
 228                                         desc_handle_irq(irq, desc);
 229                                 irq++;
 230                                 desc++;
 231                                 mask >>= 1;
 232                         } while (mask);
 233                         loop = 1;
 234                 }
 235
 236                 mask = GEDR1;
 237                 if (mask) {
 238                         GEDR1 = mask;
 239                         irq = IRQ_GPIO(32);
 240                         desc = irq_desc + irq;
 241                         do {
 242                                 if (mask & 1)
 243                                         desc_handle_irq(irq, desc);
 244                                 irq++;
 245                                 desc++;
 246                                 mask >>= 1;
 247                         } while (mask);
 248                         loop = 1;
 249                 }
 250
 251                 mask = GEDR2;
 252                 if (mask) {
 253                         GEDR2 = mask;
 254                         irq = IRQ_GPIO(64);
 255                         desc = irq_desc + irq;
 256                         do {
 257                                 if (mask & 1)
 258                                         desc_handle_irq(irq, desc);
 259                                 irq++;
 260                                 desc++;
 261                                 mask >>= 1;
 262                         } while (mask);
 263                         loop = 1;
 264                 }
 265
 266 #if PXA_LAST_GPIO >= 96
 267                 mask = GEDR3;
 268                 if (mask) {
 269                         GEDR3 = mask;
 270                         irq = IRQ_GPIO(96);
 271                         desc = irq_desc + irq;
 272                         do {
 273                                 if (mask & 1)
 274                                         desc_handle_irq(irq, desc);
 275                                 irq++;
 276                                 desc++;
 277                                 mask >>= 1;
 278                         } while (mask);
 279                         loop = 1;
 280                 }
 281 #endif
 282         } while (loop);
 283 }
 284
 285 static void pxa_ack_muxed_gpio(unsigned int irq)
 286 {
 287         int gpio = irq - IRQ_GPIO(2) + 2;
 288         GEDR(gpio) = GPIO_bit(gpio);
 289 }
 290
 291 static void pxa_mask_muxed_gpio(unsigned int irq)
 292 {
 293         int gpio = irq - IRQ_GPIO(2) + 2;
 294         __clear_bit(gpio, GPIO_IRQ_mask);
 295         GRER(gpio) &= ~GPIO_bit(gpio);
 296         GFER(gpio) &= ~GPIO_bit(gpio);
 297 }
 298
 299 static void pxa_unmask_muxed_gpio(unsigned int irq)
 300 {
 301         int gpio = irq - IRQ_GPIO(2) + 2;
 302         int idx = gpio >> 5;
 303         __set_bit(gpio, GPIO_IRQ_mask);
 304         GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx];
 305         GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx];
 306 }
 307
 308 static struct irq_chip pxa_muxed_gpio_chip = {
 309         .name           = "GPIO",
 310         .ack            = pxa_ack_muxed_gpio,
 311         .mask           = pxa_mask_muxed_gpio,
 312         .unmask         = pxa_unmask_muxed_gpio,
 313         .set_type       = pxa_gpio_irq_type,
 314         .set_wake       = pxa_set_gpio_wake,
 315 };
 316
 317
 318 void __init pxa_init_irq(void)
 319 {
 320         int irq;
 321
 322         /* disable all IRQs */
 323         ICMR = 0;
 324
 325         /* all IRQs are IRQ, not FIQ */
 326         ICLR = 0;
 327
 328         /* clear all GPIO edge detects */
 329         GFER0 = 0;
 330         GFER1 = 0;
 331         GFER2 = 0;
 332         GRER0 = 0;
 333         GRER1 = 0;
 334         GRER2 = 0;
 335         GEDR0 = GEDR0;
 336         GEDR1 = GEDR1;
 337         GEDR2 = GEDR2;
 338
 339 #ifdef CONFIG_PXA27x
 340         /* And similarly for the extra regs on the PXA27x */
 341         ICMR2 = 0;
 342         ICLR2 = 0;
 343         GFER3 = 0;
 344         GRER3 = 0;
 345         GEDR3 = GEDR3;
 346 #endif
 347
 348         /* only unmasked interrupts kick us out of idle */
 349         ICCR = 1;
 350
 351         /* GPIO 0 and 1 must have their mask bit always set */
 352         GPIO_IRQ_mask[0] = 3;
 353
 354         for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
 355                 set_irq_chip(irq, &pxa_internal_chip_low);
 356                 set_irq_handler(irq, handle_level_irq);
 357                 set_irq_flags(irq, IRQF_VALID);
 358         }
 359
 360 #if PXA_INTERNAL_IRQS > 32
 361         for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
 362                 set_irq_chip(irq, &pxa_internal_chip_high);
 363                 set_irq_handler(irq, handle_level_irq);
 364                 set_irq_flags(irq, IRQF_VALID);
 365         }
 366 #endif
 367
 368         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
 369                 set_irq_chip(irq, &pxa_low_gpio_chip);
 370                 set_irq_handler(irq, handle_edge_irq);
 371                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 372         }
 373
 374         for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
 375                 set_irq_chip(irq, &pxa_muxed_gpio_chip);
 376                 set_irq_handler(irq, handle_edge_irq);
 377                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 378         }
 379
 380         /* Install handler for GPIO>=2 edge detect interrupts */
 381         set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
 382         set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
 383 }