include/asm-alpha/pci.h

   1 #ifndef __ALPHA_PCI_H
   2 #define __ALPHA_PCI_H
   3
   4 #ifdef __KERNEL__
   5
   6 #include <linux/spinlock.h>
   7 #include <linux/dma-mapping.h>
   8 #include <asm/scatterlist.h>
   9 #include <asm/machvec.h>
  10
  11 /*
  12  * The following structure is used to manage multiple PCI busses.
  13  */
  14
  15 struct pci_dev;
  16 struct pci_bus;
  17 struct resource;
  18 struct pci_iommu_arena;
  19 struct page;
  20
  21 /* A controller.  Used to manage multiple PCI busses.  */
  22
  23 struct pci_controller {
  24         struct pci_controller *next;
  25         struct pci_bus *bus;
  26         struct resource *io_space;
  27         struct resource *mem_space;
  28
  29         /* The following are for reporting to userland.  The invariant is
  30            that if we report a BWX-capable dense memory, we do not report
  31            a sparse memory at all, even if it exists.  */
  32         unsigned long sparse_mem_base;
  33         unsigned long dense_mem_base;
  34         unsigned long sparse_io_base;
  35         unsigned long dense_io_base;
  36
  37         /* This one's for the kernel only.  It's in KSEG somewhere.  */
  38         unsigned long config_space_base;
  39
  40         unsigned int index;
  41         /* For compatibility with current (as of July 2003) pciutils
  42            and XFree86. Eventually will be removed. */
  43         unsigned int need_domain_info;
  44
  45         struct pci_iommu_arena *sg_pci;
  46         struct pci_iommu_arena *sg_isa;
  47
  48         void *sysdata;
  49 };
  50
  51 /* Override the logic in pci_scan_bus for skipping already-configured
  52    bus numbers.  */
  53
  54 #define pcibios_assign_all_busses()     1
  55 #define pcibios_scan_all_fns(a, b)      0
  56
  57 #define PCIBIOS_MIN_IO          alpha_mv.min_io_address
  58 #define PCIBIOS_MIN_MEM         alpha_mv.min_mem_address
  59
  60 extern void pcibios_set_master(struct pci_dev *dev);
  61
  62 extern inline void pcibios_penalize_isa_irq(int irq, int active)
  63 {
  64         /* We don't do dynamic PCI IRQ allocation */
  65 }
  66
  67 /* IOMMU controls.  */
  68
  69 /* The PCI address space does not equal the physical memory address space.
  70    The networking and block device layers use this boolean for bounce buffer
  71    decisions.  */
  72 #define PCI_DMA_BUS_IS_PHYS  0
  73
  74 /* Allocate and map kernel buffer using consistent mode DMA for PCI
  75    device.  Returns non-NULL cpu-view pointer to the buffer if
  76    successful and sets *DMA_ADDRP to the pci side dma address as well,
  77    else DMA_ADDRP is undefined.  */
  78
  79 extern void *pci_alloc_consistent(struct pci_dev *, size_t, dma_addr_t *);
  80
  81 /* Free and unmap a consistent DMA buffer.  CPU_ADDR and DMA_ADDR must
  82    be values that were returned from pci_alloc_consistent.  SIZE must
  83    be the same as what as passed into pci_alloc_consistent.
  84    References to the memory and mappings associated with CPU_ADDR or
  85    DMA_ADDR past this call are illegal.  */
  86
  87 extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t);
  88
  89 /* Map a single buffer of the indicate size for PCI DMA in streaming mode.
  90    The 32-bit PCI bus mastering address to use is returned.  Once the device
  91    is given the dma address, the device owns this memory until either
  92    pci_unmap_single or pci_dma_sync_single_for_cpu is performed.  */
  93
  94 extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int);
  95
  96 /* Likewise, but for a page instead of an address.  */
  97 extern dma_addr_t pci_map_page(struct pci_dev *, struct page *,
  98                                unsigned long, size_t, int);
  99
 100 /* Test for pci_map_single or pci_map_page having generated an error.  */
 101
 102 static inline int
 103 pci_dma_mapping_error(dma_addr_t dma_addr)
 104 {
 105         return dma_addr == 0;
 106 }
 107
 108 /* Unmap a single streaming mode DMA translation.  The DMA_ADDR and
 109    SIZE must match what was provided for in a previous pci_map_single
 110    call.  All other usages are undefined.  After this call, reads by
 111    the cpu to the buffer are guaranteed to see whatever the device
 112    wrote there.  */
 113
 114 extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int);
 115 extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int);
 116
 117 /* pci_unmap_{single,page} is not a nop, thus... */
 118 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
 119         dma_addr_t ADDR_NAME;
 120 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
 121         __u32 LEN_NAME;
 122 #define pci_unmap_addr(PTR, ADDR_NAME)                  \
 123         ((PTR)->ADDR_NAME)
 124 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
 125         (((PTR)->ADDR_NAME) = (VAL))
 126 #define pci_unmap_len(PTR, LEN_NAME)                    \
 127         ((PTR)->LEN_NAME)
 128 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
 129         (((PTR)->LEN_NAME) = (VAL))
 130
 131 /* Map a set of buffers described by scatterlist in streaming mode for
 132    PCI DMA.  This is the scatter-gather version of the above
 133    pci_map_single interface.  Here the scatter gather list elements
 134    are each tagged with the appropriate PCI dma address and length.
 135    They are obtained via sg_dma_{address,length}(SG).
 136
 137    NOTE: An implementation may be able to use a smaller number of DMA
 138    address/length pairs than there are SG table elements.  (for
 139    example via virtual mapping capabilities) The routine returns the
 140    number of addr/length pairs actually used, at most nents.
 141
 142    Device ownership issues as mentioned above for pci_map_single are
 143    the same here.  */
 144
 145 extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
 146
 147 /* Unmap a set of streaming mode DMA translations.  Again, cpu read
 148    rules concerning calls here are the same as for pci_unmap_single()
 149    above.  */
 150
 151 extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
 152
 153 /* Make physical memory consistent for a single streaming mode DMA
 154    translation after a transfer and device currently has ownership
 155    of the buffer.
 156
 157    If you perform a pci_map_single() but wish to interrogate the
 158    buffer using the cpu, yet do not wish to teardown the PCI dma
 159    mapping, you must call this function before doing so.  At the next
 160    point you give the PCI dma address back to the card, you must first
 161    perform a pci_dma_sync_for_device, and then the device again owns
 162    the buffer.  */
 163
 164 static inline void
 165 pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr,
 166                             long size, int direction)
 167 {
 168         /* Nothing to do.  */
 169 }
 170
 171 static inline void
 172 pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr,
 173                                size_t size, int direction)
 174 {
 175         /* Nothing to do.  */
 176 }
 177
 178 /* Make physical memory consistent for a set of streaming mode DMA
 179    translations after a transfer.  The same as pci_dma_sync_single_*
 180    but for a scatter-gather list, same rules and usage.  */
 181
 182 static inline void
 183 pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg,
 184                         int nents, int direction)
 185 {
 186         /* Nothing to do.  */
 187 }
 188
 189 static inline void
 190 pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg,
 191                            int nents, int direction)
 192 {
 193         /* Nothing to do.  */
 194 }
 195
 196 /* Return whether the given PCI device DMA address mask can
 197    be supported properly.  For example, if your device can
 198    only drive the low 24-bits during PCI bus mastering, then
 199    you would pass 0x00ffffff as the mask to this function.  */
 200
 201 extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
 202
 203 #ifdef CONFIG_PCI
 204 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 205                                         enum pci_dma_burst_strategy *strat,
 206                                         unsigned long *strategy_parameter)
 207 {
 208         unsigned long cacheline_size;
 209         u8 byte;
 210
 211         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
 212         if (byte == 0)
 213                 cacheline_size = 1024;
 214         else
 215                 cacheline_size = (int) byte * 4;
 216
 217         *strat = PCI_DMA_BURST_BOUNDARY;
 218         *strategy_parameter = cacheline_size;
 219 }
 220 #endif
 221
 222 /* TODO: integrate with include/asm-generic/pci.h ? */
 223 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 224 {
 225         return channel ? 15 : 14;
 226 }
 227
 228 extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
 229                                     struct resource *);
 230
 231 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
 232                                     struct pci_bus_region *region);
 233
 234 static inline struct resource *
 235 pcibios_select_root(struct pci_dev *pdev, struct resource *res)
 236 {
 237         struct resource *root = NULL;
 238
 239         if (res->flags & IORESOURCE_IO)
 240                 root = &ioport_resource;
 241         if (res->flags & IORESOURCE_MEM)
 242                 root = &iomem_resource;
 243
 244         return root;
 245 }
 246
 247 #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 248
 249 static inline int pci_proc_domain(struct pci_bus *bus)
 250 {
 251         struct pci_controller *hose = bus->sysdata;
 252         return hose->need_domain_info;
 253 }
 254
 255 struct pci_dev *alpha_gendev_to_pci(struct device *dev);
 256
 257 #endif /* __KERNEL__ */
 258
 259 /* Values for the `which' argument to sys_pciconfig_iobase.  */
 260 #define IOBASE_HOSE             0
 261 #define IOBASE_SPARSE_MEM       1
 262 #define IOBASE_DENSE_MEM        2
 263 #define IOBASE_SPARSE_IO        3
 264 #define IOBASE_DENSE_IO         4
 265 #define IOBASE_ROOT_BUS         5
 266 #define IOBASE_FROM_HOSE        0x10000
 267
 268 extern struct pci_dev *isa_bridge;
 269
 270 #endif /* __ALPHA_PCI_H */