arch/mips/mipssim/sim_int.c

   1 /*
   2  * Copyright (C) 1999, 2005 MIPS Technologies, Inc.  All rights reserved.
   3  *
   4  *  This program is free software; you can distribute it and/or modify it
   5  *  under the terms of the GNU General Public License (Version 2) as
   6  *  published by the Free Software Foundation.
   7  *
   8  *  This program is distributed in the hope it will be useful, but WITHOUT
   9  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11  *  for more details.
  12  *
  13  *  You should have received a copy of the GNU General Public License along
  14  *  with this program; if not, write to the Free Software Foundation, Inc.,
  15  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16  *
  17  */
  18 #include <linux/init.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel_stat.h>
  23 #include <asm/mips-boards/simint.h>
  24 #include <asm/irq_cpu.h>
  25
  26 static inline int clz(unsigned long x)
  27 {
  28         __asm__(
  29         "       .set    push                                    \n"
  30         "       .set    mips32                                  \n"
  31         "       clz     %0, %1                                  \n"
  32         "       .set    pop                                     \n"
  33         : "=r" (x)
  34         : "r" (x));
  35
  36         return x;
  37 }
  38
  39 /*
  40  * Version of ffs that only looks at bits 12..15.
  41  */
  42 static inline unsigned int irq_ffs(unsigned int pending)
  43 {
  44 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
  45         return -clz(pending) + 31 - CAUSEB_IP;
  46 #else
  47         unsigned int a0 = 7;
  48         unsigned int t0;
  49
  50         t0 = s0 & 0xf000;
  51         t0 = t0 < 1;
  52         t0 = t0 << 2;
  53         a0 = a0 - t0;
  54         s0 = s0 << t0;
  55
  56         t0 = s0 & 0xc000;
  57         t0 = t0 < 1;
  58         t0 = t0 << 1;
  59         a0 = a0 - t0;
  60         s0 = s0 << t0;
  61
  62         t0 = s0 & 0x8000;
  63         t0 = t0 < 1;
  64         /* t0 = t0 << 2; */
  65         a0 = a0 - t0;
  66         /* s0 = s0 << t0; */
  67
  68         return a0;
  69 #endif
  70 }
  71
  72 asmlinkage void plat_irq_dispatch(void)
  73 {
  74         unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
  75         int irq;
  76
  77         irq = irq_ffs(pending);
  78
  79         if (irq > 0)
  80                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
  81         else
  82                 spurious_interrupt();
  83 }
  84
  85 void __init arch_init_irq(void)
  86 {
  87         mips_cpu_irq_init();
  88 }